diff options
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 60 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 20 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 21 |
3 files changed, 23 insertions, 78 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index dfc10b1baea0..e04de7a81592 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | |||
@@ -4132,18 +4132,12 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) | |||
4132 | gfx_v8_0_rlc_reset(adev); | 4132 | gfx_v8_0_rlc_reset(adev); |
4133 | gfx_v8_0_init_pg(adev); | 4133 | gfx_v8_0_init_pg(adev); |
4134 | 4134 | ||
4135 | if (!adev->pp_enabled) { | 4135 | |
4136 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) { | 4136 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { |
4137 | /* legacy rlc firmware loading */ | 4137 | /* legacy rlc firmware loading */ |
4138 | r = gfx_v8_0_rlc_load_microcode(adev); | 4138 | r = gfx_v8_0_rlc_load_microcode(adev); |
4139 | if (r) | 4139 | if (r) |
4140 | return r; | 4140 | return r; |
4141 | } else { | ||
4142 | r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, | ||
4143 | AMDGPU_UCODE_ID_RLC_G); | ||
4144 | if (r) | ||
4145 | return -EINVAL; | ||
4146 | } | ||
4147 | } | 4141 | } |
4148 | 4142 | ||
4149 | gfx_v8_0_rlc_start(adev); | 4143 | gfx_v8_0_rlc_start(adev); |
@@ -4959,43 +4953,15 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) | |||
4959 | if (!(adev->flags & AMD_IS_APU)) | 4953 | if (!(adev->flags & AMD_IS_APU)) |
4960 | gfx_v8_0_enable_gui_idle_interrupt(adev, false); | 4954 | gfx_v8_0_enable_gui_idle_interrupt(adev, false); |
4961 | 4955 | ||
4962 | if (!adev->pp_enabled) { | 4956 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { |
4963 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) { | ||
4964 | /* legacy firmware loading */ | 4957 | /* legacy firmware loading */ |
4965 | r = gfx_v8_0_cp_gfx_load_microcode(adev); | 4958 | r = gfx_v8_0_cp_gfx_load_microcode(adev); |
4966 | if (r) | 4959 | if (r) |
4967 | return r; | 4960 | return r; |
4968 | 4961 | ||
4969 | r = gfx_v8_0_cp_compute_load_microcode(adev); | 4962 | r = gfx_v8_0_cp_compute_load_microcode(adev); |
4970 | if (r) | 4963 | if (r) |
4971 | return r; | 4964 | return r; |
4972 | } else { | ||
4973 | r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, | ||
4974 | AMDGPU_UCODE_ID_CP_CE); | ||
4975 | if (r) | ||
4976 | return -EINVAL; | ||
4977 | |||
4978 | r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, | ||
4979 | AMDGPU_UCODE_ID_CP_PFP); | ||
4980 | if (r) | ||
4981 | return -EINVAL; | ||
4982 | |||
4983 | r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, | ||
4984 | AMDGPU_UCODE_ID_CP_ME); | ||
4985 | if (r) | ||
4986 | return -EINVAL; | ||
4987 | |||
4988 | if (adev->asic_type == CHIP_TOPAZ) { | ||
4989 | r = gfx_v8_0_cp_compute_load_microcode(adev); | ||
4990 | if (r) | ||
4991 | return r; | ||
4992 | } else { | ||
4993 | r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, | ||
4994 | AMDGPU_UCODE_ID_CP_MEC1); | ||
4995 | if (r) | ||
4996 | return -EINVAL; | ||
4997 | } | ||
4998 | } | ||
4999 | } | 4965 | } |
5000 | 4966 | ||
5001 | r = gfx_v8_0_cp_gfx_resume(adev); | 4967 | r = gfx_v8_0_cp_gfx_resume(adev); |
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index acdee3a4602c..67f375bfe452 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | |||
@@ -561,21 +561,11 @@ static int sdma_v2_4_start(struct amdgpu_device *adev) | |||
561 | { | 561 | { |
562 | int r; | 562 | int r; |
563 | 563 | ||
564 | if (!adev->pp_enabled) { | 564 | |
565 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) { | 565 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { |
566 | r = sdma_v2_4_load_microcode(adev); | 566 | r = sdma_v2_4_load_microcode(adev); |
567 | if (r) | 567 | if (r) |
568 | return r; | 568 | return r; |
569 | } else { | ||
570 | r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, | ||
571 | AMDGPU_UCODE_ID_SDMA0); | ||
572 | if (r) | ||
573 | return -EINVAL; | ||
574 | r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, | ||
575 | AMDGPU_UCODE_ID_SDMA1); | ||
576 | if (r) | ||
577 | return -EINVAL; | ||
578 | } | ||
579 | } | 569 | } |
580 | 570 | ||
581 | /* halt the engine before programing */ | 571 | /* halt the engine before programing */ |
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 72f31cc7df00..6d06f8eb659f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | |||
@@ -819,23 +819,12 @@ static int sdma_v3_0_load_microcode(struct amdgpu_device *adev) | |||
819 | */ | 819 | */ |
820 | static int sdma_v3_0_start(struct amdgpu_device *adev) | 820 | static int sdma_v3_0_start(struct amdgpu_device *adev) |
821 | { | 821 | { |
822 | int r, i; | 822 | int r; |
823 | 823 | ||
824 | if (!adev->pp_enabled) { | 824 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { |
825 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) { | 825 | r = sdma_v3_0_load_microcode(adev); |
826 | r = sdma_v3_0_load_microcode(adev); | 826 | if (r) |
827 | if (r) | 827 | return r; |
828 | return r; | ||
829 | } else { | ||
830 | for (i = 0; i < adev->sdma.num_instances; i++) { | ||
831 | r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, | ||
832 | (i == 0) ? | ||
833 | AMDGPU_UCODE_ID_SDMA0 : | ||
834 | AMDGPU_UCODE_ID_SDMA1); | ||
835 | if (r) | ||
836 | return -EINVAL; | ||
837 | } | ||
838 | } | ||
839 | } | 828 | } |
840 | 829 | ||
841 | /* disable sdma engine before programing it */ | 830 | /* disable sdma engine before programing it */ |