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-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore.c15
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore.h3
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c2
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c480
4 files changed, 499 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index b63271c09248..f97f8075bf04 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -884,6 +884,15 @@ static int uncore_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id
884 * each box has a different function id. 884 * each box has a different function id.
885 */ 885 */
886 pmu = &type->pmus[UNCORE_PCI_DEV_IDX(id->driver_data)]; 886 pmu = &type->pmus[UNCORE_PCI_DEV_IDX(id->driver_data)];
887 /* Knights Landing uses a common PCI device ID for multiple instances of
888 * an uncore PMU device type. There is only one entry per device type in
889 * the knl_uncore_pci_ids table inspite of multiple devices present for
890 * some device types. Hence PCI device idx would be 0 for all devices.
891 * So increment pmu pointer to point to an unused array element.
892 */
893 if (boot_cpu_data.x86_model == 87)
894 while (pmu->func_id >= 0)
895 pmu++;
887 if (pmu->func_id < 0) 896 if (pmu->func_id < 0)
888 pmu->func_id = pdev->devfn; 897 pmu->func_id = pdev->devfn;
889 else 898 else
@@ -983,6 +992,9 @@ static int __init uncore_pci_init(void)
983 case 61: /* Broadwell */ 992 case 61: /* Broadwell */
984 ret = bdw_uncore_pci_init(); 993 ret = bdw_uncore_pci_init();
985 break; 994 break;
995 case 87: /* Knights Landing */
996 ret = knl_uncore_pci_init();
997 break;
986 default: 998 default:
987 return 0; 999 return 0;
988 } 1000 }
@@ -1292,6 +1304,9 @@ static int __init uncore_cpu_init(void)
1292 case 86: /* BDX-DE */ 1304 case 86: /* BDX-DE */
1293 bdx_uncore_cpu_init(); 1305 bdx_uncore_cpu_init();
1294 break; 1306 break;
1307 case 87: /* Knights Landing */
1308 knl_uncore_cpu_init();
1309 break;
1295 default: 1310 default:
1296 return 0; 1311 return 0;
1297 } 1312 }
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
index 2f0a4a98e16b..07aa2d6bd710 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.h
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
@@ -338,6 +338,7 @@ int hsw_uncore_pci_init(void);
338int bdw_uncore_pci_init(void); 338int bdw_uncore_pci_init(void);
339void snb_uncore_cpu_init(void); 339void snb_uncore_cpu_init(void);
340void nhm_uncore_cpu_init(void); 340void nhm_uncore_cpu_init(void);
341int snb_pci2phy_map_init(int devid);
341 342
342/* perf_event_intel_uncore_snbep.c */ 343/* perf_event_intel_uncore_snbep.c */
343int snbep_uncore_pci_init(void); 344int snbep_uncore_pci_init(void);
@@ -348,6 +349,8 @@ int hswep_uncore_pci_init(void);
348void hswep_uncore_cpu_init(void); 349void hswep_uncore_cpu_init(void);
349int bdx_uncore_pci_init(void); 350int bdx_uncore_pci_init(void);
350void bdx_uncore_cpu_init(void); 351void bdx_uncore_cpu_init(void);
352int knl_uncore_pci_init(void);
353void knl_uncore_cpu_init(void);
351 354
352/* perf_event_intel_uncore_nhmex.c */ 355/* perf_event_intel_uncore_nhmex.c */
353void nhmex_uncore_cpu_init(void); 356void nhmex_uncore_cpu_init(void);
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c b/arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c
index 845256158a10..0b934820fafd 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c
@@ -417,7 +417,7 @@ static void snb_uncore_imc_event_del(struct perf_event *event, int flags)
417 } 417 }
418} 418}
419 419
420static int snb_pci2phy_map_init(int devid) 420int snb_pci2phy_map_init(int devid)
421{ 421{
422 struct pci_dev *dev = NULL; 422 struct pci_dev *dev = NULL;
423 struct pci2phy_map *map; 423 struct pci2phy_map *map;
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
index bfb96566311c..33acb884ccf1 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
@@ -209,31 +209,98 @@
209#define HSWEP_PCU_MSR_PMON_BOX_CTL 0x710 209#define HSWEP_PCU_MSR_PMON_BOX_CTL 0x710
210#define HSWEP_PCU_MSR_PMON_BOX_FILTER 0x715 210#define HSWEP_PCU_MSR_PMON_BOX_FILTER 0x715
211 211
212/* KNL Ubox */
213#define KNL_U_MSR_PMON_RAW_EVENT_MASK \
214 (SNBEP_U_MSR_PMON_RAW_EVENT_MASK | \
215 SNBEP_CBO_PMON_CTL_TID_EN)
216/* KNL CHA */
217#define KNL_CHA_MSR_OFFSET 0xc
218#define KNL_CHA_MSR_PMON_CTL_QOR (1 << 16)
219#define KNL_CHA_MSR_PMON_RAW_EVENT_MASK \
220 (SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK | \
221 KNL_CHA_MSR_PMON_CTL_QOR)
222#define KNL_CHA_MSR_PMON_BOX_FILTER_TID 0x1ff
223#define KNL_CHA_MSR_PMON_BOX_FILTER_STATE (7 << 18)
224#define KNL_CHA_MSR_PMON_BOX_FILTER_OP (0xfffffe2aULL << 32)
225
226/* KNL EDC/MC UCLK */
227#define KNL_UCLK_MSR_PMON_CTR0_LOW 0x400
228#define KNL_UCLK_MSR_PMON_CTL0 0x420
229#define KNL_UCLK_MSR_PMON_BOX_CTL 0x430
230#define KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW 0x44c
231#define KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL 0x454
232#define KNL_PMON_FIXED_CTL_EN 0x1
233
234/* KNL EDC */
235#define KNL_EDC0_ECLK_MSR_PMON_CTR0_LOW 0xa00
236#define KNL_EDC0_ECLK_MSR_PMON_CTL0 0xa20
237#define KNL_EDC0_ECLK_MSR_PMON_BOX_CTL 0xa30
238#define KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_LOW 0xa3c
239#define KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_CTL 0xa44
240
241/* KNL MC */
242#define KNL_MC0_CH0_MSR_PMON_CTR0_LOW 0xb00
243#define KNL_MC0_CH0_MSR_PMON_CTL0 0xb20
244#define KNL_MC0_CH0_MSR_PMON_BOX_CTL 0xb30
245#define KNL_MC0_CH0_MSR_PMON_FIXED_LOW 0xb3c
246#define KNL_MC0_CH0_MSR_PMON_FIXED_CTL 0xb44
247
248/* KNL IRP */
249#define KNL_IRP_PCI_PMON_BOX_CTL 0xf0
250#define KNL_IRP_PCI_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \
251 KNL_CHA_MSR_PMON_CTL_QOR)
252/* KNL PCU */
253#define KNL_PCU_PMON_CTL_EV_SEL_MASK 0x0000007f
254#define KNL_PCU_PMON_CTL_USE_OCC_CTR (1 << 7)
255#define KNL_PCU_MSR_PMON_CTL_TRESH_MASK 0x3f000000
256#define KNL_PCU_MSR_PMON_RAW_EVENT_MASK \
257 (KNL_PCU_PMON_CTL_EV_SEL_MASK | \
258 KNL_PCU_PMON_CTL_USE_OCC_CTR | \
259 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
260 SNBEP_PMON_CTL_EDGE_DET | \
261 SNBEP_CBO_PMON_CTL_TID_EN | \
262 SNBEP_PMON_CTL_EV_SEL_EXT | \
263 SNBEP_PMON_CTL_INVERT | \
264 KNL_PCU_MSR_PMON_CTL_TRESH_MASK | \
265 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
266 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
212 267
213DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7"); 268DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
269DEFINE_UNCORE_FORMAT_ATTR(event2, event, "config:0-6");
214DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21"); 270DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21");
271DEFINE_UNCORE_FORMAT_ATTR(use_occ_ctr, use_occ_ctr, "config:7");
215DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15"); 272DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
273DEFINE_UNCORE_FORMAT_ATTR(qor, qor, "config:16");
216DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18"); 274DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
217DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19"); 275DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19");
218DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23"); 276DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
219DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31"); 277DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31");
278DEFINE_UNCORE_FORMAT_ATTR(thresh6, thresh, "config:24-29");
220DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28"); 279DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28");
221DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15"); 280DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
222DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30"); 281DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
223DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51"); 282DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
283DEFINE_UNCORE_FORMAT_ATTR(occ_edge_det, occ_edge_det, "config:31");
224DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4"); 284DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4");
225DEFINE_UNCORE_FORMAT_ATTR(filter_tid2, filter_tid, "config1:0"); 285DEFINE_UNCORE_FORMAT_ATTR(filter_tid2, filter_tid, "config1:0");
226DEFINE_UNCORE_FORMAT_ATTR(filter_tid3, filter_tid, "config1:0-5"); 286DEFINE_UNCORE_FORMAT_ATTR(filter_tid3, filter_tid, "config1:0-5");
287DEFINE_UNCORE_FORMAT_ATTR(filter_tid4, filter_tid, "config1:0-8");
227DEFINE_UNCORE_FORMAT_ATTR(filter_cid, filter_cid, "config1:5"); 288DEFINE_UNCORE_FORMAT_ATTR(filter_cid, filter_cid, "config1:5");
228DEFINE_UNCORE_FORMAT_ATTR(filter_link, filter_link, "config1:5-8"); 289DEFINE_UNCORE_FORMAT_ATTR(filter_link, filter_link, "config1:5-8");
229DEFINE_UNCORE_FORMAT_ATTR(filter_link2, filter_link, "config1:6-8"); 290DEFINE_UNCORE_FORMAT_ATTR(filter_link2, filter_link, "config1:6-8");
291DEFINE_UNCORE_FORMAT_ATTR(filter_link3, filter_link, "config1:12");
230DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17"); 292DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17");
231DEFINE_UNCORE_FORMAT_ATTR(filter_nid2, filter_nid, "config1:32-47"); 293DEFINE_UNCORE_FORMAT_ATTR(filter_nid2, filter_nid, "config1:32-47");
232DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22"); 294DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22");
233DEFINE_UNCORE_FORMAT_ATTR(filter_state2, filter_state, "config1:17-22"); 295DEFINE_UNCORE_FORMAT_ATTR(filter_state2, filter_state, "config1:17-22");
234DEFINE_UNCORE_FORMAT_ATTR(filter_state3, filter_state, "config1:17-23"); 296DEFINE_UNCORE_FORMAT_ATTR(filter_state3, filter_state, "config1:17-23");
297DEFINE_UNCORE_FORMAT_ATTR(filter_state4, filter_state, "config1:18-20");
298DEFINE_UNCORE_FORMAT_ATTR(filter_local, filter_local, "config1:33");
299DEFINE_UNCORE_FORMAT_ATTR(filter_all_op, filter_all_op, "config1:35");
300DEFINE_UNCORE_FORMAT_ATTR(filter_nnm, filter_nnm, "config1:37");
235DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31"); 301DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31");
236DEFINE_UNCORE_FORMAT_ATTR(filter_opc2, filter_opc, "config1:52-60"); 302DEFINE_UNCORE_FORMAT_ATTR(filter_opc2, filter_opc, "config1:52-60");
303DEFINE_UNCORE_FORMAT_ATTR(filter_opc3, filter_opc, "config1:41-60");
237DEFINE_UNCORE_FORMAT_ATTR(filter_nc, filter_nc, "config1:62"); 304DEFINE_UNCORE_FORMAT_ATTR(filter_nc, filter_nc, "config1:62");
238DEFINE_UNCORE_FORMAT_ATTR(filter_c6, filter_c6, "config1:61"); 305DEFINE_UNCORE_FORMAT_ATTR(filter_c6, filter_c6, "config1:61");
239DEFINE_UNCORE_FORMAT_ATTR(filter_isoc, filter_isoc, "config1:63"); 306DEFINE_UNCORE_FORMAT_ATTR(filter_isoc, filter_isoc, "config1:63");
@@ -1729,6 +1796,419 @@ int ivbep_uncore_pci_init(void)
1729} 1796}
1730/* end of IvyTown uncore support */ 1797/* end of IvyTown uncore support */
1731 1798
1799/* KNL uncore support */
1800static struct attribute *knl_uncore_ubox_formats_attr[] = {
1801 &format_attr_event.attr,
1802 &format_attr_umask.attr,
1803 &format_attr_edge.attr,
1804 &format_attr_tid_en.attr,
1805 &format_attr_inv.attr,
1806 &format_attr_thresh5.attr,
1807 NULL,
1808};
1809
1810static struct attribute_group knl_uncore_ubox_format_group = {
1811 .name = "format",
1812 .attrs = knl_uncore_ubox_formats_attr,
1813};
1814
1815static struct intel_uncore_type knl_uncore_ubox = {
1816 .name = "ubox",
1817 .num_counters = 2,
1818 .num_boxes = 1,
1819 .perf_ctr_bits = 48,
1820 .fixed_ctr_bits = 48,
1821 .perf_ctr = HSWEP_U_MSR_PMON_CTR0,
1822 .event_ctl = HSWEP_U_MSR_PMON_CTL0,
1823 .event_mask = KNL_U_MSR_PMON_RAW_EVENT_MASK,
1824 .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR,
1825 .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL,
1826 .ops = &snbep_uncore_msr_ops,
1827 .format_group = &knl_uncore_ubox_format_group,
1828};
1829
1830static struct attribute *knl_uncore_cha_formats_attr[] = {
1831 &format_attr_event.attr,
1832 &format_attr_umask.attr,
1833 &format_attr_qor.attr,
1834 &format_attr_edge.attr,
1835 &format_attr_tid_en.attr,
1836 &format_attr_inv.attr,
1837 &format_attr_thresh8.attr,
1838 &format_attr_filter_tid4.attr,
1839 &format_attr_filter_link3.attr,
1840 &format_attr_filter_state4.attr,
1841 &format_attr_filter_local.attr,
1842 &format_attr_filter_all_op.attr,
1843 &format_attr_filter_nnm.attr,
1844 &format_attr_filter_opc3.attr,
1845 &format_attr_filter_nc.attr,
1846 &format_attr_filter_isoc.attr,
1847 NULL,
1848};
1849
1850static struct attribute_group knl_uncore_cha_format_group = {
1851 .name = "format",
1852 .attrs = knl_uncore_cha_formats_attr,
1853};
1854
1855static struct event_constraint knl_uncore_cha_constraints[] = {
1856 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
1857 UNCORE_EVENT_CONSTRAINT(0x1f, 0x1),
1858 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
1859 EVENT_CONSTRAINT_END
1860};
1861
1862static struct extra_reg knl_uncore_cha_extra_regs[] = {
1863 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
1864 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
1865 SNBEP_CBO_EVENT_EXTRA_REG(0x3d, 0xff, 0x2),
1866 SNBEP_CBO_EVENT_EXTRA_REG(0x35, 0xff, 0x4),
1867 SNBEP_CBO_EVENT_EXTRA_REG(0x36, 0xff, 0x4),
1868 EVENT_EXTRA_END
1869};
1870
1871static u64 knl_cha_filter_mask(int fields)
1872{
1873 u64 mask = 0;
1874
1875 if (fields & 0x1)
1876 mask |= KNL_CHA_MSR_PMON_BOX_FILTER_TID;
1877 if (fields & 0x2)
1878 mask |= KNL_CHA_MSR_PMON_BOX_FILTER_STATE;
1879 if (fields & 0x4)
1880 mask |= KNL_CHA_MSR_PMON_BOX_FILTER_OP;
1881 return mask;
1882}
1883
1884static struct event_constraint *
1885knl_cha_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
1886{
1887 return __snbep_cbox_get_constraint(box, event, knl_cha_filter_mask);
1888}
1889
1890static int knl_cha_hw_config(struct intel_uncore_box *box,
1891 struct perf_event *event)
1892{
1893 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1894 struct extra_reg *er;
1895 int idx = 0;
1896
1897 for (er = knl_uncore_cha_extra_regs; er->msr; er++) {
1898 if (er->event != (event->hw.config & er->config_mask))
1899 continue;
1900 idx |= er->idx;
1901 }
1902
1903 if (idx) {
1904 reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 +
1905 KNL_CHA_MSR_OFFSET * box->pmu->pmu_idx;
1906 reg1->config = event->attr.config1 & knl_cha_filter_mask(idx);
1907 reg1->idx = idx;
1908 }
1909 return 0;
1910}
1911
1912static void hswep_cbox_enable_event(struct intel_uncore_box *box,
1913 struct perf_event *event);
1914
1915static struct intel_uncore_ops knl_uncore_cha_ops = {
1916 .init_box = snbep_uncore_msr_init_box,
1917 .disable_box = snbep_uncore_msr_disable_box,
1918 .enable_box = snbep_uncore_msr_enable_box,
1919 .disable_event = snbep_uncore_msr_disable_event,
1920 .enable_event = hswep_cbox_enable_event,
1921 .read_counter = uncore_msr_read_counter,
1922 .hw_config = knl_cha_hw_config,
1923 .get_constraint = knl_cha_get_constraint,
1924 .put_constraint = snbep_cbox_put_constraint,
1925};
1926
1927static struct intel_uncore_type knl_uncore_cha = {
1928 .name = "cha",
1929 .num_counters = 4,
1930 .num_boxes = 38,
1931 .perf_ctr_bits = 48,
1932 .event_ctl = HSWEP_C0_MSR_PMON_CTL0,
1933 .perf_ctr = HSWEP_C0_MSR_PMON_CTR0,
1934 .event_mask = KNL_CHA_MSR_PMON_RAW_EVENT_MASK,
1935 .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL,
1936 .msr_offset = KNL_CHA_MSR_OFFSET,
1937 .num_shared_regs = 1,
1938 .constraints = knl_uncore_cha_constraints,
1939 .ops = &knl_uncore_cha_ops,
1940 .format_group = &knl_uncore_cha_format_group,
1941};
1942
1943static struct attribute *knl_uncore_pcu_formats_attr[] = {
1944 &format_attr_event2.attr,
1945 &format_attr_use_occ_ctr.attr,
1946 &format_attr_occ_sel.attr,
1947 &format_attr_edge.attr,
1948 &format_attr_tid_en.attr,
1949 &format_attr_inv.attr,
1950 &format_attr_thresh6.attr,
1951 &format_attr_occ_invert.attr,
1952 &format_attr_occ_edge_det.attr,
1953 NULL,
1954};
1955
1956static struct attribute_group knl_uncore_pcu_format_group = {
1957 .name = "format",
1958 .attrs = knl_uncore_pcu_formats_attr,
1959};
1960
1961static struct intel_uncore_type knl_uncore_pcu = {
1962 .name = "pcu",
1963 .num_counters = 4,
1964 .num_boxes = 1,
1965 .perf_ctr_bits = 48,
1966 .perf_ctr = HSWEP_PCU_MSR_PMON_CTR0,
1967 .event_ctl = HSWEP_PCU_MSR_PMON_CTL0,
1968 .event_mask = KNL_PCU_MSR_PMON_RAW_EVENT_MASK,
1969 .box_ctl = HSWEP_PCU_MSR_PMON_BOX_CTL,
1970 .ops = &snbep_uncore_msr_ops,
1971 .format_group = &knl_uncore_pcu_format_group,
1972};
1973
1974static struct intel_uncore_type *knl_msr_uncores[] = {
1975 &knl_uncore_ubox,
1976 &knl_uncore_cha,
1977 &knl_uncore_pcu,
1978 NULL,
1979};
1980
1981void knl_uncore_cpu_init(void)
1982{
1983 uncore_msr_uncores = knl_msr_uncores;
1984}
1985
1986static void knl_uncore_imc_enable_box(struct intel_uncore_box *box)
1987{
1988 struct pci_dev *pdev = box->pci_dev;
1989 int box_ctl = uncore_pci_box_ctl(box);
1990
1991 pci_write_config_dword(pdev, box_ctl, 0);
1992}
1993
1994static void knl_uncore_imc_enable_event(struct intel_uncore_box *box,
1995 struct perf_event *event)
1996{
1997 struct pci_dev *pdev = box->pci_dev;
1998 struct hw_perf_event *hwc = &event->hw;
1999
2000 if ((event->attr.config & SNBEP_PMON_CTL_EV_SEL_MASK)
2001 == UNCORE_FIXED_EVENT)
2002 pci_write_config_dword(pdev, hwc->config_base,
2003 hwc->config | KNL_PMON_FIXED_CTL_EN);
2004 else
2005 pci_write_config_dword(pdev, hwc->config_base,
2006 hwc->config | SNBEP_PMON_CTL_EN);
2007}
2008
2009static struct intel_uncore_ops knl_uncore_imc_ops = {
2010 .init_box = snbep_uncore_pci_init_box,
2011 .disable_box = snbep_uncore_pci_disable_box,
2012 .enable_box = knl_uncore_imc_enable_box,
2013 .read_counter = snbep_uncore_pci_read_counter,
2014 .enable_event = knl_uncore_imc_enable_event,
2015 .disable_event = snbep_uncore_pci_disable_event,
2016};
2017
2018static struct intel_uncore_type knl_uncore_imc_uclk = {
2019 .name = "imc_uclk",
2020 .num_counters = 4,
2021 .num_boxes = 2,
2022 .perf_ctr_bits = 48,
2023 .fixed_ctr_bits = 48,
2024 .perf_ctr = KNL_UCLK_MSR_PMON_CTR0_LOW,
2025 .event_ctl = KNL_UCLK_MSR_PMON_CTL0,
2026 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
2027 .fixed_ctr = KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW,
2028 .fixed_ctl = KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL,
2029 .box_ctl = KNL_UCLK_MSR_PMON_BOX_CTL,
2030 .ops = &knl_uncore_imc_ops,
2031 .format_group = &snbep_uncore_format_group,
2032};
2033
2034static struct intel_uncore_type knl_uncore_imc_dclk = {
2035 .name = "imc",
2036 .num_counters = 4,
2037 .num_boxes = 6,
2038 .perf_ctr_bits = 48,
2039 .fixed_ctr_bits = 48,
2040 .perf_ctr = KNL_MC0_CH0_MSR_PMON_CTR0_LOW,
2041 .event_ctl = KNL_MC0_CH0_MSR_PMON_CTL0,
2042 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
2043 .fixed_ctr = KNL_MC0_CH0_MSR_PMON_FIXED_LOW,
2044 .fixed_ctl = KNL_MC0_CH0_MSR_PMON_FIXED_CTL,
2045 .box_ctl = KNL_MC0_CH0_MSR_PMON_BOX_CTL,
2046 .ops = &knl_uncore_imc_ops,
2047 .format_group = &snbep_uncore_format_group,
2048};
2049
2050static struct intel_uncore_type knl_uncore_edc_uclk = {
2051 .name = "edc_uclk",
2052 .num_counters = 4,
2053 .num_boxes = 8,
2054 .perf_ctr_bits = 48,
2055 .fixed_ctr_bits = 48,
2056 .perf_ctr = KNL_UCLK_MSR_PMON_CTR0_LOW,
2057 .event_ctl = KNL_UCLK_MSR_PMON_CTL0,
2058 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
2059 .fixed_ctr = KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW,
2060 .fixed_ctl = KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL,
2061 .box_ctl = KNL_UCLK_MSR_PMON_BOX_CTL,
2062 .ops = &knl_uncore_imc_ops,
2063 .format_group = &snbep_uncore_format_group,
2064};
2065
2066static struct intel_uncore_type knl_uncore_edc_eclk = {
2067 .name = "edc_eclk",
2068 .num_counters = 4,
2069 .num_boxes = 8,
2070 .perf_ctr_bits = 48,
2071 .fixed_ctr_bits = 48,
2072 .perf_ctr = KNL_EDC0_ECLK_MSR_PMON_CTR0_LOW,
2073 .event_ctl = KNL_EDC0_ECLK_MSR_PMON_CTL0,
2074 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
2075 .fixed_ctr = KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_LOW,
2076 .fixed_ctl = KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_CTL,
2077 .box_ctl = KNL_EDC0_ECLK_MSR_PMON_BOX_CTL,
2078 .ops = &knl_uncore_imc_ops,
2079 .format_group = &snbep_uncore_format_group,
2080};
2081
2082static struct event_constraint knl_uncore_m2pcie_constraints[] = {
2083 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
2084 EVENT_CONSTRAINT_END
2085};
2086
2087static struct intel_uncore_type knl_uncore_m2pcie = {
2088 .name = "m2pcie",
2089 .num_counters = 4,
2090 .num_boxes = 1,
2091 .perf_ctr_bits = 48,
2092 .constraints = knl_uncore_m2pcie_constraints,
2093 SNBEP_UNCORE_PCI_COMMON_INIT(),
2094};
2095
2096static struct attribute *knl_uncore_irp_formats_attr[] = {
2097 &format_attr_event.attr,
2098 &format_attr_umask.attr,
2099 &format_attr_qor.attr,
2100 &format_attr_edge.attr,
2101 &format_attr_inv.attr,
2102 &format_attr_thresh8.attr,
2103 NULL,
2104};
2105
2106static struct attribute_group knl_uncore_irp_format_group = {
2107 .name = "format",
2108 .attrs = knl_uncore_irp_formats_attr,
2109};
2110
2111static struct intel_uncore_type knl_uncore_irp = {
2112 .name = "irp",
2113 .num_counters = 2,
2114 .num_boxes = 1,
2115 .perf_ctr_bits = 48,
2116 .perf_ctr = SNBEP_PCI_PMON_CTR0,
2117 .event_ctl = SNBEP_PCI_PMON_CTL0,
2118 .event_mask = KNL_IRP_PCI_PMON_RAW_EVENT_MASK,
2119 .box_ctl = KNL_IRP_PCI_PMON_BOX_CTL,
2120 .ops = &snbep_uncore_pci_ops,
2121 .format_group = &knl_uncore_irp_format_group,
2122};
2123
2124enum {
2125 KNL_PCI_UNCORE_MC_UCLK,
2126 KNL_PCI_UNCORE_MC_DCLK,
2127 KNL_PCI_UNCORE_EDC_UCLK,
2128 KNL_PCI_UNCORE_EDC_ECLK,
2129 KNL_PCI_UNCORE_M2PCIE,
2130 KNL_PCI_UNCORE_IRP,
2131};
2132
2133static struct intel_uncore_type *knl_pci_uncores[] = {
2134 [KNL_PCI_UNCORE_MC_UCLK] = &knl_uncore_imc_uclk,
2135 [KNL_PCI_UNCORE_MC_DCLK] = &knl_uncore_imc_dclk,
2136 [KNL_PCI_UNCORE_EDC_UCLK] = &knl_uncore_edc_uclk,
2137 [KNL_PCI_UNCORE_EDC_ECLK] = &knl_uncore_edc_eclk,
2138 [KNL_PCI_UNCORE_M2PCIE] = &knl_uncore_m2pcie,
2139 [KNL_PCI_UNCORE_IRP] = &knl_uncore_irp,
2140 NULL,
2141};
2142
2143/*
2144 * KNL uses a common PCI device ID for multiple instances of an Uncore PMU
2145 * device type. prior to KNL, each instance of a PMU device type had a unique
2146 * device ID.
2147 *
2148 * PCI Device ID Uncore PMU Devices
2149 * ----------------------------------
2150 * 0x7841 MC0 UClk, MC1 UClk
2151 * 0x7843 MC0 DClk CH 0, MC0 DClk CH 1, MC0 DClk CH 2,
2152 * MC1 DClk CH 0, MC1 DClk CH 1, MC1 DClk CH 2
2153 * 0x7833 EDC0 UClk, EDC1 UClk, EDC2 UClk, EDC3 UClk,
2154 * EDC4 UClk, EDC5 UClk, EDC6 UClk, EDC7 UClk
2155 * 0x7835 EDC0 EClk, EDC1 EClk, EDC2 EClk, EDC3 EClk,
2156 * EDC4 EClk, EDC5 EClk, EDC6 EClk, EDC7 EClk
2157 * 0x7817 M2PCIe
2158 * 0x7814 IRP
2159*/
2160
2161static const struct pci_device_id knl_uncore_pci_ids[] = {
2162 { /* MC UClk */
2163 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7841),
2164 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_MC_UCLK, 0),
2165 },
2166 { /* MC DClk Channel */
2167 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843),
2168 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_MC_DCLK, 0),
2169 },
2170 { /* EDC UClk */
2171 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2172 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_EDC_UCLK, 0),
2173 },
2174 { /* EDC EClk */
2175 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2176 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_EDC_ECLK, 0),
2177 },
2178 { /* M2PCIe */
2179 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7817),
2180 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_M2PCIE, 0),
2181 },
2182 { /* IRP */
2183 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7814),
2184 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_IRP, 0),
2185 },
2186 { /* end: all zeroes */ }
2187};
2188
2189static struct pci_driver knl_uncore_pci_driver = {
2190 .name = "knl_uncore",
2191 .id_table = knl_uncore_pci_ids,
2192};
2193
2194int knl_uncore_pci_init(void)
2195{
2196 int ret;
2197
2198 /* All KNL PCI based PMON units are on the same PCI bus except IRP */
2199 ret = snb_pci2phy_map_init(0x7814); /* IRP */
2200 if (ret)
2201 return ret;
2202 ret = snb_pci2phy_map_init(0x7817); /* M2PCIe */
2203 if (ret)
2204 return ret;
2205 uncore_pci_uncores = knl_pci_uncores;
2206 uncore_pci_driver = &knl_uncore_pci_driver;
2207 return 0;
2208}
2209
2210/* end of KNL uncore support */
2211
1732/* Haswell-EP uncore support */ 2212/* Haswell-EP uncore support */
1733static struct attribute *hswep_uncore_ubox_formats_attr[] = { 2213static struct attribute *hswep_uncore_ubox_formats_attr[] = {
1734 &format_attr_event.attr, 2214 &format_attr_event.attr,
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 18:51:28 -0400