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-rw-r--r--drivers/gpu/drm/i915/gvt/handlers.c31
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h13
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h128
-rw-r--r--drivers/gpu/drm/i915/intel_display.c5
-rw-r--r--drivers/gpu/drm/i915/intel_runtime_pm.c302
5 files changed, 361 insertions, 118 deletions
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 6b50f850dc28..749c704ca304 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1287,12 +1287,13 @@ static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1287{ 1287{
1288 write_vreg(vgpu, offset, p_data, bytes); 1288 write_vreg(vgpu, offset, p_data, bytes);
1289 1289
1290 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL)) 1290 if (vgpu_vreg(vgpu, offset) &
1291 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL))
1291 vgpu_vreg(vgpu, offset) |= 1292 vgpu_vreg(vgpu, offset) |=
1292 HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); 1293 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1293 else 1294 else
1294 vgpu_vreg(vgpu, offset) &= 1295 vgpu_vreg(vgpu, offset) &=
1295 ~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); 1296 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1296 return 0; 1297 return 0;
1297} 1298}
1298 1299
@@ -2443,17 +2444,10 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
2443 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2444 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
2444 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2445 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
2445 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2446 MMIO_D(GEN6_PMINTRMSK, D_ALL);
2446 /* 2447 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
2447 * Use an arbitrary power well controlled by the PWR_WELL_CTL 2448 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
2448 * register. 2449 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
2449 */ 2450 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
2450 MMIO_DH(HSW_PWR_WELL_CTL_BIOS(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2451 power_well_ctl_mmio_write);
2452 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2453 power_well_ctl_mmio_write);
2454 MMIO_DH(HSW_PWR_WELL_CTL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write);
2455 MMIO_DH(HSW_PWR_WELL_CTL_DEBUG(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2456 power_well_ctl_mmio_write);
2457 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2451 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
2458 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2452 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
2459 2453
@@ -2804,13 +2798,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
2804 MMIO_F(_MMIO(_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2798 MMIO_F(_MMIO(_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2805 dp_aux_ch_ctl_mmio_write); 2799 dp_aux_ch_ctl_mmio_write);
2806 2800
2807 /* 2801 MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
2808 * Use an arbitrary power well controlled by the PWR_WELL_CTL 2802 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
2809 * register.
2810 */
2811 MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS);
2812 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL,
2813 skl_power_well_ctl_write);
2814 2803
2815 MMIO_D(_MMIO(0xa210), D_SKL_PLUS); 2804 MMIO_D(_MMIO(0xa210), D_SKL_PLUS);
2816 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2805 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6fa61403d456..0b10a30b7d96 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -867,6 +867,13 @@ struct i915_power_well_ops {
867 struct i915_power_well *power_well); 867 struct i915_power_well *power_well);
868}; 868};
869 869
870struct i915_power_well_regs {
871 i915_reg_t bios;
872 i915_reg_t driver;
873 i915_reg_t kvmr;
874 i915_reg_t debug;
875};
876
870/* Power well structure for haswell */ 877/* Power well structure for haswell */
871struct i915_power_well_desc { 878struct i915_power_well_desc {
872 const char *name; 879 const char *name;
@@ -890,6 +897,12 @@ struct i915_power_well_desc {
890 enum dpio_phy phy; 897 enum dpio_phy phy;
891 } bxt; 898 } bxt;
892 struct { 899 struct {
900 const struct i915_power_well_regs *regs;
901 /*
902 * request/status flag index in the power well
903 * constrol/status registers.
904 */
905 u8 idx;
893 /* Mask of pipes whose IRQ logic is backed by the pw */ 906 /* Mask of pipes whose IRQ logic is backed by the pw */
894 u8 irq_pipe_mask; 907 u8 irq_pipe_mask;
895 /* The pw is backing the VGA functionality */ 908 /* The pw is backing the VGA functionality */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ed30b4f8b948..4f5eb49934b4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8925,46 +8925,78 @@ enum {
8925#define HSW_AUD_CHICKENBIT _MMIO(0x65f10) 8925#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
8926#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) 8926#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
8927 8927
8928/* HSW Power Wells */
8929#define _HSW_PWR_WELL_CTL1 0x45400
8930#define _HSW_PWR_WELL_CTL2 0x45404
8931#define _HSW_PWR_WELL_CTL3 0x45408
8932#define _HSW_PWR_WELL_CTL4 0x4540C
8933
8934#define _ICL_PWR_WELL_CTL_AUX1 0x45440
8935#define _ICL_PWR_WELL_CTL_AUX2 0x45444
8936#define _ICL_PWR_WELL_CTL_AUX4 0x4544C
8937
8938#define _ICL_PWR_WELL_CTL_DDI1 0x45450
8939#define _ICL_PWR_WELL_CTL_DDI2 0x45454
8940#define _ICL_PWR_WELL_CTL_DDI4 0x4545C
8941
8942/* 8928/*
8943 * Each power well control register contains up to 16 (request, status) HW 8929 * HSW - ICL power wells
8944 * flag tuples. The register index and HW flag shift is determined by the 8930 *
8945 * power well ID (see i915_power_well_id). There are 4 possible sources of 8931 * Platforms have up to 3 power well control register sets, each set
8946 * power well requests each source having its own set of control registers: 8932 * controlling up to 16 power wells via a request/status HW flag tuple:
8947 * BIOS, DRIVER, KVMR, DEBUG. 8933 * - main (HSW_PWR_WELL_CTL[1-4])
8934 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
8935 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
8936 * Each control register set consists of up to 4 registers used by different
8937 * sources that can request a power well to be enabled:
8938 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
8939 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
8940 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
8941 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
8948 */ 8942 */
8949#define _HSW_PW_REG_IDX(pw) ((pw) >> 4) 8943#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
8950#define _HSW_PW_SHIFT(pw) (((pw) & 0xf) * 2) 8944#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
8951#define HSW_PWR_WELL_CTL_BIOS(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ 8945#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
8952 _HSW_PWR_WELL_CTL1, \ 8946#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
8953 _ICL_PWR_WELL_CTL_AUX1, \ 8947#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
8954 _ICL_PWR_WELL_CTL_DDI1)) 8948#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
8955#define HSW_PWR_WELL_CTL_DRIVER(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ 8949
8956 _HSW_PWR_WELL_CTL2, \ 8950/* HSW/BDW power well */
8957 _ICL_PWR_WELL_CTL_AUX2, \ 8951#define HSW_PW_CTL_IDX_GLOBAL 15
8958 _ICL_PWR_WELL_CTL_DDI2)) 8952
8959/* KVMR doesn't have a reg for AUX or DDI power well control */ 8953/* SKL/BXT/GLK/CNL power wells */
8960#define HSW_PWR_WELL_CTL_KVMR _MMIO(_HSW_PWR_WELL_CTL3) 8954#define SKL_PW_CTL_IDX_PW_2 15
8961#define HSW_PWR_WELL_CTL_DEBUG(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ 8955#define SKL_PW_CTL_IDX_PW_1 14
8962 _HSW_PWR_WELL_CTL4, \ 8956#define CNL_PW_CTL_IDX_AUX_F 12
8963 _ICL_PWR_WELL_CTL_AUX4, \ 8957#define CNL_PW_CTL_IDX_AUX_D 11
8964 _ICL_PWR_WELL_CTL_DDI4)) 8958#define GLK_PW_CTL_IDX_AUX_C 10
8965 8959#define GLK_PW_CTL_IDX_AUX_B 9
8966#define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1)) 8960#define GLK_PW_CTL_IDX_AUX_A 8
8967#define HSW_PWR_WELL_CTL_STATE(pw) (1 << _HSW_PW_SHIFT(pw)) 8961#define CNL_PW_CTL_IDX_DDI_F 6
8962#define SKL_PW_CTL_IDX_DDI_D 4
8963#define SKL_PW_CTL_IDX_DDI_C 3
8964#define SKL_PW_CTL_IDX_DDI_B 2
8965#define SKL_PW_CTL_IDX_DDI_A_E 1
8966#define GLK_PW_CTL_IDX_DDI_A 1
8967#define SKL_PW_CTL_IDX_MISC_IO 0
8968
8969/* ICL - power wells */
8970#define ICL_PW_CTL_IDX_PW_4 3
8971#define ICL_PW_CTL_IDX_PW_3 2
8972#define ICL_PW_CTL_IDX_PW_2 1
8973#define ICL_PW_CTL_IDX_PW_1 0
8974
8975#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
8976#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
8977#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
8978#define ICL_PW_CTL_IDX_AUX_TBT4 11
8979#define ICL_PW_CTL_IDX_AUX_TBT3 10
8980#define ICL_PW_CTL_IDX_AUX_TBT2 9
8981#define ICL_PW_CTL_IDX_AUX_TBT1 8
8982#define ICL_PW_CTL_IDX_AUX_F 5
8983#define ICL_PW_CTL_IDX_AUX_E 4
8984#define ICL_PW_CTL_IDX_AUX_D 3
8985#define ICL_PW_CTL_IDX_AUX_C 2
8986#define ICL_PW_CTL_IDX_AUX_B 1
8987#define ICL_PW_CTL_IDX_AUX_A 0
8988
8989#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
8990#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
8991#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
8992#define ICL_PW_CTL_IDX_DDI_F 5
8993#define ICL_PW_CTL_IDX_DDI_E 4
8994#define ICL_PW_CTL_IDX_DDI_D 3
8995#define ICL_PW_CTL_IDX_DDI_C 2
8996#define ICL_PW_CTL_IDX_DDI_B 1
8997#define ICL_PW_CTL_IDX_DDI_A 0
8998
8999/* HSW - power well misc debug registers */
8968#define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 9000#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
8969#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) 9001#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
8970#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) 9002#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
@@ -8980,18 +9012,26 @@ enum skl_power_gate {
8980 9012
8981#define SKL_FUSE_STATUS _MMIO(0x42000) 9013#define SKL_FUSE_STATUS _MMIO(0x42000)
8982#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) 9014#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
8983/* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */ 9015/*
8984#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1) 9016 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
8985/* PG0 (HW control->no power well ID), PG1..PG4 (ICL_DISP_PW1..ICL_DISP_PW4) */ 9017 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
8986#define ICL_PW_TO_PG(pw) ((pw) - ICL_DISP_PW_1 + SKL_PG1) 9018 */
9019#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
9020 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
9021/*
9022 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9023 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
9024 */
9025#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
9026 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
8987#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) 9027#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
8988 9028
8989#define _CNL_AUX_REG_IDX(pw) ((pw) - 9) 9029#define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
8990#define _CNL_AUX_ANAOVRD1_B 0x162250 9030#define _CNL_AUX_ANAOVRD1_B 0x162250
8991#define _CNL_AUX_ANAOVRD1_C 0x162210 9031#define _CNL_AUX_ANAOVRD1_C 0x162210
8992#define _CNL_AUX_ANAOVRD1_D 0x1622D0 9032#define _CNL_AUX_ANAOVRD1_D 0x1622D0
8993#define _CNL_AUX_ANAOVRD1_F 0x162A90 9033#define _CNL_AUX_ANAOVRD1_F 0x162A90
8994#define CNL_AUX_ANAOVRD1(pw) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \ 9034#define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
8995 _CNL_AUX_ANAOVRD1_B, \ 9035 _CNL_AUX_ANAOVRD1_B, \
8996 _CNL_AUX_ANAOVRD1_C, \ 9036 _CNL_AUX_ANAOVRD1_C, \
8997 _CNL_AUX_ANAOVRD1_D, \ 9037 _CNL_AUX_ANAOVRD1_D, \
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 73c6d56ba3ec..53e7a7e75384 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8973,7 +8973,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8973 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", 8973 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8974 pipe_name(crtc->pipe)); 8974 pipe_name(crtc->pipe));
8975 8975
8976 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)), 8976 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2),
8977 "Display power well on\n"); 8977 "Display power well on\n");
8978 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); 8978 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8979 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); 8979 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
@@ -16129,8 +16129,7 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16129 return NULL; 16129 return NULL;
16130 16130
16131 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 16131 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16132 error->power_well_driver = 16132 error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
16133 I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
16134 16133
16135 for_each_pipe(dev_priv, i) { 16134 for_each_pipe(dev_priv, i) {
16136 error->pipe[i].power_domain_on = 16135 error->pipe[i].power_domain_on =
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index bcdf04847b49..bba32df770b2 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -323,26 +323,29 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
323static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, 323static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
324 struct i915_power_well *power_well) 324 struct i915_power_well *power_well)
325{ 325{
326 enum i915_power_well_id id = power_well->desc->id; 326 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
327 int pw_idx = power_well->desc->hsw.idx;
327 328
328 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ 329 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
329 WARN_ON(intel_wait_for_register(dev_priv, 330 WARN_ON(intel_wait_for_register(dev_priv,
330 HSW_PWR_WELL_CTL_DRIVER(id), 331 regs->driver,
331 HSW_PWR_WELL_CTL_STATE(id), 332 HSW_PWR_WELL_CTL_STATE(pw_idx),
332 HSW_PWR_WELL_CTL_STATE(id), 333 HSW_PWR_WELL_CTL_STATE(pw_idx),
333 1)); 334 1));
334} 335}
335 336
336static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, 337static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
337 enum i915_power_well_id id) 338 const struct i915_power_well_regs *regs,
339 int pw_idx)
338{ 340{
339 u32 req_mask = HSW_PWR_WELL_CTL_REQ(id); 341 u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
340 u32 ret; 342 u32 ret;
341 343
342 ret = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)) & req_mask ? 1 : 0; 344 ret = I915_READ(regs->bios) & req_mask ? 1 : 0;
343 ret |= I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & req_mask ? 2 : 0; 345 ret |= I915_READ(regs->driver) & req_mask ? 2 : 0;
344 ret |= I915_READ(HSW_PWR_WELL_CTL_KVMR) & req_mask ? 4 : 0; 346 if (regs->kvmr.reg)
345 ret |= I915_READ(HSW_PWR_WELL_CTL_DEBUG(id)) & req_mask ? 8 : 0; 347 ret |= I915_READ(regs->kvmr) & req_mask ? 4 : 0;
348 ret |= I915_READ(regs->debug) & req_mask ? 8 : 0;
346 349
347 return ret; 350 return ret;
348} 351}
@@ -350,7 +353,8 @@ static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
350static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, 353static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
351 struct i915_power_well *power_well) 354 struct i915_power_well *power_well)
352{ 355{
353 enum i915_power_well_id id = power_well->desc->id; 356 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
357 int pw_idx = power_well->desc->hsw.idx;
354 bool disabled; 358 bool disabled;
355 u32 reqs; 359 u32 reqs;
356 360
@@ -363,9 +367,9 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
363 * Skip the wait in case any of the request bits are set and print a 367 * Skip the wait in case any of the request bits are set and print a
364 * diagnostic message. 368 * diagnostic message.
365 */ 369 */
366 wait_for((disabled = !(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & 370 wait_for((disabled = !(I915_READ(regs->driver) &
367 HSW_PWR_WELL_CTL_STATE(id))) || 371 HSW_PWR_WELL_CTL_STATE(pw_idx))) ||
368 (reqs = hsw_power_well_requesters(dev_priv, id)), 1); 372 (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1);
369 if (disabled) 373 if (disabled)
370 return; 374 return;
371 375
@@ -386,14 +390,15 @@ static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
386static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 390static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
387 struct i915_power_well *power_well) 391 struct i915_power_well *power_well)
388{ 392{
389 enum i915_power_well_id id = power_well->desc->id; 393 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
394 int pw_idx = power_well->desc->hsw.idx;
390 bool wait_fuses = power_well->desc->hsw.has_fuses; 395 bool wait_fuses = power_well->desc->hsw.has_fuses;
391 enum skl_power_gate uninitialized_var(pg); 396 enum skl_power_gate uninitialized_var(pg);
392 u32 val; 397 u32 val;
393 398
394 if (wait_fuses) { 399 if (wait_fuses) {
395 pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_TO_PG(id) : 400 pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
396 SKL_PW_TO_PG(id); 401 SKL_PW_CTL_IDX_TO_PG(pw_idx);
397 /* 402 /*
398 * For PW1 we have to wait both for the PW0/PG0 fuse state 403 * For PW1 we have to wait both for the PW0/PG0 fuse state
399 * before enabling the power well and PW1/PG1's own fuse 404 * before enabling the power well and PW1/PG1's own fuse
@@ -405,17 +410,17 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
405 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); 410 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0);
406 } 411 }
407 412
408 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); 413 val = I915_READ(regs->driver);
409 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id)); 414 I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
410 hsw_wait_for_power_well_enable(dev_priv, power_well); 415 hsw_wait_for_power_well_enable(dev_priv, power_well);
411 416
412 /* Display WA #1178: cnl */ 417 /* Display WA #1178: cnl */
413 if (IS_CANNONLAKE(dev_priv) && 418 if (IS_CANNONLAKE(dev_priv) &&
414 (id == CNL_DISP_PW_AUX_B || id == CNL_DISP_PW_AUX_C || 419 pw_idx >= GLK_PW_CTL_IDX_AUX_B &&
415 id == CNL_DISP_PW_AUX_D || id == CNL_DISP_PW_AUX_F)) { 420 pw_idx <= CNL_PW_CTL_IDX_AUX_F) {
416 val = I915_READ(CNL_AUX_ANAOVRD1(id)); 421 val = I915_READ(CNL_AUX_ANAOVRD1(pw_idx));
417 val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS; 422 val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
418 I915_WRITE(CNL_AUX_ANAOVRD1(id), val); 423 I915_WRITE(CNL_AUX_ANAOVRD1(pw_idx), val);
419 } 424 }
420 425
421 if (wait_fuses) 426 if (wait_fuses)
@@ -429,30 +434,31 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
429static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 434static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
430 struct i915_power_well *power_well) 435 struct i915_power_well *power_well)
431{ 436{
432 enum i915_power_well_id id = power_well->desc->id; 437 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
438 int pw_idx = power_well->desc->hsw.idx;
433 u32 val; 439 u32 val;
434 440
435 hsw_power_well_pre_disable(dev_priv, 441 hsw_power_well_pre_disable(dev_priv,
436 power_well->desc->hsw.irq_pipe_mask); 442 power_well->desc->hsw.irq_pipe_mask);
437 443
438 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); 444 val = I915_READ(regs->driver);
439 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), 445 I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
440 val & ~HSW_PWR_WELL_CTL_REQ(id));
441 hsw_wait_for_power_well_disable(dev_priv, power_well); 446 hsw_wait_for_power_well_disable(dev_priv, power_well);
442} 447}
443 448
444#define ICL_AUX_PW_TO_PORT(pw) ((pw) - ICL_DISP_PW_AUX_A) 449#define ICL_AUX_PW_TO_PORT(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
445 450
446static void 451static void
447icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, 452icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
448 struct i915_power_well *power_well) 453 struct i915_power_well *power_well)
449{ 454{
450 enum i915_power_well_id id = power_well->desc->id; 455 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
451 enum port port = ICL_AUX_PW_TO_PORT(id); 456 int pw_idx = power_well->desc->hsw.idx;
457 enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
452 u32 val; 458 u32 val;
453 459
454 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); 460 val = I915_READ(regs->driver);
455 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id)); 461 I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
456 462
457 val = I915_READ(ICL_PORT_CL_DW12(port)); 463 val = I915_READ(ICL_PORT_CL_DW12(port));
458 I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX); 464 I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
@@ -464,16 +470,16 @@ static void
464icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, 470icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
465 struct i915_power_well *power_well) 471 struct i915_power_well *power_well)
466{ 472{
467 enum i915_power_well_id id = power_well->desc->id; 473 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
468 enum port port = ICL_AUX_PW_TO_PORT(id); 474 int pw_idx = power_well->desc->hsw.idx;
475 enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
469 u32 val; 476 u32 val;
470 477
471 val = I915_READ(ICL_PORT_CL_DW12(port)); 478 val = I915_READ(ICL_PORT_CL_DW12(port));
472 I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX); 479 I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
473 480
474 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); 481 val = I915_READ(regs->driver);
475 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), 482 I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
476 val & ~HSW_PWR_WELL_CTL_REQ(id));
477 483
478 hsw_wait_for_power_well_disable(dev_priv, power_well); 484 hsw_wait_for_power_well_disable(dev_priv, power_well);
479} 485}
@@ -486,22 +492,22 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
486static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 492static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
487 struct i915_power_well *power_well) 493 struct i915_power_well *power_well)
488{ 494{
489 enum i915_power_well_id id = power_well->desc->id; 495 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
490 u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id); 496 int pw_idx = power_well->desc->hsw.idx;
497 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
498 HSW_PWR_WELL_CTL_STATE(pw_idx);
491 499
492 return (I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & mask) == mask; 500 return (I915_READ(regs->driver) & mask) == mask;
493} 501}
494 502
495static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) 503static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
496{ 504{
497 enum i915_power_well_id id = SKL_DISP_PW_2;
498
499 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 505 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
500 "DC9 already programmed to be enabled.\n"); 506 "DC9 already programmed to be enabled.\n");
501 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 507 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
502 "DC5 still not disabled to enable DC9.\n"); 508 "DC5 still not disabled to enable DC9.\n");
503 WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & 509 WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL2) &
504 HSW_PWR_WELL_CTL_REQ(id), 510 HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2),
505 "Power well 2 on.\n"); 511 "Power well 2 on.\n");
506 WARN_ONCE(intel_irqs_enabled(dev_priv), 512 WARN_ONCE(intel_irqs_enabled(dev_priv),
507 "Interrupts not disabled yet.\n"); 513 "Interrupts not disabled yet.\n");
@@ -725,17 +731,18 @@ static void skl_enable_dc6(struct drm_i915_private *dev_priv)
725static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 731static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
726 struct i915_power_well *power_well) 732 struct i915_power_well *power_well)
727{ 733{
728 enum i915_power_well_id id = power_well->desc->id; 734 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
729 u32 mask = HSW_PWR_WELL_CTL_REQ(id); 735 int pw_idx = power_well->desc->hsw.idx;
730 u32 bios_req = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)); 736 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
737 u32 bios_req = I915_READ(regs->bios);
731 738
732 /* Take over the request bit if set by BIOS. */ 739 /* Take over the request bit if set by BIOS. */
733 if (bios_req & mask) { 740 if (bios_req & mask) {
734 u32 drv_req = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); 741 u32 drv_req = I915_READ(regs->driver);
735 742
736 if (!(drv_req & mask)) 743 if (!(drv_req & mask))
737 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), drv_req | mask); 744 I915_WRITE(regs->driver, drv_req | mask);
738 I915_WRITE(HSW_PWR_WELL_CTL_BIOS(id), bios_req & ~mask); 745 I915_WRITE(regs->bios, bios_req & ~mask);
739 } 746 }
740} 747}
741 748
@@ -2108,6 +2115,13 @@ static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
2108 .is_enabled = bxt_dpio_cmn_power_well_enabled, 2115 .is_enabled = bxt_dpio_cmn_power_well_enabled,
2109}; 2116};
2110 2117
2118static const struct i915_power_well_regs hsw_power_well_regs = {
2119 .bios = HSW_PWR_WELL_CTL1,
2120 .driver = HSW_PWR_WELL_CTL2,
2121 .kvmr = HSW_PWR_WELL_CTL3,
2122 .debug = HSW_PWR_WELL_CTL4,
2123};
2124
2111static const struct i915_power_well_desc hsw_power_wells[] = { 2125static const struct i915_power_well_desc hsw_power_wells[] = {
2112 { 2126 {
2113 .name = "always-on", 2127 .name = "always-on",
@@ -2122,6 +2136,8 @@ static const struct i915_power_well_desc hsw_power_wells[] = {
2122 .ops = &hsw_power_well_ops, 2136 .ops = &hsw_power_well_ops,
2123 .id = HSW_DISP_PW_GLOBAL, 2137 .id = HSW_DISP_PW_GLOBAL,
2124 { 2138 {
2139 .hsw.regs = &hsw_power_well_regs,
2140 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
2125 .hsw.has_vga = true, 2141 .hsw.has_vga = true,
2126 }, 2142 },
2127 }, 2143 },
@@ -2141,6 +2157,8 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
2141 .ops = &hsw_power_well_ops, 2157 .ops = &hsw_power_well_ops,
2142 .id = HSW_DISP_PW_GLOBAL, 2158 .id = HSW_DISP_PW_GLOBAL,
2143 { 2159 {
2160 .hsw.regs = &hsw_power_well_regs,
2161 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
2144 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2162 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2145 .hsw.has_vga = true, 2163 .hsw.has_vga = true,
2146 }, 2164 },
@@ -2310,6 +2328,8 @@ static const struct i915_power_well_desc skl_power_wells[] = {
2310 .ops = &hsw_power_well_ops, 2328 .ops = &hsw_power_well_ops,
2311 .id = SKL_DISP_PW_1, 2329 .id = SKL_DISP_PW_1,
2312 { 2330 {
2331 .hsw.regs = &hsw_power_well_regs,
2332 .hsw.idx = SKL_PW_CTL_IDX_PW_1,
2313 .hsw.has_fuses = true, 2333 .hsw.has_fuses = true,
2314 }, 2334 },
2315 }, 2335 },
@@ -2319,6 +2339,10 @@ static const struct i915_power_well_desc skl_power_wells[] = {
2319 .domains = 0, 2339 .domains = 0,
2320 .ops = &hsw_power_well_ops, 2340 .ops = &hsw_power_well_ops,
2321 .id = SKL_DISP_PW_MISC_IO, 2341 .id = SKL_DISP_PW_MISC_IO,
2342 {
2343 .hsw.regs = &hsw_power_well_regs,
2344 .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
2345 },
2322 }, 2346 },
2323 { 2347 {
2324 .name = "DC off", 2348 .name = "DC off",
@@ -2332,6 +2356,8 @@ static const struct i915_power_well_desc skl_power_wells[] = {
2332 .ops = &hsw_power_well_ops, 2356 .ops = &hsw_power_well_ops,
2333 .id = SKL_DISP_PW_2, 2357 .id = SKL_DISP_PW_2,
2334 { 2358 {
2359 .hsw.regs = &hsw_power_well_regs,
2360 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
2335 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2361 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2336 .hsw.has_vga = true, 2362 .hsw.has_vga = true,
2337 .hsw.has_fuses = true, 2363 .hsw.has_fuses = true,
@@ -2342,24 +2368,40 @@ static const struct i915_power_well_desc skl_power_wells[] = {
2342 .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS, 2368 .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
2343 .ops = &hsw_power_well_ops, 2369 .ops = &hsw_power_well_ops,
2344 .id = SKL_DISP_PW_DDI_A_E, 2370 .id = SKL_DISP_PW_DDI_A_E,
2371 {
2372 .hsw.regs = &hsw_power_well_regs,
2373 .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
2374 },
2345 }, 2375 },
2346 { 2376 {
2347 .name = "DDI B IO power well", 2377 .name = "DDI B IO power well",
2348 .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS, 2378 .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
2349 .ops = &hsw_power_well_ops, 2379 .ops = &hsw_power_well_ops,
2350 .id = SKL_DISP_PW_DDI_B, 2380 .id = SKL_DISP_PW_DDI_B,
2381 {
2382 .hsw.regs = &hsw_power_well_regs,
2383 .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
2384 },
2351 }, 2385 },
2352 { 2386 {
2353 .name = "DDI C IO power well", 2387 .name = "DDI C IO power well",
2354 .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS, 2388 .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
2355 .ops = &hsw_power_well_ops, 2389 .ops = &hsw_power_well_ops,
2356 .id = SKL_DISP_PW_DDI_C, 2390 .id = SKL_DISP_PW_DDI_C,
2391 {
2392 .hsw.regs = &hsw_power_well_regs,
2393 .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
2394 },
2357 }, 2395 },
2358 { 2396 {
2359 .name = "DDI D IO power well", 2397 .name = "DDI D IO power well",
2360 .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS, 2398 .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
2361 .ops = &hsw_power_well_ops, 2399 .ops = &hsw_power_well_ops,
2362 .id = SKL_DISP_PW_DDI_D, 2400 .id = SKL_DISP_PW_DDI_D,
2401 {
2402 .hsw.regs = &hsw_power_well_regs,
2403 .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
2404 },
2363 }, 2405 },
2364}; 2406};
2365 2407
@@ -2377,6 +2419,8 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
2377 .ops = &hsw_power_well_ops, 2419 .ops = &hsw_power_well_ops,
2378 .id = SKL_DISP_PW_1, 2420 .id = SKL_DISP_PW_1,
2379 { 2421 {
2422 .hsw.regs = &hsw_power_well_regs,
2423 .hsw.idx = SKL_PW_CTL_IDX_PW_1,
2380 .hsw.has_fuses = true, 2424 .hsw.has_fuses = true,
2381 }, 2425 },
2382 }, 2426 },
@@ -2392,6 +2436,8 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
2392 .ops = &hsw_power_well_ops, 2436 .ops = &hsw_power_well_ops,
2393 .id = SKL_DISP_PW_2, 2437 .id = SKL_DISP_PW_2,
2394 { 2438 {
2439 .hsw.regs = &hsw_power_well_regs,
2440 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
2395 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2441 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2396 .hsw.has_vga = true, 2442 .hsw.has_vga = true,
2397 .hsw.has_fuses = true, 2443 .hsw.has_fuses = true,
@@ -2432,6 +2478,8 @@ static const struct i915_power_well_desc glk_power_wells[] = {
2432 .ops = &hsw_power_well_ops, 2478 .ops = &hsw_power_well_ops,
2433 .id = SKL_DISP_PW_1, 2479 .id = SKL_DISP_PW_1,
2434 { 2480 {
2481 .hsw.regs = &hsw_power_well_regs,
2482 .hsw.idx = SKL_PW_CTL_IDX_PW_1,
2435 .hsw.has_fuses = true, 2483 .hsw.has_fuses = true,
2436 }, 2484 },
2437 }, 2485 },
@@ -2447,6 +2495,8 @@ static const struct i915_power_well_desc glk_power_wells[] = {
2447 .ops = &hsw_power_well_ops, 2495 .ops = &hsw_power_well_ops,
2448 .id = SKL_DISP_PW_2, 2496 .id = SKL_DISP_PW_2,
2449 { 2497 {
2498 .hsw.regs = &hsw_power_well_regs,
2499 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
2450 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2500 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2451 .hsw.has_vga = true, 2501 .hsw.has_vga = true,
2452 .hsw.has_fuses = true, 2502 .hsw.has_fuses = true,
@@ -2484,36 +2534,60 @@ static const struct i915_power_well_desc glk_power_wells[] = {
2484 .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS, 2534 .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
2485 .ops = &hsw_power_well_ops, 2535 .ops = &hsw_power_well_ops,
2486 .id = GLK_DISP_PW_AUX_A, 2536 .id = GLK_DISP_PW_AUX_A,
2537 {
2538 .hsw.regs = &hsw_power_well_regs,
2539 .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
2540 },
2487 }, 2541 },
2488 { 2542 {
2489 .name = "AUX B", 2543 .name = "AUX B",
2490 .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS, 2544 .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
2491 .ops = &hsw_power_well_ops, 2545 .ops = &hsw_power_well_ops,
2492 .id = GLK_DISP_PW_AUX_B, 2546 .id = GLK_DISP_PW_AUX_B,
2547 {
2548 .hsw.regs = &hsw_power_well_regs,
2549 .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
2550 },
2493 }, 2551 },
2494 { 2552 {
2495 .name = "AUX C", 2553 .name = "AUX C",
2496 .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS, 2554 .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
2497 .ops = &hsw_power_well_ops, 2555 .ops = &hsw_power_well_ops,
2498 .id = GLK_DISP_PW_AUX_C, 2556 .id = GLK_DISP_PW_AUX_C,
2557 {
2558 .hsw.regs = &hsw_power_well_regs,
2559 .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
2560 },
2499 }, 2561 },
2500 { 2562 {
2501 .name = "DDI A IO power well", 2563 .name = "DDI A IO power well",
2502 .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS, 2564 .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
2503 .ops = &hsw_power_well_ops, 2565 .ops = &hsw_power_well_ops,
2504 .id = GLK_DISP_PW_DDI_A, 2566 .id = GLK_DISP_PW_DDI_A,
2567 {
2568 .hsw.regs = &hsw_power_well_regs,
2569 .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
2570 },
2505 }, 2571 },
2506 { 2572 {
2507 .name = "DDI B IO power well", 2573 .name = "DDI B IO power well",
2508 .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS, 2574 .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
2509 .ops = &hsw_power_well_ops, 2575 .ops = &hsw_power_well_ops,
2510 .id = SKL_DISP_PW_DDI_B, 2576 .id = SKL_DISP_PW_DDI_B,
2577 {
2578 .hsw.regs = &hsw_power_well_regs,
2579 .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
2580 },
2511 }, 2581 },
2512 { 2582 {
2513 .name = "DDI C IO power well", 2583 .name = "DDI C IO power well",
2514 .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS, 2584 .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
2515 .ops = &hsw_power_well_ops, 2585 .ops = &hsw_power_well_ops,
2516 .id = SKL_DISP_PW_DDI_C, 2586 .id = SKL_DISP_PW_DDI_C,
2587 {
2588 .hsw.regs = &hsw_power_well_regs,
2589 .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
2590 },
2517 }, 2591 },
2518}; 2592};
2519 2593
@@ -2532,6 +2606,8 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
2532 .ops = &hsw_power_well_ops, 2606 .ops = &hsw_power_well_ops,
2533 .id = SKL_DISP_PW_1, 2607 .id = SKL_DISP_PW_1,
2534 { 2608 {
2609 .hsw.regs = &hsw_power_well_regs,
2610 .hsw.idx = SKL_PW_CTL_IDX_PW_1,
2535 .hsw.has_fuses = true, 2611 .hsw.has_fuses = true,
2536 }, 2612 },
2537 }, 2613 },
@@ -2540,24 +2616,40 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
2540 .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS, 2616 .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
2541 .ops = &hsw_power_well_ops, 2617 .ops = &hsw_power_well_ops,
2542 .id = CNL_DISP_PW_AUX_A, 2618 .id = CNL_DISP_PW_AUX_A,
2619 {
2620 .hsw.regs = &hsw_power_well_regs,
2621 .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
2622 },
2543 }, 2623 },
2544 { 2624 {
2545 .name = "AUX B", 2625 .name = "AUX B",
2546 .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS, 2626 .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
2547 .ops = &hsw_power_well_ops, 2627 .ops = &hsw_power_well_ops,
2548 .id = CNL_DISP_PW_AUX_B, 2628 .id = CNL_DISP_PW_AUX_B,
2629 {
2630 .hsw.regs = &hsw_power_well_regs,
2631 .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
2632 },
2549 }, 2633 },
2550 { 2634 {
2551 .name = "AUX C", 2635 .name = "AUX C",
2552 .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS, 2636 .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
2553 .ops = &hsw_power_well_ops, 2637 .ops = &hsw_power_well_ops,
2554 .id = CNL_DISP_PW_AUX_C, 2638 .id = CNL_DISP_PW_AUX_C,
2639 {
2640 .hsw.regs = &hsw_power_well_regs,
2641 .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
2642 },
2555 }, 2643 },
2556 { 2644 {
2557 .name = "AUX D", 2645 .name = "AUX D",
2558 .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS, 2646 .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
2559 .ops = &hsw_power_well_ops, 2647 .ops = &hsw_power_well_ops,
2560 .id = CNL_DISP_PW_AUX_D, 2648 .id = CNL_DISP_PW_AUX_D,
2649 {
2650 .hsw.regs = &hsw_power_well_regs,
2651 .hsw.idx = CNL_PW_CTL_IDX_AUX_D,
2652 },
2561 }, 2653 },
2562 { 2654 {
2563 .name = "DC off", 2655 .name = "DC off",
@@ -2571,6 +2663,8 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
2571 .ops = &hsw_power_well_ops, 2663 .ops = &hsw_power_well_ops,
2572 .id = SKL_DISP_PW_2, 2664 .id = SKL_DISP_PW_2,
2573 { 2665 {
2666 .hsw.regs = &hsw_power_well_regs,
2667 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
2574 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2668 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2575 .hsw.has_vga = true, 2669 .hsw.has_vga = true,
2576 .hsw.has_fuses = true, 2670 .hsw.has_fuses = true,
@@ -2581,36 +2675,60 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
2581 .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS, 2675 .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
2582 .ops = &hsw_power_well_ops, 2676 .ops = &hsw_power_well_ops,
2583 .id = CNL_DISP_PW_DDI_A, 2677 .id = CNL_DISP_PW_DDI_A,
2678 {
2679 .hsw.regs = &hsw_power_well_regs,
2680 .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
2681 },
2584 }, 2682 },
2585 { 2683 {
2586 .name = "DDI B IO power well", 2684 .name = "DDI B IO power well",
2587 .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS, 2685 .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
2588 .ops = &hsw_power_well_ops, 2686 .ops = &hsw_power_well_ops,
2589 .id = SKL_DISP_PW_DDI_B, 2687 .id = SKL_DISP_PW_DDI_B,
2688 {
2689 .hsw.regs = &hsw_power_well_regs,
2690 .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
2691 },
2590 }, 2692 },
2591 { 2693 {
2592 .name = "DDI C IO power well", 2694 .name = "DDI C IO power well",
2593 .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS, 2695 .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
2594 .ops = &hsw_power_well_ops, 2696 .ops = &hsw_power_well_ops,
2595 .id = SKL_DISP_PW_DDI_C, 2697 .id = SKL_DISP_PW_DDI_C,
2698 {
2699 .hsw.regs = &hsw_power_well_regs,
2700 .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
2701 },
2596 }, 2702 },
2597 { 2703 {
2598 .name = "DDI D IO power well", 2704 .name = "DDI D IO power well",
2599 .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS, 2705 .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
2600 .ops = &hsw_power_well_ops, 2706 .ops = &hsw_power_well_ops,
2601 .id = SKL_DISP_PW_DDI_D, 2707 .id = SKL_DISP_PW_DDI_D,
2708 {
2709 .hsw.regs = &hsw_power_well_regs,
2710 .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
2711 },
2602 }, 2712 },
2603 { 2713 {
2604 .name = "DDI F IO power well", 2714 .name = "DDI F IO power well",
2605 .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS, 2715 .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
2606 .ops = &hsw_power_well_ops, 2716 .ops = &hsw_power_well_ops,
2607 .id = CNL_DISP_PW_DDI_F, 2717 .id = CNL_DISP_PW_DDI_F,
2718 {
2719 .hsw.regs = &hsw_power_well_regs,
2720 .hsw.idx = CNL_PW_CTL_IDX_DDI_F,
2721 },
2608 }, 2722 },
2609 { 2723 {
2610 .name = "AUX F", 2724 .name = "AUX F",
2611 .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS, 2725 .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
2612 .ops = &hsw_power_well_ops, 2726 .ops = &hsw_power_well_ops,
2613 .id = CNL_DISP_PW_AUX_F, 2727 .id = CNL_DISP_PW_AUX_F,
2728 {
2729 .hsw.regs = &hsw_power_well_regs,
2730 .hsw.idx = CNL_PW_CTL_IDX_AUX_F,
2731 },
2614 }, 2732 },
2615}; 2733};
2616 2734
@@ -2621,6 +2739,18 @@ static const struct i915_power_well_ops icl_combo_phy_aux_power_well_ops = {
2621 .is_enabled = hsw_power_well_enabled, 2739 .is_enabled = hsw_power_well_enabled,
2622}; 2740};
2623 2741
2742static const struct i915_power_well_regs icl_aux_power_well_regs = {
2743 .bios = ICL_PWR_WELL_CTL_AUX1,
2744 .driver = ICL_PWR_WELL_CTL_AUX2,
2745 .debug = ICL_PWR_WELL_CTL_AUX4,
2746};
2747
2748static const struct i915_power_well_regs icl_ddi_power_well_regs = {
2749 .bios = ICL_PWR_WELL_CTL_DDI1,
2750 .driver = ICL_PWR_WELL_CTL_DDI2,
2751 .debug = ICL_PWR_WELL_CTL_DDI4,
2752};
2753
2624static const struct i915_power_well_desc icl_power_wells[] = { 2754static const struct i915_power_well_desc icl_power_wells[] = {
2625 { 2755 {
2626 .name = "always-on", 2756 .name = "always-on",
@@ -2636,6 +2766,8 @@ static const struct i915_power_well_desc icl_power_wells[] = {
2636 .ops = &hsw_power_well_ops, 2766 .ops = &hsw_power_well_ops,
2637 .id = ICL_DISP_PW_1, 2767 .id = ICL_DISP_PW_1,
2638 { 2768 {
2769 .hsw.regs = &hsw_power_well_regs,
2770 .hsw.idx = ICL_PW_CTL_IDX_PW_1,
2639 .hsw.has_fuses = true, 2771 .hsw.has_fuses = true,
2640 }, 2772 },
2641 }, 2773 },
@@ -2645,6 +2777,8 @@ static const struct i915_power_well_desc icl_power_wells[] = {
2645 .ops = &hsw_power_well_ops, 2777 .ops = &hsw_power_well_ops,
2646 .id = ICL_DISP_PW_2, 2778 .id = ICL_DISP_PW_2,
2647 { 2779 {
2780 .hsw.regs = &hsw_power_well_regs,
2781 .hsw.idx = ICL_PW_CTL_IDX_PW_2,
2648 .hsw.has_fuses = true, 2782 .hsw.has_fuses = true,
2649 }, 2783 },
2650 }, 2784 },
@@ -2660,6 +2794,8 @@ static const struct i915_power_well_desc icl_power_wells[] = {
2660 .ops = &hsw_power_well_ops, 2794 .ops = &hsw_power_well_ops,
2661 .id = ICL_DISP_PW_3, 2795 .id = ICL_DISP_PW_3,
2662 { 2796 {
2797 .hsw.regs = &hsw_power_well_regs,
2798 .hsw.idx = ICL_PW_CTL_IDX_PW_3,
2663 .hsw.irq_pipe_mask = BIT(PIPE_B), 2799 .hsw.irq_pipe_mask = BIT(PIPE_B),
2664 .hsw.has_vga = true, 2800 .hsw.has_vga = true,
2665 .hsw.has_fuses = true, 2801 .hsw.has_fuses = true,
@@ -2670,96 +2806,160 @@ static const struct i915_power_well_desc icl_power_wells[] = {
2670 .domains = ICL_DDI_IO_A_POWER_DOMAINS, 2806 .domains = ICL_DDI_IO_A_POWER_DOMAINS,
2671 .ops = &hsw_power_well_ops, 2807 .ops = &hsw_power_well_ops,
2672 .id = ICL_DISP_PW_DDI_A, 2808 .id = ICL_DISP_PW_DDI_A,
2809 {
2810 .hsw.regs = &icl_ddi_power_well_regs,
2811 .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
2812 },
2673 }, 2813 },
2674 { 2814 {
2675 .name = "DDI B IO", 2815 .name = "DDI B IO",
2676 .domains = ICL_DDI_IO_B_POWER_DOMAINS, 2816 .domains = ICL_DDI_IO_B_POWER_DOMAINS,
2677 .ops = &hsw_power_well_ops, 2817 .ops = &hsw_power_well_ops,
2678 .id = ICL_DISP_PW_DDI_B, 2818 .id = ICL_DISP_PW_DDI_B,
2819 {
2820 .hsw.regs = &icl_ddi_power_well_regs,
2821 .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
2822 },
2679 }, 2823 },
2680 { 2824 {
2681 .name = "DDI C IO", 2825 .name = "DDI C IO",
2682 .domains = ICL_DDI_IO_C_POWER_DOMAINS, 2826 .domains = ICL_DDI_IO_C_POWER_DOMAINS,
2683 .ops = &hsw_power_well_ops, 2827 .ops = &hsw_power_well_ops,
2684 .id = ICL_DISP_PW_DDI_C, 2828 .id = ICL_DISP_PW_DDI_C,
2829 {
2830 .hsw.regs = &icl_ddi_power_well_regs,
2831 .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
2832 },
2685 }, 2833 },
2686 { 2834 {
2687 .name = "DDI D IO", 2835 .name = "DDI D IO",
2688 .domains = ICL_DDI_IO_D_POWER_DOMAINS, 2836 .domains = ICL_DDI_IO_D_POWER_DOMAINS,
2689 .ops = &hsw_power_well_ops, 2837 .ops = &hsw_power_well_ops,
2690 .id = ICL_DISP_PW_DDI_D, 2838 .id = ICL_DISP_PW_DDI_D,
2839 {
2840 .hsw.regs = &icl_ddi_power_well_regs,
2841 .hsw.idx = ICL_PW_CTL_IDX_DDI_D,
2842 },
2691 }, 2843 },
2692 { 2844 {
2693 .name = "DDI E IO", 2845 .name = "DDI E IO",
2694 .domains = ICL_DDI_IO_E_POWER_DOMAINS, 2846 .domains = ICL_DDI_IO_E_POWER_DOMAINS,
2695 .ops = &hsw_power_well_ops, 2847 .ops = &hsw_power_well_ops,
2696 .id = ICL_DISP_PW_DDI_E, 2848 .id = ICL_DISP_PW_DDI_E,
2849 {
2850 .hsw.regs = &icl_ddi_power_well_regs,
2851 .hsw.idx = ICL_PW_CTL_IDX_DDI_E,
2852 },
2697 }, 2853 },
2698 { 2854 {
2699 .name = "DDI F IO", 2855 .name = "DDI F IO",
2700 .domains = ICL_DDI_IO_F_POWER_DOMAINS, 2856 .domains = ICL_DDI_IO_F_POWER_DOMAINS,
2701 .ops = &hsw_power_well_ops, 2857 .ops = &hsw_power_well_ops,
2702 .id = ICL_DISP_PW_DDI_F, 2858 .id = ICL_DISP_PW_DDI_F,
2859 {
2860 .hsw.regs = &icl_ddi_power_well_regs,
2861 .hsw.idx = ICL_PW_CTL_IDX_DDI_F,
2862 },
2703 }, 2863 },
2704 { 2864 {
2705 .name = "AUX A", 2865 .name = "AUX A",
2706 .domains = ICL_AUX_A_IO_POWER_DOMAINS, 2866 .domains = ICL_AUX_A_IO_POWER_DOMAINS,
2707 .ops = &icl_combo_phy_aux_power_well_ops, 2867 .ops = &icl_combo_phy_aux_power_well_ops,
2708 .id = ICL_DISP_PW_AUX_A, 2868 .id = ICL_DISP_PW_AUX_A,
2869 {
2870 .hsw.regs = &icl_aux_power_well_regs,
2871 .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
2872 },
2709 }, 2873 },
2710 { 2874 {
2711 .name = "AUX B", 2875 .name = "AUX B",
2712 .domains = ICL_AUX_B_IO_POWER_DOMAINS, 2876 .domains = ICL_AUX_B_IO_POWER_DOMAINS,
2713 .ops = &icl_combo_phy_aux_power_well_ops, 2877 .ops = &icl_combo_phy_aux_power_well_ops,
2714 .id = ICL_DISP_PW_AUX_B, 2878 .id = ICL_DISP_PW_AUX_B,
2879 {
2880 .hsw.regs = &icl_aux_power_well_regs,
2881 .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
2882 },
2715 }, 2883 },
2716 { 2884 {
2717 .name = "AUX C", 2885 .name = "AUX C",
2718 .domains = ICL_AUX_C_IO_POWER_DOMAINS, 2886 .domains = ICL_AUX_C_IO_POWER_DOMAINS,
2719 .ops = &hsw_power_well_ops, 2887 .ops = &hsw_power_well_ops,
2720 .id = ICL_DISP_PW_AUX_C, 2888 .id = ICL_DISP_PW_AUX_C,
2889 {
2890 .hsw.regs = &icl_aux_power_well_regs,
2891 .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
2892 },
2721 }, 2893 },
2722 { 2894 {
2723 .name = "AUX D", 2895 .name = "AUX D",
2724 .domains = ICL_AUX_D_IO_POWER_DOMAINS, 2896 .domains = ICL_AUX_D_IO_POWER_DOMAINS,
2725 .ops = &hsw_power_well_ops, 2897 .ops = &hsw_power_well_ops,
2726 .id = ICL_DISP_PW_AUX_D, 2898 .id = ICL_DISP_PW_AUX_D,
2899 {
2900 .hsw.regs = &icl_aux_power_well_regs,
2901 .hsw.idx = ICL_PW_CTL_IDX_AUX_D,
2902 },
2727 }, 2903 },
2728 { 2904 {
2729 .name = "AUX E", 2905 .name = "AUX E",
2730 .domains = ICL_AUX_E_IO_POWER_DOMAINS, 2906 .domains = ICL_AUX_E_IO_POWER_DOMAINS,
2731 .ops = &hsw_power_well_ops, 2907 .ops = &hsw_power_well_ops,
2732 .id = ICL_DISP_PW_AUX_E, 2908 .id = ICL_DISP_PW_AUX_E,
2909 {
2910 .hsw.regs = &icl_aux_power_well_regs,
2911 .hsw.idx = ICL_PW_CTL_IDX_AUX_E,
2912 },
2733 }, 2913 },
2734 { 2914 {
2735 .name = "AUX F", 2915 .name = "AUX F",
2736 .domains = ICL_AUX_F_IO_POWER_DOMAINS, 2916 .domains = ICL_AUX_F_IO_POWER_DOMAINS,
2737 .ops = &hsw_power_well_ops, 2917 .ops = &hsw_power_well_ops,
2738 .id = ICL_DISP_PW_AUX_F, 2918 .id = ICL_DISP_PW_AUX_F,
2919 {
2920 .hsw.regs = &icl_aux_power_well_regs,
2921 .hsw.idx = ICL_PW_CTL_IDX_AUX_F,
2922 },
2739 }, 2923 },
2740 { 2924 {
2741 .name = "AUX TBT1", 2925 .name = "AUX TBT1",
2742 .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS, 2926 .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
2743 .ops = &hsw_power_well_ops, 2927 .ops = &hsw_power_well_ops,
2744 .id = ICL_DISP_PW_AUX_TBT1, 2928 .id = ICL_DISP_PW_AUX_TBT1,
2929 {
2930 .hsw.regs = &icl_aux_power_well_regs,
2931 .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
2932 },
2745 }, 2933 },
2746 { 2934 {
2747 .name = "AUX TBT2", 2935 .name = "AUX TBT2",
2748 .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS, 2936 .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
2749 .ops = &hsw_power_well_ops, 2937 .ops = &hsw_power_well_ops,
2750 .id = ICL_DISP_PW_AUX_TBT2, 2938 .id = ICL_DISP_PW_AUX_TBT2,
2939 {
2940 .hsw.regs = &icl_aux_power_well_regs,
2941 .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
2942 },
2751 }, 2943 },
2752 { 2944 {
2753 .name = "AUX TBT3", 2945 .name = "AUX TBT3",
2754 .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS, 2946 .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
2755 .ops = &hsw_power_well_ops, 2947 .ops = &hsw_power_well_ops,
2756 .id = ICL_DISP_PW_AUX_TBT3, 2948 .id = ICL_DISP_PW_AUX_TBT3,
2949 {
2950 .hsw.regs = &icl_aux_power_well_regs,
2951 .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
2952 },
2757 }, 2953 },
2758 { 2954 {
2759 .name = "AUX TBT4", 2955 .name = "AUX TBT4",
2760 .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS, 2956 .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
2761 .ops = &hsw_power_well_ops, 2957 .ops = &hsw_power_well_ops,
2762 .id = ICL_DISP_PW_AUX_TBT4, 2958 .id = ICL_DISP_PW_AUX_TBT4,
2959 {
2960 .hsw.regs = &icl_aux_power_well_regs,
2961 .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
2962 },
2763 }, 2963 },
2764 { 2964 {
2765 .name = "power well 4", 2965 .name = "power well 4",
@@ -2767,6 +2967,8 @@ static const struct i915_power_well_desc icl_power_wells[] = {
2767 .ops = &hsw_power_well_ops, 2967 .ops = &hsw_power_well_ops,
2768 .id = ICL_DISP_PW_4, 2968 .id = ICL_DISP_PW_4,
2769 { 2969 {
2970 .hsw.regs = &hsw_power_well_regs,
2971 .hsw.idx = ICL_PW_CTL_IDX_PW_4,
2770 .hsw.has_fuses = true, 2972 .hsw.has_fuses = true,
2771 .hsw.irq_pipe_mask = BIT(PIPE_C), 2973 .hsw.irq_pipe_mask = BIT(PIPE_C),
2772 }, 2974 },
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-07 05:17:07 -0500