diff options
-rw-r--r-- | arch/x86/kernel/cpu/mcheck/mce_amd.c | 29 |
1 files changed, 14 insertions, 15 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index f7666eef4a87..c8e038800591 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c | |||
@@ -94,6 +94,11 @@ static struct smca_bank_name smca_names[] = { | |||
94 | [SMCA_SMU] = { "smu", "System Management Unit" }, | 94 | [SMCA_SMU] = { "smu", "System Management Unit" }, |
95 | }; | 95 | }; |
96 | 96 | ||
97 | static u32 smca_bank_addrs[MAX_NR_BANKS][NR_BLOCKS] __ro_after_init = | ||
98 | { | ||
99 | [0 ... MAX_NR_BANKS - 1] = { [0 ... NR_BLOCKS - 1] = -1 } | ||
100 | }; | ||
101 | |||
97 | const char *smca_get_name(enum smca_bank_types t) | 102 | const char *smca_get_name(enum smca_bank_types t) |
98 | { | 103 | { |
99 | if (t >= N_SMCA_BANK_TYPES) | 104 | if (t >= N_SMCA_BANK_TYPES) |
@@ -443,20 +448,26 @@ static u32 smca_get_block_address(unsigned int cpu, unsigned int bank, | |||
443 | if (!block) | 448 | if (!block) |
444 | return MSR_AMD64_SMCA_MCx_MISC(bank); | 449 | return MSR_AMD64_SMCA_MCx_MISC(bank); |
445 | 450 | ||
451 | /* Check our cache first: */ | ||
452 | if (smca_bank_addrs[bank][block] != -1) | ||
453 | return smca_bank_addrs[bank][block]; | ||
454 | |||
446 | /* | 455 | /* |
447 | * For SMCA enabled processors, BLKPTR field of the first MISC register | 456 | * For SMCA enabled processors, BLKPTR field of the first MISC register |
448 | * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). | 457 | * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). |
449 | */ | 458 | */ |
450 | if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) | 459 | if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) |
451 | return addr; | 460 | goto out; |
452 | 461 | ||
453 | if (!(low & MCI_CONFIG_MCAX)) | 462 | if (!(low & MCI_CONFIG_MCAX)) |
454 | return addr; | 463 | goto out; |
455 | 464 | ||
456 | if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && | 465 | if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && |
457 | (low & MASK_BLKPTR_LO)) | 466 | (low & MASK_BLKPTR_LO)) |
458 | return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); | 467 | addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); |
459 | 468 | ||
469 | out: | ||
470 | smca_bank_addrs[bank][block] = addr; | ||
460 | return addr; | 471 | return addr; |
461 | } | 472 | } |
462 | 473 | ||
@@ -468,18 +479,6 @@ static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 hi | |||
468 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) | 479 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) |
469 | return addr; | 480 | return addr; |
470 | 481 | ||
471 | /* Get address from already initialized block. */ | ||
472 | if (per_cpu(threshold_banks, cpu)) { | ||
473 | struct threshold_bank *bankp = per_cpu(threshold_banks, cpu)[bank]; | ||
474 | |||
475 | if (bankp && bankp->blocks) { | ||
476 | struct threshold_block *blockp = &bankp->blocks[block]; | ||
477 | |||
478 | if (blockp) | ||
479 | return blockp->address; | ||
480 | } | ||
481 | } | ||
482 | |||
483 | if (mce_flags.smca) | 482 | if (mce_flags.smca) |
484 | return smca_get_block_address(cpu, bank, block); | 483 | return smca_get_block_address(cpu, bank, block); |
485 | 484 | ||