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-rw-r--r--drivers/pwm/pwm-imx.c43
1 files changed, 25 insertions, 18 deletions
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index c944f15f574c..d557279446ed 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -137,18 +137,36 @@ static void imx_pwm_sw_reset(struct pwm_chip *chip)
137 dev_warn(dev, "software reset timeout\n"); 137 dev_warn(dev, "software reset timeout\n");
138} 138}
139 139
140static void imx_pwm_wait_fifo_slot(struct pwm_chip *chip,
141 struct pwm_device *pwm)
142{
143 struct imx_chip *imx = to_imx_chip(chip);
144 struct device *dev = chip->dev;
145 unsigned int period_ms;
146 int fifoav;
147 u32 sr;
148
149 sr = readl(imx->mmio_base + MX3_PWMSR);
150 fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
151 if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
152 period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
153 NSEC_PER_MSEC);
154 msleep(period_ms);
155
156 sr = readl(imx->mmio_base + MX3_PWMSR);
157 if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
158 dev_warn(dev, "there is no free FIFO slot\n");
159 }
160}
140 161
141static int imx_pwm_config_v2(struct pwm_chip *chip, 162static int imx_pwm_config_v2(struct pwm_chip *chip,
142 struct pwm_device *pwm, int duty_ns, int period_ns) 163 struct pwm_device *pwm, int duty_ns, int period_ns)
143{ 164{
144 struct imx_chip *imx = to_imx_chip(chip); 165 struct imx_chip *imx = to_imx_chip(chip);
145 struct device *dev = chip->dev;
146 unsigned long long c; 166 unsigned long long c;
147 unsigned long period_cycles, duty_cycles, prescale; 167 unsigned long period_cycles, duty_cycles, prescale;
148 unsigned int period_ms;
149 bool enable = pwm_is_enabled(pwm); 168 bool enable = pwm_is_enabled(pwm);
150 int fifoav; 169 u32 cr;
151 u32 cr, sr;
152 170
153 /* 171 /*
154 * i.MX PWMv2 has a 4-word sample FIFO. 172 * i.MX PWMv2 has a 4-word sample FIFO.
@@ -157,21 +175,10 @@ static int imx_pwm_config_v2(struct pwm_chip *chip,
157 * wait for a full PWM cycle to get a relinquished FIFO slot 175 * wait for a full PWM cycle to get a relinquished FIFO slot
158 * when the controller is enabled and the FIFO is fully loaded. 176 * when the controller is enabled and the FIFO is fully loaded.
159 */ 177 */
160 if (enable) { 178 if (enable)
161 sr = readl(imx->mmio_base + MX3_PWMSR); 179 imx_pwm_wait_fifo_slot(chip, pwm);
162 fifoav = sr & MX3_PWMSR_FIFOAV_MASK; 180 else
163 if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
164 period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
165 NSEC_PER_MSEC);
166 msleep(period_ms);
167
168 sr = readl(imx->mmio_base + MX3_PWMSR);
169 if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
170 dev_warn(dev, "there is no free FIFO slot\n");
171 }
172 } else {
173 imx_pwm_sw_reset(chip); 181 imx_pwm_sw_reset(chip);
174 }
175 182
176 c = clk_get_rate(imx->clk_per); 183 c = clk_get_rate(imx->clk_per);
177 c = c * period_ns; 184 c = c * period_ns;