3 files changed, 14 insertions, 1 deletions

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 0f7ce5eaeac8..028b287466fb 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -239,6 +239,16 @@ config PCIE_MEDIATEK
           Say Y here if you want to enable PCIe controller support on
           MediaTek SoCs.
 
+config PCIE_MOBIVEIL
+        bool "Mobiveil AXI PCIe controller"
+        depends on ARCH_ZYNQMP || COMPILE_TEST
+        depends on OF
+        depends on PCI_MSI_IRQ_DOMAIN
+        help
+          Say Y here if you want to enable support for the Mobiveil AXI PCIe
+          Soft IP. It has up to 8 outbound and inbound windows
+          for address translation and it is a PCIe Gen4 IP.
+
 config PCIE_TANGO_SMP8759
         bool "Tango SMP8759 PCIe controller (DANGEROUS)"
         depends on ARCH_TANGO && PCI_MSI && OF
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 24322b92f200..d56a507495c5 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
 obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
 obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
+obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index cf0aa7cee5b0..a939e8d31735 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -23,6 +23,8 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
+#include "../pci.h"
+
 /* register offsets and bit positions */
 
 /*
@@ -130,7 +132,7 @@ struct mobiveil_pcie {
         void __iomem *config_axi_slave_base;    /* endpoint config base */
         void __iomem *csr_axi_slave_base;       /* root port config base */
         void __iomem *apb_csr_base;     /* MSI register base */
-        void __iomem *pcie_reg_base;    /* Physical PCIe Controller Base */
+        phys_addr_t pcie_reg_base;      /* Physical PCIe Controller Base */
         struct irq_domain *intx_domain;
         raw_spinlock_t intx_mask_lock;
         int irq;