diff options
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen_hdmi.c | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/r600_hdmi.c | 9 |
2 files changed, 7 insertions, 9 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c index b4ab8ceb1654..ed7c8a768092 100644 --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c | |||
| @@ -154,19 +154,18 @@ static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) | |||
| 154 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 154 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 155 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | 155 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 156 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | 156 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 157 | u32 base_rate = 48000; | 157 | u32 base_rate = 24000; |
| 158 | 158 | ||
| 159 | if (!dig || !dig->afmt) | 159 | if (!dig || !dig->afmt) |
| 160 | return; | 160 | return; |
| 161 | 161 | ||
| 162 | /* XXX: properly calculate this */ | ||
| 163 | /* XXX two dtos; generally use dto0 for hdmi */ | 162 | /* XXX two dtos; generally use dto0 for hdmi */ |
| 164 | /* Express [24MHz / target pixel clock] as an exact rational | 163 | /* Express [24MHz / target pixel clock] as an exact rational |
| 165 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE | 164 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
| 166 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator | 165 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
| 167 | */ | 166 | */ |
| 168 | WREG32(DCCG_AUDIO_DTO0_PHASE, (base_rate*50) & 0xffffff); | 167 | WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); |
| 169 | WREG32(DCCG_AUDIO_DTO0_MODULE, (clock*100) & 0xffffff); | 168 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); |
| 170 | WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); | 169 | WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); |
| 171 | } | 170 | } |
| 172 | 171 | ||
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index 47f180a79352..456750a0daa5 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c | |||
| @@ -232,7 +232,7 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) | |||
| 232 | struct radeon_device *rdev = dev->dev_private; | 232 | struct radeon_device *rdev = dev->dev_private; |
| 233 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 233 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 234 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | 234 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 235 | u32 base_rate = 48000; | 235 | u32 base_rate = 24000; |
| 236 | 236 | ||
| 237 | if (!dig || !dig->afmt) | 237 | if (!dig || !dig->afmt) |
| 238 | return; | 238 | return; |
| @@ -240,7 +240,6 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) | |||
| 240 | /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT. | 240 | /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT. |
| 241 | * doesn't matter which one you use. Just use the first one. | 241 | * doesn't matter which one you use. Just use the first one. |
| 242 | */ | 242 | */ |
| 243 | /* XXX: properly calculate this */ | ||
| 244 | /* XXX two dtos; generally use dto0 for hdmi */ | 243 | /* XXX two dtos; generally use dto0 for hdmi */ |
| 245 | /* Express [24MHz / target pixel clock] as an exact rational | 244 | /* Express [24MHz / target pixel clock] as an exact rational |
| 246 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE | 245 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
| @@ -250,13 +249,13 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) | |||
| 250 | /* according to the reg specs, this should DCE3.2 only, but in | 249 | /* according to the reg specs, this should DCE3.2 only, but in |
| 251 | * practice it seems to cover DCE3.0 as well. | 250 | * practice it seems to cover DCE3.0 as well. |
| 252 | */ | 251 | */ |
| 253 | WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 50); | 252 | WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); |
| 254 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); | 253 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); |
| 255 | WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ | 254 | WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ |
| 256 | } else { | 255 | } else { |
| 257 | /* according to the reg specs, this should be DCE2.0 and DCE3.0 */ | 256 | /* according to the reg specs, this should be DCE2.0 and DCE3.0 */ |
| 258 | WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate * 50) | | 257 | WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) | |
| 259 | AUDIO_DTO_MODULE(clock * 100)); | 258 | AUDIO_DTO_MODULE(clock / 10)); |
| 260 | } | 259 | } |
| 261 | } | 260 | } |
| 262 | 261 | ||
