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-rw-r--r--arch/x86/mm/iomap_32.c12
-rw-r--r--arch/x86/mm/ioremap.c5
-rw-r--r--arch/x86/mm/pageattr.c3
-rw-r--r--arch/x86/mm/pat.c13
4 files changed, 10 insertions, 23 deletions
diff --git a/arch/x86/mm/iomap_32.c b/arch/x86/mm/iomap_32.c
index 3a2ec8790ca7..a9dc7a37e6a2 100644
--- a/arch/x86/mm/iomap_32.c
+++ b/arch/x86/mm/iomap_32.c
@@ -77,13 +77,13 @@ void __iomem *
77iomap_atomic_prot_pfn(unsigned long pfn, pgprot_t prot) 77iomap_atomic_prot_pfn(unsigned long pfn, pgprot_t prot)
78{ 78{
79 /* 79 /*
80 * For non-PAT systems, promote PAGE_KERNEL_WC to PAGE_KERNEL_UC_MINUS. 80 * For non-PAT systems, translate non-WB request to UC- just in
81 * PAGE_KERNEL_WC maps to PWT, which translates to uncached if the 81 * case the caller set the PWT bit to prot directly without using
82 * MTRR is UC or WC. UC_MINUS gets the real intention, of the 82 * pgprot_writecombine(). UC- translates to uncached if the MTRR
83 * user, which is "WC if the MTRR is WC, UC if you can't do that." 83 * is UC or WC. UC- gets the real intention, of the user, which is
84 * "WC if the MTRR is WC, UC if you can't do that."
84 */ 85 */
85 if (!pat_enabled() && pgprot_val(prot) == 86 if (!pat_enabled() && pgprot2cachemode(prot) != _PAGE_CACHE_MODE_WB)
86 (__PAGE_KERNEL | cachemode2protval(_PAGE_CACHE_MODE_WC)))
87 prot = __pgprot(__PAGE_KERNEL | 87 prot = __pgprot(__PAGE_KERNEL |
88 cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS)); 88 cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS));
89 89
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index b0da3588b452..cc0f17c5ad9f 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -292,11 +292,8 @@ EXPORT_SYMBOL_GPL(ioremap_uc);
292 */ 292 */
293void __iomem *ioremap_wc(resource_size_t phys_addr, unsigned long size) 293void __iomem *ioremap_wc(resource_size_t phys_addr, unsigned long size)
294{ 294{
295 if (pat_enabled()) 295 return __ioremap_caller(phys_addr, size, _PAGE_CACHE_MODE_WC,
296 return __ioremap_caller(phys_addr, size, _PAGE_CACHE_MODE_WC,
297 __builtin_return_address(0)); 296 __builtin_return_address(0));
298 else
299 return ioremap_nocache(phys_addr, size);
300} 297}
301EXPORT_SYMBOL(ioremap_wc); 298EXPORT_SYMBOL(ioremap_wc);
302 299
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index fae3c5366ac0..31b4f3fd1207 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -1572,9 +1572,6 @@ int set_memory_wc(unsigned long addr, int numpages)
1572{ 1572{
1573 int ret; 1573 int ret;
1574 1574
1575 if (!pat_enabled())
1576 return set_memory_uc(addr, numpages);
1577
1578 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, 1575 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1579 _PAGE_CACHE_MODE_WC, NULL); 1576 _PAGE_CACHE_MODE_WC, NULL);
1580 if (ret) 1577 if (ret)
diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
index 6dc7826e4797..f89e460c55a8 100644
--- a/arch/x86/mm/pat.c
+++ b/arch/x86/mm/pat.c
@@ -438,12 +438,8 @@ int reserve_memtype(u64 start, u64 end, enum page_cache_mode req_type,
438 438
439 if (!pat_enabled()) { 439 if (!pat_enabled()) {
440 /* This is identical to page table setting without PAT */ 440 /* This is identical to page table setting without PAT */
441 if (new_type) { 441 if (new_type)
442 if (req_type == _PAGE_CACHE_MODE_WC) 442 *new_type = req_type;
443 *new_type = _PAGE_CACHE_MODE_UC_MINUS;
444 else
445 *new_type = req_type;
446 }
447 return 0; 443 return 0;
448 } 444 }
449 445
@@ -947,11 +943,8 @@ void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn,
947 943
948pgprot_t pgprot_writecombine(pgprot_t prot) 944pgprot_t pgprot_writecombine(pgprot_t prot)
949{ 945{
950 if (pat_enabled()) 946 return __pgprot(pgprot_val(prot) |
951 return __pgprot(pgprot_val(prot) |
952 cachemode2protval(_PAGE_CACHE_MODE_WC)); 947 cachemode2protval(_PAGE_CACHE_MODE_WC));
953 else
954 return pgprot_noncached(prot);
955} 948}
956EXPORT_SYMBOL_GPL(pgprot_writecombine); 949EXPORT_SYMBOL_GPL(pgprot_writecombine);
957 950