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-rw-r--r--drivers/net/ethernet/mellanox/mlxsw/core.c16
-rw-r--r--drivers/net/ethernet/mellanox/mlxsw/core.h8
-rw-r--r--drivers/net/ethernet/mellanox/mlxsw/spectrum.h8
-rw-r--r--drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c388
-rw-r--r--drivers/net/ethernet/netronome/nfp/nfp_devlink.c3
-rw-r--r--include/net/devlink.h8
-rw-r--r--net/core/devlink.c22
7 files changed, 300 insertions, 153 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.c b/drivers/net/ethernet/mellanox/mlxsw/core.c
index 9e8e3e92f369..bcbe07ec22be 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/core.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/core.c
@@ -781,7 +781,8 @@ mlxsw_devlink_sb_pool_get(struct devlink *devlink,
781static int 781static int
782mlxsw_devlink_sb_pool_set(struct devlink *devlink, 782mlxsw_devlink_sb_pool_set(struct devlink *devlink,
783 unsigned int sb_index, u16 pool_index, u32 size, 783 unsigned int sb_index, u16 pool_index, u32 size,
784 enum devlink_sb_threshold_type threshold_type) 784 enum devlink_sb_threshold_type threshold_type,
785 struct netlink_ext_ack *extack)
785{ 786{
786 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 787 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
787 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 788 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver;
@@ -789,7 +790,8 @@ mlxsw_devlink_sb_pool_set(struct devlink *devlink,
789 if (!mlxsw_driver->sb_pool_set) 790 if (!mlxsw_driver->sb_pool_set)
790 return -EOPNOTSUPP; 791 return -EOPNOTSUPP;
791 return mlxsw_driver->sb_pool_set(mlxsw_core, sb_index, 792 return mlxsw_driver->sb_pool_set(mlxsw_core, sb_index,
792 pool_index, size, threshold_type); 793 pool_index, size, threshold_type,
794 extack);
793} 795}
794 796
795static void *__dl_port(struct devlink_port *devlink_port) 797static void *__dl_port(struct devlink_port *devlink_port)
@@ -829,7 +831,8 @@ static int mlxsw_devlink_sb_port_pool_get(struct devlink_port *devlink_port,
829 831
830static int mlxsw_devlink_sb_port_pool_set(struct devlink_port *devlink_port, 832static int mlxsw_devlink_sb_port_pool_set(struct devlink_port *devlink_port,
831 unsigned int sb_index, u16 pool_index, 833 unsigned int sb_index, u16 pool_index,
832 u32 threshold) 834 u32 threshold,
835 struct netlink_ext_ack *extack)
833{ 836{
834 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 837 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink);
835 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 838 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver;
@@ -839,7 +842,7 @@ static int mlxsw_devlink_sb_port_pool_set(struct devlink_port *devlink_port,
839 !mlxsw_core_port_check(mlxsw_core_port)) 842 !mlxsw_core_port_check(mlxsw_core_port))
840 return -EOPNOTSUPP; 843 return -EOPNOTSUPP;
841 return mlxsw_driver->sb_port_pool_set(mlxsw_core_port, sb_index, 844 return mlxsw_driver->sb_port_pool_set(mlxsw_core_port, sb_index,
842 pool_index, threshold); 845 pool_index, threshold, extack);
843} 846}
844 847
845static int 848static int
@@ -864,7 +867,8 @@ static int
864mlxsw_devlink_sb_tc_pool_bind_set(struct devlink_port *devlink_port, 867mlxsw_devlink_sb_tc_pool_bind_set(struct devlink_port *devlink_port,
865 unsigned int sb_index, u16 tc_index, 868 unsigned int sb_index, u16 tc_index,
866 enum devlink_sb_pool_type pool_type, 869 enum devlink_sb_pool_type pool_type,
867 u16 pool_index, u32 threshold) 870 u16 pool_index, u32 threshold,
871 struct netlink_ext_ack *extack)
868{ 872{
869 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 873 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink);
870 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 874 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver;
@@ -875,7 +879,7 @@ mlxsw_devlink_sb_tc_pool_bind_set(struct devlink_port *devlink_port,
875 return -EOPNOTSUPP; 879 return -EOPNOTSUPP;
876 return mlxsw_driver->sb_tc_pool_bind_set(mlxsw_core_port, sb_index, 880 return mlxsw_driver->sb_tc_pool_bind_set(mlxsw_core_port, sb_index,
877 tc_index, pool_type, 881 tc_index, pool_type,
878 pool_index, threshold); 882 pool_index, threshold, extack);
879} 883}
880 884
881static int mlxsw_devlink_sb_occ_snapshot(struct devlink *devlink, 885static int mlxsw_devlink_sb_occ_snapshot(struct devlink *devlink,
diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.h b/drivers/net/ethernet/mellanox/mlxsw/core.h
index d51dfc3560b6..917be621c904 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/core.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/core.h
@@ -254,13 +254,14 @@ struct mlxsw_driver {
254 struct devlink_sb_pool_info *pool_info); 254 struct devlink_sb_pool_info *pool_info);
255 int (*sb_pool_set)(struct mlxsw_core *mlxsw_core, 255 int (*sb_pool_set)(struct mlxsw_core *mlxsw_core,
256 unsigned int sb_index, u16 pool_index, u32 size, 256 unsigned int sb_index, u16 pool_index, u32 size,
257 enum devlink_sb_threshold_type threshold_type); 257 enum devlink_sb_threshold_type threshold_type,
258 struct netlink_ext_ack *extack);
258 int (*sb_port_pool_get)(struct mlxsw_core_port *mlxsw_core_port, 259 int (*sb_port_pool_get)(struct mlxsw_core_port *mlxsw_core_port,
259 unsigned int sb_index, u16 pool_index, 260 unsigned int sb_index, u16 pool_index,
260 u32 *p_threshold); 261 u32 *p_threshold);
261 int (*sb_port_pool_set)(struct mlxsw_core_port *mlxsw_core_port, 262 int (*sb_port_pool_set)(struct mlxsw_core_port *mlxsw_core_port,
262 unsigned int sb_index, u16 pool_index, 263 unsigned int sb_index, u16 pool_index,
263 u32 threshold); 264 u32 threshold, struct netlink_ext_ack *extack);
264 int (*sb_tc_pool_bind_get)(struct mlxsw_core_port *mlxsw_core_port, 265 int (*sb_tc_pool_bind_get)(struct mlxsw_core_port *mlxsw_core_port,
265 unsigned int sb_index, u16 tc_index, 266 unsigned int sb_index, u16 tc_index,
266 enum devlink_sb_pool_type pool_type, 267 enum devlink_sb_pool_type pool_type,
@@ -268,7 +269,8 @@ struct mlxsw_driver {
268 int (*sb_tc_pool_bind_set)(struct mlxsw_core_port *mlxsw_core_port, 269 int (*sb_tc_pool_bind_set)(struct mlxsw_core_port *mlxsw_core_port,
269 unsigned int sb_index, u16 tc_index, 270 unsigned int sb_index, u16 tc_index,
270 enum devlink_sb_pool_type pool_type, 271 enum devlink_sb_pool_type pool_type,
271 u16 pool_index, u32 threshold); 272 u16 pool_index, u32 threshold,
273 struct netlink_ext_ack *extack);
272 int (*sb_occ_snapshot)(struct mlxsw_core *mlxsw_core, 274 int (*sb_occ_snapshot)(struct mlxsw_core *mlxsw_core,
273 unsigned int sb_index); 275 unsigned int sb_index);
274 int (*sb_occ_max_clear)(struct mlxsw_core *mlxsw_core, 276 int (*sb_occ_max_clear)(struct mlxsw_core *mlxsw_core,
diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.h b/drivers/net/ethernet/mellanox/mlxsw/spectrum.h
index da6278b0caa4..8601b3041acd 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.h
@@ -371,13 +371,14 @@ int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core,
371 struct devlink_sb_pool_info *pool_info); 371 struct devlink_sb_pool_info *pool_info);
372int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core, 372int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core,
373 unsigned int sb_index, u16 pool_index, u32 size, 373 unsigned int sb_index, u16 pool_index, u32 size,
374 enum devlink_sb_threshold_type threshold_type); 374 enum devlink_sb_threshold_type threshold_type,
375 struct netlink_ext_ack *extack);
375int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port, 376int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
376 unsigned int sb_index, u16 pool_index, 377 unsigned int sb_index, u16 pool_index,
377 u32 *p_threshold); 378 u32 *p_threshold);
378int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port, 379int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
379 unsigned int sb_index, u16 pool_index, 380 unsigned int sb_index, u16 pool_index,
380 u32 threshold); 381 u32 threshold, struct netlink_ext_ack *extack);
381int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port, 382int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
382 unsigned int sb_index, u16 tc_index, 383 unsigned int sb_index, u16 tc_index,
383 enum devlink_sb_pool_type pool_type, 384 enum devlink_sb_pool_type pool_type,
@@ -385,7 +386,8 @@ int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
385int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port, 386int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port,
386 unsigned int sb_index, u16 tc_index, 387 unsigned int sb_index, u16 tc_index,
387 enum devlink_sb_pool_type pool_type, 388 enum devlink_sb_pool_type pool_type,
388 u16 pool_index, u32 threshold); 389 u16 pool_index, u32 threshold,
390 struct netlink_ext_ack *extack);
389int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core, 391int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core,
390 unsigned int sb_index); 392 unsigned int sb_index);
391int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core, 393int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core,
diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c
index d633bef5f105..8512dd49e420 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c
@@ -6,6 +6,7 @@
6#include <linux/dcbnl.h> 6#include <linux/dcbnl.h>
7#include <linux/if_ether.h> 7#include <linux/if_ether.h>
8#include <linux/list.h> 8#include <linux/list.h>
9#include <linux/netlink.h>
9 10
10#include "spectrum.h" 11#include "spectrum.h"
11#include "core.h" 12#include "core.h"
@@ -15,6 +16,8 @@
15struct mlxsw_sp_sb_pr { 16struct mlxsw_sp_sb_pr {
16 enum mlxsw_reg_sbpr_mode mode; 17 enum mlxsw_reg_sbpr_mode mode;
17 u32 size; 18 u32 size;
19 u8 freeze_mode:1,
20 freeze_size:1;
18}; 21};
19 22
20struct mlxsw_cp_sb_occ { 23struct mlxsw_cp_sb_occ {
@@ -27,6 +30,8 @@ struct mlxsw_sp_sb_cm {
27 u32 max_buff; 30 u32 max_buff;
28 u16 pool_index; 31 u16 pool_index;
29 struct mlxsw_cp_sb_occ occ; 32 struct mlxsw_cp_sb_occ occ;
33 u8 freeze_pool:1,
34 freeze_thresh:1;
30}; 35};
31 36
32#define MLXSW_SP_SB_INFI -1U 37#define MLXSW_SP_SB_INFI -1U
@@ -48,7 +53,12 @@ struct mlxsw_sp_sb_pool_des {
48 u8 pool; 53 u8 pool;
49}; 54};
50 55
51/* Order ingress pools before egress pools. */ 56#define MLXSW_SP_SB_POOL_ING 0
57#define MLXSW_SP_SB_POOL_EGR 4
58#define MLXSW_SP_SB_POOL_EGR_MC 8
59#define MLXSW_SP_SB_POOL_ING_CPU 9
60#define MLXSW_SP_SB_POOL_EGR_CPU 10
61
52static const struct mlxsw_sp_sb_pool_des mlxsw_sp1_sb_pool_dess[] = { 62static const struct mlxsw_sp_sb_pool_des mlxsw_sp1_sb_pool_dess[] = {
53 {MLXSW_REG_SBXX_DIR_INGRESS, 0}, 63 {MLXSW_REG_SBXX_DIR_INGRESS, 0},
54 {MLXSW_REG_SBXX_DIR_INGRESS, 1}, 64 {MLXSW_REG_SBXX_DIR_INGRESS, 1},
@@ -59,6 +69,8 @@ static const struct mlxsw_sp_sb_pool_des mlxsw_sp1_sb_pool_dess[] = {
59 {MLXSW_REG_SBXX_DIR_EGRESS, 2}, 69 {MLXSW_REG_SBXX_DIR_EGRESS, 2},
60 {MLXSW_REG_SBXX_DIR_EGRESS, 3}, 70 {MLXSW_REG_SBXX_DIR_EGRESS, 3},
61 {MLXSW_REG_SBXX_DIR_EGRESS, 15}, 71 {MLXSW_REG_SBXX_DIR_EGRESS, 15},
72 {MLXSW_REG_SBXX_DIR_INGRESS, 4},
73 {MLXSW_REG_SBXX_DIR_EGRESS, 4},
62}; 74};
63 75
64static const struct mlxsw_sp_sb_pool_des mlxsw_sp2_sb_pool_dess[] = { 76static const struct mlxsw_sp_sb_pool_des mlxsw_sp2_sb_pool_dess[] = {
@@ -71,6 +83,8 @@ static const struct mlxsw_sp_sb_pool_des mlxsw_sp2_sb_pool_dess[] = {
71 {MLXSW_REG_SBXX_DIR_EGRESS, 2}, 83 {MLXSW_REG_SBXX_DIR_EGRESS, 2},
72 {MLXSW_REG_SBXX_DIR_EGRESS, 3}, 84 {MLXSW_REG_SBXX_DIR_EGRESS, 3},
73 {MLXSW_REG_SBXX_DIR_EGRESS, 15}, 85 {MLXSW_REG_SBXX_DIR_EGRESS, 15},
86 {MLXSW_REG_SBXX_DIR_INGRESS, 4},
87 {MLXSW_REG_SBXX_DIR_EGRESS, 4},
74}; 88};
75 89
76#define MLXSW_SP_SB_ING_TC_COUNT 8 90#define MLXSW_SP_SB_ING_TC_COUNT 8
@@ -94,6 +108,7 @@ struct mlxsw_sp_sb_vals {
94 unsigned int pool_count; 108 unsigned int pool_count;
95 const struct mlxsw_sp_sb_pool_des *pool_dess; 109 const struct mlxsw_sp_sb_pool_des *pool_dess;
96 const struct mlxsw_sp_sb_pm *pms; 110 const struct mlxsw_sp_sb_pm *pms;
111 const struct mlxsw_sp_sb_pm *pms_cpu;
97 const struct mlxsw_sp_sb_pr *prs; 112 const struct mlxsw_sp_sb_pr *prs;
98 const struct mlxsw_sp_sb_mm *mms; 113 const struct mlxsw_sp_sb_mm *mms;
99 const struct mlxsw_sp_sb_cm *cms_ingress; 114 const struct mlxsw_sp_sb_cm *cms_ingress;
@@ -275,7 +290,7 @@ static int mlxsw_sp_port_pb_init(struct mlxsw_sp_port *mlxsw_sp_port)
275{ 290{
276 const u32 pbs[] = { 291 const u32 pbs[] = {
277 [0] = MLXSW_SP_PB_HEADROOM * mlxsw_sp_port->mapping.width, 292 [0] = MLXSW_SP_PB_HEADROOM * mlxsw_sp_port->mapping.width,
278 [9] = 2 * MLXSW_PORT_MAX_MTU, 293 [9] = MLXSW_PORT_MAX_MTU,
279 }; 294 };
280 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 295 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
281 char pbmc_pl[MLXSW_REG_PBMC_LEN]; 296 char pbmc_pl[MLXSW_REG_PBMC_LEN];
@@ -390,46 +405,60 @@ static void mlxsw_sp_sb_ports_fini(struct mlxsw_sp *mlxsw_sp)
390 .size = _size, \ 405 .size = _size, \
391 } 406 }
392 407
408#define MLXSW_SP_SB_PR_EXT(_mode, _size, _freeze_mode, _freeze_size) \
409 { \
410 .mode = _mode, \
411 .size = _size, \
412 .freeze_mode = _freeze_mode, \
413 .freeze_size = _freeze_size, \
414 }
415
393#define MLXSW_SP1_SB_PR_INGRESS_SIZE 12440000 416#define MLXSW_SP1_SB_PR_INGRESS_SIZE 12440000
394#define MLXSW_SP1_SB_PR_INGRESS_MNG_SIZE (200 * 1000)
395#define MLXSW_SP1_SB_PR_EGRESS_SIZE 13232000 417#define MLXSW_SP1_SB_PR_EGRESS_SIZE 13232000
418#define MLXSW_SP1_SB_PR_CPU_SIZE (256 * 1000)
396 419
420/* Order according to mlxsw_sp1_sb_pool_dess */
397static const struct mlxsw_sp_sb_pr mlxsw_sp1_sb_prs[] = { 421static const struct mlxsw_sp_sb_pr mlxsw_sp1_sb_prs[] = {
398 /* Ingress pools. */
399 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 422 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
400 MLXSW_SP1_SB_PR_INGRESS_SIZE), 423 MLXSW_SP1_SB_PR_INGRESS_SIZE),
401 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0), 424 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
402 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0), 425 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
403 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 426 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
404 MLXSW_SP1_SB_PR_INGRESS_MNG_SIZE), 427 MLXSW_SP_SB_PR_EXT(MLXSW_REG_SBPR_MODE_DYNAMIC,
405 /* Egress pools. */ 428 MLXSW_SP1_SB_PR_EGRESS_SIZE, true, false),
406 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
407 MLXSW_SP1_SB_PR_EGRESS_SIZE),
408 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0), 429 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
409 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0), 430 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
410 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0), 431 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
411 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, MLXSW_SP_SB_INFI), 432 MLXSW_SP_SB_PR_EXT(MLXSW_REG_SBPR_MODE_STATIC, MLXSW_SP_SB_INFI,
433 true, true),
434 MLXSW_SP_SB_PR_EXT(MLXSW_REG_SBPR_MODE_DYNAMIC,
435 MLXSW_SP1_SB_PR_CPU_SIZE, true, false),
436 MLXSW_SP_SB_PR_EXT(MLXSW_REG_SBPR_MODE_DYNAMIC,
437 MLXSW_SP1_SB_PR_CPU_SIZE, true, false),
412}; 438};
413 439
414#define MLXSW_SP2_SB_PR_INGRESS_SIZE 40960000 440#define MLXSW_SP2_SB_PR_INGRESS_SIZE 40960000
415#define MLXSW_SP2_SB_PR_INGRESS_MNG_SIZE (200 * 1000)
416#define MLXSW_SP2_SB_PR_EGRESS_SIZE 40960000 441#define MLXSW_SP2_SB_PR_EGRESS_SIZE 40960000
442#define MLXSW_SP2_SB_PR_CPU_SIZE (256 * 1000)
417 443
444/* Order according to mlxsw_sp2_sb_pool_dess */
418static const struct mlxsw_sp_sb_pr mlxsw_sp2_sb_prs[] = { 445static const struct mlxsw_sp_sb_pr mlxsw_sp2_sb_prs[] = {
419 /* Ingress pools. */
420 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 446 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
421 MLXSW_SP2_SB_PR_INGRESS_SIZE), 447 MLXSW_SP2_SB_PR_INGRESS_SIZE),
422 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0), 448 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0),
423 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0), 449 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0),
424 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 450 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0),
425 MLXSW_SP2_SB_PR_INGRESS_MNG_SIZE), 451 MLXSW_SP_SB_PR_EXT(MLXSW_REG_SBPR_MODE_DYNAMIC,
426 /* Egress pools. */ 452 MLXSW_SP2_SB_PR_EGRESS_SIZE, true, false),
427 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
428 MLXSW_SP2_SB_PR_EGRESS_SIZE),
429 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0), 453 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0),
430 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0), 454 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0),
431 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0), 455 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0),
432 MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, MLXSW_SP_SB_INFI), 456 MLXSW_SP_SB_PR_EXT(MLXSW_REG_SBPR_MODE_STATIC, MLXSW_SP_SB_INFI,
457 true, true),
458 MLXSW_SP_SB_PR_EXT(MLXSW_REG_SBPR_MODE_DYNAMIC,
459 MLXSW_SP2_SB_PR_CPU_SIZE, true, false),
460 MLXSW_SP_SB_PR_EXT(MLXSW_REG_SBPR_MODE_DYNAMIC,
461 MLXSW_SP2_SB_PR_CPU_SIZE, true, false),
433}; 462};
434 463
435static int mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp, 464static int mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp,
@@ -464,83 +493,106 @@ static int mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp,
464 .pool_index = _pool, \ 493 .pool_index = _pool, \
465 } 494 }
466 495
496#define MLXSW_SP_SB_CM_ING(_min_buff, _max_buff) \
497 { \
498 .min_buff = _min_buff, \
499 .max_buff = _max_buff, \
500 .pool_index = MLXSW_SP_SB_POOL_ING, \
501 }
502
503#define MLXSW_SP_SB_CM_EGR(_min_buff, _max_buff) \
504 { \
505 .min_buff = _min_buff, \
506 .max_buff = _max_buff, \
507 .pool_index = MLXSW_SP_SB_POOL_EGR, \
508 }
509
510#define MLXSW_SP_SB_CM_EGR_MC(_min_buff, _max_buff) \
511 { \
512 .min_buff = _min_buff, \
513 .max_buff = _max_buff, \
514 .pool_index = MLXSW_SP_SB_POOL_EGR_MC, \
515 .freeze_pool = true, \
516 .freeze_thresh = true, \
517 }
518
467static const struct mlxsw_sp_sb_cm mlxsw_sp1_sb_cms_ingress[] = { 519static const struct mlxsw_sp_sb_cm mlxsw_sp1_sb_cms_ingress[] = {
468 MLXSW_SP_SB_CM(10000, 8, 0), 520 MLXSW_SP_SB_CM_ING(10000, 8),
469 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), 521 MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
470 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), 522 MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
471 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), 523 MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
472 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), 524 MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
473 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), 525 MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
474 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), 526 MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
475 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), 527 MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
476 MLXSW_SP_SB_CM(0, 0, 0), /* dummy, this PG does not exist */ 528 MLXSW_SP_SB_CM_ING(0, 0), /* dummy, this PG does not exist */
477 MLXSW_SP_SB_CM(20000, 1, 3), 529 MLXSW_SP_SB_CM(10000, 8, MLXSW_SP_SB_POOL_ING_CPU),
478}; 530};
479 531
480static const struct mlxsw_sp_sb_cm mlxsw_sp2_sb_cms_ingress[] = { 532static const struct mlxsw_sp_sb_cm mlxsw_sp2_sb_cms_ingress[] = {
481 MLXSW_SP_SB_CM(0, 7, 0), 533 MLXSW_SP_SB_CM_ING(0, 7),
482 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), 534 MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
483 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), 535 MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
484 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), 536 MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
485 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), 537 MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
486 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), 538 MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
487 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), 539 MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
488 MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), 540 MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
489 MLXSW_SP_SB_CM(0, 0, 0), /* dummy, this PG does not exist */ 541 MLXSW_SP_SB_CM_ING(0, 0), /* dummy, this PG does not exist */
490 MLXSW_SP_SB_CM(20000, 1, 3), 542 MLXSW_SP_SB_CM(10000, 8, MLXSW_SP_SB_POOL_ING_CPU),
491}; 543};
492 544
493static const struct mlxsw_sp_sb_cm mlxsw_sp1_sb_cms_egress[] = { 545static const struct mlxsw_sp_sb_cm mlxsw_sp1_sb_cms_egress[] = {
494 MLXSW_SP_SB_CM(1500, 9, 4), 546 MLXSW_SP_SB_CM_EGR(1500, 9),
495 MLXSW_SP_SB_CM(1500, 9, 4), 547 MLXSW_SP_SB_CM_EGR(1500, 9),
496 MLXSW_SP_SB_CM(1500, 9, 4), 548 MLXSW_SP_SB_CM_EGR(1500, 9),
497 MLXSW_SP_SB_CM(1500, 9, 4), 549 MLXSW_SP_SB_CM_EGR(1500, 9),
498 MLXSW_SP_SB_CM(1500, 9, 4), 550 MLXSW_SP_SB_CM_EGR(1500, 9),
499 MLXSW_SP_SB_CM(1500, 9, 4), 551 MLXSW_SP_SB_CM_EGR(1500, 9),
500 MLXSW_SP_SB_CM(1500, 9, 4), 552 MLXSW_SP_SB_CM_EGR(1500, 9),
501 MLXSW_SP_SB_CM(1500, 9, 4), 553 MLXSW_SP_SB_CM_EGR(1500, 9),
502 MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), 554 MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
503 MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), 555 MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
504 MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), 556 MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
505 MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), 557 MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
506 MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), 558 MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
507 MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), 559 MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
508 MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), 560 MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
509 MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), 561 MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
510 MLXSW_SP_SB_CM(1, 0xff, 4), 562 MLXSW_SP_SB_CM_EGR(1, 0xff),
511}; 563};
512 564
513static const struct mlxsw_sp_sb_cm mlxsw_sp2_sb_cms_egress[] = { 565static const struct mlxsw_sp_sb_cm mlxsw_sp2_sb_cms_egress[] = {
514 MLXSW_SP_SB_CM(0, 7, 4), 566 MLXSW_SP_SB_CM_EGR(0, 7),
515 MLXSW_SP_SB_CM(0, 7, 4), 567 MLXSW_SP_SB_CM_EGR(0, 7),
516 MLXSW_SP_SB_CM(0, 7, 4), 568 MLXSW_SP_SB_CM_EGR(0, 7),
517 MLXSW_SP_SB_CM(0, 7, 4), 569 MLXSW_SP_SB_CM_EGR(0, 7),
518 MLXSW_SP_SB_CM(0, 7, 4), 570 MLXSW_SP_SB_CM_EGR(0, 7),
519 MLXSW_SP_SB_CM(0, 7, 4), 571 MLXSW_SP_SB_CM_EGR(0, 7),
520 MLXSW_SP_SB_CM(0, 7, 4), 572 MLXSW_SP_SB_CM_EGR(0, 7),
521 MLXSW_SP_SB_CM(0, 7, 4), 573 MLXSW_SP_SB_CM_EGR(0, 7),
522 MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), 574 MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
523 MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), 575 MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
524 MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), 576 MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
525 MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), 577 MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
526 MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), 578 MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
527 MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), 579 MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
528 MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), 580 MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
529 MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), 581 MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
530 MLXSW_SP_SB_CM(1, 0xff, 4), 582 MLXSW_SP_SB_CM_EGR(1, 0xff),
531}; 583};
532 584
533#define MLXSW_SP_CPU_PORT_SB_CM MLXSW_SP_SB_CM(0, 0, 4) 585#define MLXSW_SP_CPU_PORT_SB_CM MLXSW_SP_SB_CM(0, 0, MLXSW_SP_SB_POOL_EGR_CPU)
534 586
535static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] = { 587static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] = {
536 MLXSW_SP_CPU_PORT_SB_CM, 588 MLXSW_SP_CPU_PORT_SB_CM,
537 MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4), 589 MLXSW_SP_SB_CM(1000, 8, MLXSW_SP_SB_POOL_EGR_CPU),
538 MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4), 590 MLXSW_SP_SB_CM(1000, 8, MLXSW_SP_SB_POOL_EGR_CPU),
539 MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4), 591 MLXSW_SP_SB_CM(1000, 8, MLXSW_SP_SB_POOL_EGR_CPU),
540 MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4), 592 MLXSW_SP_SB_CM(1000, 8, MLXSW_SP_SB_POOL_EGR_CPU),
541 MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4), 593 MLXSW_SP_SB_CM(1000, 8, MLXSW_SP_SB_POOL_EGR_CPU),
542 MLXSW_SP_CPU_PORT_SB_CM, 594 MLXSW_SP_CPU_PORT_SB_CM,
543 MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4), 595 MLXSW_SP_SB_CM(1000, 8, MLXSW_SP_SB_POOL_EGR_CPU),
544 MLXSW_SP_CPU_PORT_SB_CM, 596 MLXSW_SP_CPU_PORT_SB_CM,
545 MLXSW_SP_CPU_PORT_SB_CM, 597 MLXSW_SP_CPU_PORT_SB_CM,
546 MLXSW_SP_CPU_PORT_SB_CM, 598 MLXSW_SP_CPU_PORT_SB_CM,
@@ -648,80 +700,116 @@ static int mlxsw_sp_cpu_port_sb_cms_init(struct mlxsw_sp *mlxsw_sp)
648 .max_buff = _max_buff, \ 700 .max_buff = _max_buff, \
649 } 701 }
650 702
703/* Order according to mlxsw_sp1_sb_pool_dess */
651static const struct mlxsw_sp_sb_pm mlxsw_sp1_sb_pms[] = { 704static const struct mlxsw_sp_sb_pm mlxsw_sp1_sb_pms[] = {
652 /* Ingress pools. */
653 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX), 705 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX),
654 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN), 706 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
655 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN), 707 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
656 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX), 708 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
657 /* Egress pools. */
658 MLXSW_SP_SB_PM(0, 7), 709 MLXSW_SP_SB_PM(0, 7),
659 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN), 710 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
660 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN), 711 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
661 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN), 712 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
662 MLXSW_SP_SB_PM(10000, 90000), 713 MLXSW_SP_SB_PM(10000, 90000),
714 MLXSW_SP_SB_PM(0, 8), /* 50% occupancy */
715 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
663}; 716};
664 717
718/* Order according to mlxsw_sp2_sb_pool_dess */
665static const struct mlxsw_sp_sb_pm mlxsw_sp2_sb_pms[] = { 719static const struct mlxsw_sp_sb_pm mlxsw_sp2_sb_pms[] = {
666 /* Ingress pools. */
667 MLXSW_SP_SB_PM(0, 7), 720 MLXSW_SP_SB_PM(0, 7),
668 MLXSW_SP_SB_PM(0, 0), 721 MLXSW_SP_SB_PM(0, 0),
669 MLXSW_SP_SB_PM(0, 0), 722 MLXSW_SP_SB_PM(0, 0),
670 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX), 723 MLXSW_SP_SB_PM(0, 0),
671 /* Egress pools. */
672 MLXSW_SP_SB_PM(0, 7), 724 MLXSW_SP_SB_PM(0, 7),
673 MLXSW_SP_SB_PM(0, 0), 725 MLXSW_SP_SB_PM(0, 0),
674 MLXSW_SP_SB_PM(0, 0), 726 MLXSW_SP_SB_PM(0, 0),
675 MLXSW_SP_SB_PM(0, 0), 727 MLXSW_SP_SB_PM(0, 0),
676 MLXSW_SP_SB_PM(10000, 90000), 728 MLXSW_SP_SB_PM(10000, 90000),
729 MLXSW_SP_SB_PM(0, 8), /* 50% occupancy */
730 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
677}; 731};
678 732
679static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port) 733/* Order according to mlxsw_sp*_sb_pool_dess */
734static const struct mlxsw_sp_sb_pm mlxsw_sp_cpu_port_sb_pms[] = {
735 MLXSW_SP_SB_PM(0, 0),
736 MLXSW_SP_SB_PM(0, 0),
737 MLXSW_SP_SB_PM(0, 0),
738 MLXSW_SP_SB_PM(0, 0),
739 MLXSW_SP_SB_PM(0, 0),
740 MLXSW_SP_SB_PM(0, 0),
741 MLXSW_SP_SB_PM(0, 0),
742 MLXSW_SP_SB_PM(0, 0),
743 MLXSW_SP_SB_PM(0, 90000),
744 MLXSW_SP_SB_PM(0, 0),
745 MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX),
746};
747
748static int mlxsw_sp_sb_pms_init(struct mlxsw_sp *mlxsw_sp, u8 local_port,
749 const struct mlxsw_sp_sb_pm *pms,
750 bool skip_ingress)
680{ 751{
681 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 752 int i, err;
682 int i;
683 int err;
684 753
685 for (i = 0; i < mlxsw_sp->sb_vals->pool_count; i++) { 754 for (i = 0; i < mlxsw_sp->sb_vals->pool_count; i++) {
686 const struct mlxsw_sp_sb_pm *pm = &mlxsw_sp->sb_vals->pms[i]; 755 const struct mlxsw_sp_sb_pm *pm = &pms[i];
756 const struct mlxsw_sp_sb_pool_des *des;
687 u32 max_buff; 757 u32 max_buff;
688 u32 min_buff; 758 u32 min_buff;
689 759
760 des = &mlxsw_sp->sb_vals->pool_dess[i];
761 if (skip_ingress && des->dir == MLXSW_REG_SBXX_DIR_INGRESS)
762 continue;
763
690 min_buff = mlxsw_sp_bytes_cells(mlxsw_sp, pm->min_buff); 764 min_buff = mlxsw_sp_bytes_cells(mlxsw_sp, pm->min_buff);
691 max_buff = pm->max_buff; 765 max_buff = pm->max_buff;
692 if (mlxsw_sp_sb_pool_is_static(mlxsw_sp, i)) 766 if (mlxsw_sp_sb_pool_is_static(mlxsw_sp, i))
693 max_buff = mlxsw_sp_bytes_cells(mlxsw_sp, max_buff); 767 max_buff = mlxsw_sp_bytes_cells(mlxsw_sp, max_buff);
694 err = mlxsw_sp_sb_pm_write(mlxsw_sp, mlxsw_sp_port->local_port, 768 err = mlxsw_sp_sb_pm_write(mlxsw_sp, local_port, i, min_buff,
695 i, min_buff, max_buff); 769 max_buff);
696 if (err) 770 if (err)
697 return err; 771 return err;
698 } 772 }
699 return 0; 773 return 0;
700} 774}
701 775
702#define MLXSW_SP_SB_MM(_min_buff, _max_buff, _pool) \ 776static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port)
777{
778 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
779
780 return mlxsw_sp_sb_pms_init(mlxsw_sp, mlxsw_sp_port->local_port,
781 mlxsw_sp->sb_vals->pms, false);
782}
783
784static int mlxsw_sp_cpu_port_sb_pms_init(struct mlxsw_sp *mlxsw_sp)
785{
786 return mlxsw_sp_sb_pms_init(mlxsw_sp, 0, mlxsw_sp->sb_vals->pms_cpu,
787 true);
788}
789
790#define MLXSW_SP_SB_MM(_min_buff, _max_buff) \
703 { \ 791 { \
704 .min_buff = _min_buff, \ 792 .min_buff = _min_buff, \
705 .max_buff = _max_buff, \ 793 .max_buff = _max_buff, \
706 .pool_index = _pool, \ 794 .pool_index = MLXSW_SP_SB_POOL_EGR, \
707 } 795 }
708 796
709static const struct mlxsw_sp_sb_mm mlxsw_sp_sb_mms[] = { 797static const struct mlxsw_sp_sb_mm mlxsw_sp_sb_mms[] = {
710 MLXSW_SP_SB_MM(0, 6, 4), 798 MLXSW_SP_SB_MM(0, 6),
711 MLXSW_SP_SB_MM(0, 6, 4), 799 MLXSW_SP_SB_MM(0, 6),
712 MLXSW_SP_SB_MM(0, 6, 4), 800 MLXSW_SP_SB_MM(0, 6),
713 MLXSW_SP_SB_MM(0, 6, 4), 801 MLXSW_SP_SB_MM(0, 6),
714 MLXSW_SP_SB_MM(0, 6, 4), 802 MLXSW_SP_SB_MM(0, 6),
715 MLXSW_SP_SB_MM(0, 6, 4), 803 MLXSW_SP_SB_MM(0, 6),
716 MLXSW_SP_SB_MM(0, 6, 4), 804 MLXSW_SP_SB_MM(0, 6),
717 MLXSW_SP_SB_MM(0, 6, 4), 805 MLXSW_SP_SB_MM(0, 6),
718 MLXSW_SP_SB_MM(0, 6, 4), 806 MLXSW_SP_SB_MM(0, 6),
719 MLXSW_SP_SB_MM(0, 6, 4), 807 MLXSW_SP_SB_MM(0, 6),
720 MLXSW_SP_SB_MM(0, 6, 4), 808 MLXSW_SP_SB_MM(0, 6),
721 MLXSW_SP_SB_MM(0, 6, 4), 809 MLXSW_SP_SB_MM(0, 6),
722 MLXSW_SP_SB_MM(0, 6, 4), 810 MLXSW_SP_SB_MM(0, 6),
723 MLXSW_SP_SB_MM(0, 6, 4), 811 MLXSW_SP_SB_MM(0, 6),
724 MLXSW_SP_SB_MM(0, 6, 4), 812 MLXSW_SP_SB_MM(0, 6),
725}; 813};
726 814
727static int mlxsw_sp_sb_mms_init(struct mlxsw_sp *mlxsw_sp) 815static int mlxsw_sp_sb_mms_init(struct mlxsw_sp *mlxsw_sp)
@@ -755,21 +843,22 @@ static void mlxsw_sp_pool_count(struct mlxsw_sp *mlxsw_sp,
755{ 843{
756 int i; 844 int i;
757 845
758 for (i = 0; i < mlxsw_sp->sb_vals->pool_count; ++i) 846 for (i = 0; i < mlxsw_sp->sb_vals->pool_count; ++i) {
759 if (mlxsw_sp->sb_vals->pool_dess[i].dir == 847 if (mlxsw_sp->sb_vals->pool_dess[i].dir ==
760 MLXSW_REG_SBXX_DIR_EGRESS) 848 MLXSW_REG_SBXX_DIR_INGRESS)
761 goto out; 849 (*p_ingress_len)++;
762 WARN(1, "No egress pools\n"); 850 else
851 (*p_egress_len)++;
852 }
763 853
764out: 854 WARN(*p_egress_len == 0, "No egress pools\n");
765 *p_ingress_len = i;
766 *p_egress_len = mlxsw_sp->sb_vals->pool_count - i;
767} 855}
768 856
769const struct mlxsw_sp_sb_vals mlxsw_sp1_sb_vals = { 857const struct mlxsw_sp_sb_vals mlxsw_sp1_sb_vals = {
770 .pool_count = ARRAY_SIZE(mlxsw_sp1_sb_pool_dess), 858 .pool_count = ARRAY_SIZE(mlxsw_sp1_sb_pool_dess),
771 .pool_dess = mlxsw_sp1_sb_pool_dess, 859 .pool_dess = mlxsw_sp1_sb_pool_dess,
772 .pms = mlxsw_sp1_sb_pms, 860 .pms = mlxsw_sp1_sb_pms,
861 .pms_cpu = mlxsw_sp_cpu_port_sb_pms,
773 .prs = mlxsw_sp1_sb_prs, 862 .prs = mlxsw_sp1_sb_prs,
774 .mms = mlxsw_sp_sb_mms, 863 .mms = mlxsw_sp_sb_mms,
775 .cms_ingress = mlxsw_sp1_sb_cms_ingress, 864 .cms_ingress = mlxsw_sp1_sb_cms_ingress,
@@ -785,6 +874,7 @@ const struct mlxsw_sp_sb_vals mlxsw_sp2_sb_vals = {
785 .pool_count = ARRAY_SIZE(mlxsw_sp2_sb_pool_dess), 874 .pool_count = ARRAY_SIZE(mlxsw_sp2_sb_pool_dess),
786 .pool_dess = mlxsw_sp2_sb_pool_dess, 875 .pool_dess = mlxsw_sp2_sb_pool_dess,
787 .pms = mlxsw_sp2_sb_pms, 876 .pms = mlxsw_sp2_sb_pms,
877 .pms_cpu = mlxsw_sp_cpu_port_sb_pms,
788 .prs = mlxsw_sp2_sb_prs, 878 .prs = mlxsw_sp2_sb_prs,
789 .mms = mlxsw_sp_sb_mms, 879 .mms = mlxsw_sp_sb_mms,
790 .cms_ingress = mlxsw_sp2_sb_cms_ingress, 880 .cms_ingress = mlxsw_sp2_sb_cms_ingress,
@@ -799,8 +889,8 @@ const struct mlxsw_sp_sb_vals mlxsw_sp2_sb_vals = {
799int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp) 889int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp)
800{ 890{
801 u32 max_headroom_size; 891 u32 max_headroom_size;
802 u16 ing_pool_count; 892 u16 ing_pool_count = 0;
803 u16 eg_pool_count; 893 u16 eg_pool_count = 0;
804 int err; 894 int err;
805 895
806 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, CELL_SIZE)) 896 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, CELL_SIZE))
@@ -834,6 +924,9 @@ int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp)
834 err = mlxsw_sp_cpu_port_sb_cms_init(mlxsw_sp); 924 err = mlxsw_sp_cpu_port_sb_cms_init(mlxsw_sp);
835 if (err) 925 if (err)
836 goto err_sb_cpu_port_sb_cms_init; 926 goto err_sb_cpu_port_sb_cms_init;
927 err = mlxsw_sp_cpu_port_sb_pms_init(mlxsw_sp);
928 if (err)
929 goto err_sb_cpu_port_pms_init;
837 err = mlxsw_sp_sb_mms_init(mlxsw_sp); 930 err = mlxsw_sp_sb_mms_init(mlxsw_sp);
838 if (err) 931 if (err)
839 goto err_sb_mms_init; 932 goto err_sb_mms_init;
@@ -851,6 +944,7 @@ int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp)
851 944
852err_devlink_sb_register: 945err_devlink_sb_register:
853err_sb_mms_init: 946err_sb_mms_init:
947err_sb_cpu_port_pms_init:
854err_sb_cpu_port_sb_cms_init: 948err_sb_cpu_port_sb_cms_init:
855err_sb_prs_init: 949err_sb_prs_init:
856 mlxsw_sp_sb_ports_fini(mlxsw_sp); 950 mlxsw_sp_sb_ports_fini(mlxsw_sp);
@@ -900,16 +994,32 @@ int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core,
900 994
901int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core, 995int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core,
902 unsigned int sb_index, u16 pool_index, u32 size, 996 unsigned int sb_index, u16 pool_index, u32 size,
903 enum devlink_sb_threshold_type threshold_type) 997 enum devlink_sb_threshold_type threshold_type,
998 struct netlink_ext_ack *extack)
904{ 999{
905 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 1000 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
906 u32 pool_size = mlxsw_sp_bytes_cells(mlxsw_sp, size); 1001 u32 pool_size = mlxsw_sp_bytes_cells(mlxsw_sp, size);
1002 const struct mlxsw_sp_sb_pr *pr;
907 enum mlxsw_reg_sbpr_mode mode; 1003 enum mlxsw_reg_sbpr_mode mode;
908 1004
909 if (size > MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_BUFFER_SIZE)) 1005 mode = (enum mlxsw_reg_sbpr_mode) threshold_type;
1006 pr = &mlxsw_sp->sb_vals->prs[pool_index];
1007
1008 if (size > MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_BUFFER_SIZE)) {
1009 NL_SET_ERR_MSG_MOD(extack, "Exceeded shared buffer size");
910 return -EINVAL; 1010 return -EINVAL;
1011 }
1012
1013 if (pr->freeze_mode && pr->mode != mode) {
1014 NL_SET_ERR_MSG_MOD(extack, "Changing this pool's threshold type is forbidden");
1015 return -EINVAL;
1016 };
1017
1018 if (pr->freeze_size && pr->size != size) {
1019 NL_SET_ERR_MSG_MOD(extack, "Changing this pool's size is forbidden");
1020 return -EINVAL;
1021 };
911 1022
912 mode = (enum mlxsw_reg_sbpr_mode) threshold_type;
913 return mlxsw_sp_sb_pr_write(mlxsw_sp, pool_index, mode, 1023 return mlxsw_sp_sb_pr_write(mlxsw_sp, pool_index, mode,
914 pool_size, false); 1024 pool_size, false);
915} 1025}
@@ -927,7 +1037,8 @@ static u32 mlxsw_sp_sb_threshold_out(struct mlxsw_sp *mlxsw_sp, u16 pool_index,
927} 1037}
928 1038
929static int mlxsw_sp_sb_threshold_in(struct mlxsw_sp *mlxsw_sp, u16 pool_index, 1039static int mlxsw_sp_sb_threshold_in(struct mlxsw_sp *mlxsw_sp, u16 pool_index,
930 u32 threshold, u32 *p_max_buff) 1040 u32 threshold, u32 *p_max_buff,
1041 struct netlink_ext_ack *extack)
931{ 1042{
932 struct mlxsw_sp_sb_pr *pr = mlxsw_sp_sb_pr_get(mlxsw_sp, pool_index); 1043 struct mlxsw_sp_sb_pr *pr = mlxsw_sp_sb_pr_get(mlxsw_sp, pool_index);
933 1044
@@ -936,8 +1047,10 @@ static int mlxsw_sp_sb_threshold_in(struct mlxsw_sp *mlxsw_sp, u16 pool_index,
936 1047
937 val = threshold + MLXSW_SP_SB_THRESHOLD_TO_ALPHA_OFFSET; 1048 val = threshold + MLXSW_SP_SB_THRESHOLD_TO_ALPHA_OFFSET;
938 if (val < MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN || 1049 if (val < MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN ||
939 val > MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX) 1050 val > MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX) {
1051 NL_SET_ERR_MSG_MOD(extack, "Invalid dynamic threshold value");
940 return -EINVAL; 1052 return -EINVAL;
1053 }
941 *p_max_buff = val; 1054 *p_max_buff = val;
942 } else { 1055 } else {
943 *p_max_buff = mlxsw_sp_bytes_cells(mlxsw_sp, threshold); 1056 *p_max_buff = mlxsw_sp_bytes_cells(mlxsw_sp, threshold);
@@ -963,7 +1076,7 @@ int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
963 1076
964int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port, 1077int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
965 unsigned int sb_index, u16 pool_index, 1078 unsigned int sb_index, u16 pool_index,
966 u32 threshold) 1079 u32 threshold, struct netlink_ext_ack *extack)
967{ 1080{
968 struct mlxsw_sp_port *mlxsw_sp_port = 1081 struct mlxsw_sp_port *mlxsw_sp_port =
969 mlxsw_core_port_driver_priv(mlxsw_core_port); 1082 mlxsw_core_port_driver_priv(mlxsw_core_port);
@@ -973,7 +1086,7 @@ int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
973 int err; 1086 int err;
974 1087
975 err = mlxsw_sp_sb_threshold_in(mlxsw_sp, pool_index, 1088 err = mlxsw_sp_sb_threshold_in(mlxsw_sp, pool_index,
976 threshold, &max_buff); 1089 threshold, &max_buff, extack);
977 if (err) 1090 if (err)
978 return err; 1091 return err;
979 1092
@@ -1004,22 +1117,41 @@ int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
1004int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port, 1117int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port,
1005 unsigned int sb_index, u16 tc_index, 1118 unsigned int sb_index, u16 tc_index,
1006 enum devlink_sb_pool_type pool_type, 1119 enum devlink_sb_pool_type pool_type,
1007 u16 pool_index, u32 threshold) 1120 u16 pool_index, u32 threshold,
1121 struct netlink_ext_ack *extack)
1008{ 1122{
1009 struct mlxsw_sp_port *mlxsw_sp_port = 1123 struct mlxsw_sp_port *mlxsw_sp_port =
1010 mlxsw_core_port_driver_priv(mlxsw_core_port); 1124 mlxsw_core_port_driver_priv(mlxsw_core_port);
1011 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1125 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1012 u8 local_port = mlxsw_sp_port->local_port; 1126 u8 local_port = mlxsw_sp_port->local_port;
1127 const struct mlxsw_sp_sb_cm *cm;
1013 u8 pg_buff = tc_index; 1128 u8 pg_buff = tc_index;
1014 enum mlxsw_reg_sbxx_dir dir = (enum mlxsw_reg_sbxx_dir) pool_type; 1129 enum mlxsw_reg_sbxx_dir dir = (enum mlxsw_reg_sbxx_dir) pool_type;
1015 u32 max_buff; 1130 u32 max_buff;
1016 int err; 1131 int err;
1017 1132
1018 if (dir != mlxsw_sp->sb_vals->pool_dess[pool_index].dir) 1133 if (dir != mlxsw_sp->sb_vals->pool_dess[pool_index].dir) {
1134 NL_SET_ERR_MSG_MOD(extack, "Binding egress TC to ingress pool and vice versa is forbidden");
1019 return -EINVAL; 1135 return -EINVAL;
1136 }
1137
1138 if (dir == MLXSW_REG_SBXX_DIR_INGRESS)
1139 cm = &mlxsw_sp->sb_vals->cms_ingress[tc_index];
1140 else
1141 cm = &mlxsw_sp->sb_vals->cms_egress[tc_index];
1142
1143 if (cm->freeze_pool && cm->pool_index != pool_index) {
1144 NL_SET_ERR_MSG_MOD(extack, "Binding this TC to a different pool is forbidden");
1145 return -EINVAL;
1146 }
1147
1148 if (cm->freeze_thresh && cm->max_buff != threshold) {
1149 NL_SET_ERR_MSG_MOD(extack, "Changing this TC's threshold is forbidden");
1150 return -EINVAL;
1151 }
1020 1152
1021 err = mlxsw_sp_sb_threshold_in(mlxsw_sp, pool_index, 1153 err = mlxsw_sp_sb_threshold_in(mlxsw_sp, pool_index,
1022 threshold, &max_buff); 1154 threshold, &max_buff, extack);
1023 if (err) 1155 if (err)
1024 return err; 1156 return err;
1025 1157
diff --git a/drivers/net/ethernet/netronome/nfp/nfp_devlink.c b/drivers/net/ethernet/netronome/nfp/nfp_devlink.c
index 8e7591241e7c..c50fce42f473 100644
--- a/drivers/net/ethernet/netronome/nfp/nfp_devlink.c
+++ b/drivers/net/ethernet/netronome/nfp/nfp_devlink.c
@@ -144,7 +144,8 @@ nfp_devlink_sb_pool_get(struct devlink *devlink, unsigned int sb_index,
144static int 144static int
145nfp_devlink_sb_pool_set(struct devlink *devlink, unsigned int sb_index, 145nfp_devlink_sb_pool_set(struct devlink *devlink, unsigned int sb_index,
146 u16 pool_index, 146 u16 pool_index,
147 u32 size, enum devlink_sb_threshold_type threshold_type) 147 u32 size, enum devlink_sb_threshold_type threshold_type,
148 struct netlink_ext_ack *extack)
148{ 149{
149 struct nfp_pf *pf = devlink_priv(devlink); 150 struct nfp_pf *pf = devlink_priv(devlink);
150 151
diff --git a/include/net/devlink.h b/include/net/devlink.h
index 70c7d1ac8344..4f5e41613503 100644
--- a/include/net/devlink.h
+++ b/include/net/devlink.h
@@ -491,13 +491,14 @@ struct devlink_ops {
491 struct devlink_sb_pool_info *pool_info); 491 struct devlink_sb_pool_info *pool_info);
492 int (*sb_pool_set)(struct devlink *devlink, unsigned int sb_index, 492 int (*sb_pool_set)(struct devlink *devlink, unsigned int sb_index,
493 u16 pool_index, u32 size, 493 u16 pool_index, u32 size,
494 enum devlink_sb_threshold_type threshold_type); 494 enum devlink_sb_threshold_type threshold_type,
495 struct netlink_ext_ack *extack);
495 int (*sb_port_pool_get)(struct devlink_port *devlink_port, 496 int (*sb_port_pool_get)(struct devlink_port *devlink_port,
496 unsigned int sb_index, u16 pool_index, 497 unsigned int sb_index, u16 pool_index,
497 u32 *p_threshold); 498 u32 *p_threshold);
498 int (*sb_port_pool_set)(struct devlink_port *devlink_port, 499 int (*sb_port_pool_set)(struct devlink_port *devlink_port,
499 unsigned int sb_index, u16 pool_index, 500 unsigned int sb_index, u16 pool_index,
500 u32 threshold); 501 u32 threshold, struct netlink_ext_ack *extack);
501 int (*sb_tc_pool_bind_get)(struct devlink_port *devlink_port, 502 int (*sb_tc_pool_bind_get)(struct devlink_port *devlink_port,
502 unsigned int sb_index, 503 unsigned int sb_index,
503 u16 tc_index, 504 u16 tc_index,
@@ -507,7 +508,8 @@ struct devlink_ops {
507 unsigned int sb_index, 508 unsigned int sb_index,
508 u16 tc_index, 509 u16 tc_index,
509 enum devlink_sb_pool_type pool_type, 510 enum devlink_sb_pool_type pool_type,
510 u16 pool_index, u32 threshold); 511 u16 pool_index, u32 threshold,
512 struct netlink_ext_ack *extack);
511 int (*sb_occ_snapshot)(struct devlink *devlink, 513 int (*sb_occ_snapshot)(struct devlink *devlink,
512 unsigned int sb_index); 514 unsigned int sb_index);
513 int (*sb_occ_max_clear)(struct devlink *devlink, 515 int (*sb_occ_max_clear)(struct devlink *devlink,
diff --git a/net/core/devlink.c b/net/core/devlink.c
index b2715a187a11..7b91605e75d6 100644
--- a/net/core/devlink.c
+++ b/net/core/devlink.c
@@ -1047,14 +1047,15 @@ out:
1047 1047
1048static int devlink_sb_pool_set(struct devlink *devlink, unsigned int sb_index, 1048static int devlink_sb_pool_set(struct devlink *devlink, unsigned int sb_index,
1049 u16 pool_index, u32 size, 1049 u16 pool_index, u32 size,
1050 enum devlink_sb_threshold_type threshold_type) 1050 enum devlink_sb_threshold_type threshold_type,
1051 struct netlink_ext_ack *extack)
1051 1052
1052{ 1053{
1053 const struct devlink_ops *ops = devlink->ops; 1054 const struct devlink_ops *ops = devlink->ops;
1054 1055
1055 if (ops->sb_pool_set) 1056 if (ops->sb_pool_set)
1056 return ops->sb_pool_set(devlink, sb_index, pool_index, 1057 return ops->sb_pool_set(devlink, sb_index, pool_index,
1057 size, threshold_type); 1058 size, threshold_type, extack);
1058 return -EOPNOTSUPP; 1059 return -EOPNOTSUPP;
1059} 1060}
1060 1061
@@ -1082,7 +1083,8 @@ static int devlink_nl_cmd_sb_pool_set_doit(struct sk_buff *skb,
1082 1083
1083 size = nla_get_u32(info->attrs[DEVLINK_ATTR_SB_POOL_SIZE]); 1084 size = nla_get_u32(info->attrs[DEVLINK_ATTR_SB_POOL_SIZE]);
1084 return devlink_sb_pool_set(devlink, devlink_sb->index, 1085 return devlink_sb_pool_set(devlink, devlink_sb->index,
1085 pool_index, size, threshold_type); 1086 pool_index, size, threshold_type,
1087 info->extack);
1086} 1088}
1087 1089
1088static int devlink_nl_sb_port_pool_fill(struct sk_buff *msg, 1090static int devlink_nl_sb_port_pool_fill(struct sk_buff *msg,
@@ -1243,14 +1245,15 @@ out:
1243 1245
1244static int devlink_sb_port_pool_set(struct devlink_port *devlink_port, 1246static int devlink_sb_port_pool_set(struct devlink_port *devlink_port,
1245 unsigned int sb_index, u16 pool_index, 1247 unsigned int sb_index, u16 pool_index,
1246 u32 threshold) 1248 u32 threshold,
1249 struct netlink_ext_ack *extack)
1247 1250
1248{ 1251{
1249 const struct devlink_ops *ops = devlink_port->devlink->ops; 1252 const struct devlink_ops *ops = devlink_port->devlink->ops;
1250 1253
1251 if (ops->sb_port_pool_set) 1254 if (ops->sb_port_pool_set)
1252 return ops->sb_port_pool_set(devlink_port, sb_index, 1255 return ops->sb_port_pool_set(devlink_port, sb_index,
1253 pool_index, threshold); 1256 pool_index, threshold, extack);
1254 return -EOPNOTSUPP; 1257 return -EOPNOTSUPP;
1255} 1258}
1256 1259
@@ -1273,7 +1276,7 @@ static int devlink_nl_cmd_sb_port_pool_set_doit(struct sk_buff *skb,
1273 1276
1274 threshold = nla_get_u32(info->attrs[DEVLINK_ATTR_SB_THRESHOLD]); 1277 threshold = nla_get_u32(info->attrs[DEVLINK_ATTR_SB_THRESHOLD]);
1275 return devlink_sb_port_pool_set(devlink_port, devlink_sb->index, 1278 return devlink_sb_port_pool_set(devlink_port, devlink_sb->index,
1276 pool_index, threshold); 1279 pool_index, threshold, info->extack);
1277} 1280}
1278 1281
1279static int 1282static int
@@ -1472,7 +1475,8 @@ out:
1472static int devlink_sb_tc_pool_bind_set(struct devlink_port *devlink_port, 1475static int devlink_sb_tc_pool_bind_set(struct devlink_port *devlink_port,
1473 unsigned int sb_index, u16 tc_index, 1476 unsigned int sb_index, u16 tc_index,
1474 enum devlink_sb_pool_type pool_type, 1477 enum devlink_sb_pool_type pool_type,
1475 u16 pool_index, u32 threshold) 1478 u16 pool_index, u32 threshold,
1479 struct netlink_ext_ack *extack)
1476 1480
1477{ 1481{
1478 const struct devlink_ops *ops = devlink_port->devlink->ops; 1482 const struct devlink_ops *ops = devlink_port->devlink->ops;
@@ -1480,7 +1484,7 @@ static int devlink_sb_tc_pool_bind_set(struct devlink_port *devlink_port,
1480 if (ops->sb_tc_pool_bind_set) 1484 if (ops->sb_tc_pool_bind_set)
1481 return ops->sb_tc_pool_bind_set(devlink_port, sb_index, 1485 return ops->sb_tc_pool_bind_set(devlink_port, sb_index,
1482 tc_index, pool_type, 1486 tc_index, pool_type,
1483 pool_index, threshold); 1487 pool_index, threshold, extack);
1484 return -EOPNOTSUPP; 1488 return -EOPNOTSUPP;
1485} 1489}
1486 1490
@@ -1515,7 +1519,7 @@ static int devlink_nl_cmd_sb_tc_pool_bind_set_doit(struct sk_buff *skb,
1515 threshold = nla_get_u32(info->attrs[DEVLINK_ATTR_SB_THRESHOLD]); 1519 threshold = nla_get_u32(info->attrs[DEVLINK_ATTR_SB_THRESHOLD]);
1516 return devlink_sb_tc_pool_bind_set(devlink_port, devlink_sb->index, 1520 return devlink_sb_tc_pool_bind_set(devlink_port, devlink_sb->index,
1517 tc_index, pool_type, 1521 tc_index, pool_type,
1518 pool_index, threshold); 1522 pool_index, threshold, info->extack);
1519} 1523}
1520 1524
1521static int devlink_nl_cmd_sb_occ_snapshot_doit(struct sk_buff *skb, 1525static int devlink_nl_cmd_sb_occ_snapshot_doit(struct sk_buff *skb,
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-30 13:40:25 -0500