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-rw-r--r--Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt27
-rw-r--r--Documentation/devicetree/bindings/reset/fsl,imx7-src.txt7
-rw-r--r--MAINTAINERS1
-rw-r--r--arch/arm/mach-socfpga/socfpga.c3
-rw-r--r--arch/arm/mach-sunxi/sunxi.c2
-rw-r--r--drivers/reset/Kconfig12
-rw-r--r--drivers/reset/Makefile1
-rw-r--r--drivers/reset/reset-brcmstb.c132
-rw-r--r--drivers/reset/reset-imx7.c172
-rw-r--r--drivers/reset/reset-socfpga.c2
-rw-r--r--drivers/reset/reset-sunxi.c1
-rw-r--r--include/dt-bindings/reset/amlogic,meson-g12a-reset.h134
-rw-r--r--include/dt-bindings/reset/imx8mq-reset.h64
-rw-r--r--include/linux/reset/socfpga.h7
-rw-r--r--include/linux/reset/sunxi.h7
15 files changed, 550 insertions, 22 deletions
diff --git a/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt b/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt
new file mode 100644
index 000000000000..6e5341b4f891
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt
@@ -0,0 +1,27 @@
1Broadcom STB SW_INIT-style reset controller
2===========================================
3
4Broadcom STB SoCs have a SW_INIT-style reset controller with separate
5SET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit
6reset lines.
7
8Please also refer to reset.txt in this directory for common reset
9controller binding usage.
10
11Required properties:
12- compatible: should be brcm,brcmstb-reset
13- reg: register base and length
14- #reset-cells: must be set to 1
15
16Example:
17
18 reset: reset-controller@8404318 {
19 compatible = "brcm,brcmstb-reset";
20 reg = <0x8404318 0x30>;
21 #reset-cells = <1>;
22 };
23
24 &ethernet_switch {
25 resets = <&reset>;
26 reset-names = "switch";
27 };
diff --git a/Documentation/devicetree/bindings/reset/fsl,imx7-src.txt b/Documentation/devicetree/bindings/reset/fsl,imx7-src.txt
index 1ab1d109318e..2ecf33815d18 100644
--- a/Documentation/devicetree/bindings/reset/fsl,imx7-src.txt
+++ b/Documentation/devicetree/bindings/reset/fsl,imx7-src.txt
@@ -5,7 +5,9 @@ Please also refer to reset.txt in this directory for common reset
5controller binding usage. 5controller binding usage.
6 6
7Required properties: 7Required properties:
8- compatible: Should be "fsl,imx7d-src", "syscon" 8- compatible:
9 - For i.MX7 SoCs should be "fsl,imx7d-src", "syscon"
10 - For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon"
9- reg: should be register base and length as documented in the 11- reg: should be register base and length as documented in the
10 datasheet 12 datasheet
11- interrupts: Should contain SRC interrupt 13- interrupts: Should contain SRC interrupt
@@ -44,4 +46,5 @@ Example:
44 46
45 47
46For list of all valid reset indicies see 48For list of all valid reset indicies see
47<dt-bindings/reset/imx7-reset.h> 49<dt-bindings/reset/imx7-reset.h> for i.MX7 and
50<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ
diff --git a/MAINTAINERS b/MAINTAINERS
index 9f64f8d3740e..5ba2c18d4f5d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12958,6 +12958,7 @@ F: drivers/reset/
12958F: Documentation/devicetree/bindings/reset/ 12958F: Documentation/devicetree/bindings/reset/
12959F: include/dt-bindings/reset/ 12959F: include/dt-bindings/reset/
12960F: include/linux/reset.h 12960F: include/linux/reset.h
12961F: include/linux/reset/
12961F: include/linux/reset-controller.h 12962F: include/linux/reset-controller.h
12962 12963
12963RESTARTABLE SEQUENCES SUPPORT 12964RESTARTABLE SEQUENCES SUPPORT
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index afd98971d903..816da0eb6616 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -19,6 +19,7 @@
19#include <linux/of_irq.h> 19#include <linux/of_irq.h>
20#include <linux/of_platform.h> 20#include <linux/of_platform.h>
21#include <linux/reboot.h> 21#include <linux/reboot.h>
22#include <linux/reset/socfpga.h>
22 23
23#include <asm/hardware/cache-l2x0.h> 24#include <asm/hardware/cache-l2x0.h>
24#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
@@ -32,8 +33,6 @@ void __iomem *rst_manager_base_addr;
32void __iomem *sdr_ctl_base_addr; 33void __iomem *sdr_ctl_base_addr;
33unsigned long socfpga_cpu1start_addr; 34unsigned long socfpga_cpu1start_addr;
34 35
35extern void __init socfpga_reset_init(void);
36
37static void __init socfpga_sysmgr_init(void) 36static void __init socfpga_sysmgr_init(void)
38{ 37{
39 struct device_node *np; 38 struct device_node *np;
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 8a7f301839c2..933b6930f024 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -14,6 +14,7 @@
14#include <linux/clocksource.h> 14#include <linux/clocksource.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/reset/sunxi.h>
17 18
18#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
19#include <asm/secure_cntvoff.h> 20#include <asm/secure_cntvoff.h>
@@ -37,7 +38,6 @@ static const char * const sun6i_board_dt_compat[] = {
37 NULL, 38 NULL,
38}; 39};
39 40
40extern void __init sun6i_reset_init(void);
41static void __init sun6i_timer_init(void) 41static void __init sun6i_timer_init(void)
42{ 42{
43 of_clk_init(NULL); 43 of_clk_init(NULL);
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 2e01bd833ffd..2c8c23db92fb 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -40,6 +40,14 @@ config RESET_BERLIN
40 help 40 help
41 This enables the reset controller driver for Marvell Berlin SoCs. 41 This enables the reset controller driver for Marvell Berlin SoCs.
42 42
43config RESET_BRCMSTB
44 tristate "Broadcom STB reset controller"
45 depends on ARCH_BRCMSTB || COMPILE_TEST
46 default ARCH_BRCMSTB
47 help
48 This enables the reset controller driver for Broadcom STB SoCs using
49 a SUN_TOP_CTRL_SW_INIT style controller.
50
43config RESET_HSDK 51config RESET_HSDK
44 bool "Synopsys HSDK Reset Driver" 52 bool "Synopsys HSDK Reset Driver"
45 depends on HAS_IOMEM 53 depends on HAS_IOMEM
@@ -48,9 +56,9 @@ config RESET_HSDK
48 This enables the reset controller driver for HSDK board. 56 This enables the reset controller driver for HSDK board.
49 57
50config RESET_IMX7 58config RESET_IMX7
51 bool "i.MX7 Reset Driver" if COMPILE_TEST 59 bool "i.MX7/8 Reset Driver" if COMPILE_TEST
52 depends on HAS_IOMEM 60 depends on HAS_IOMEM
53 default SOC_IMX7D 61 default SOC_IMX7D || (ARM64 && ARCH_MXC)
54 select MFD_SYSCON 62 select MFD_SYSCON
55 help 63 help
56 This enables the reset controller driver for i.MX7 SoCs. 64 This enables the reset controller driver for i.MX7 SoCs.
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 573b8386d901..61456b8f659c 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
7obj-$(CONFIG_RESET_ATH79) += reset-ath79.o 7obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
8obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o 8obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
9obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o 9obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
10obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
10obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o 11obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
11obj-$(CONFIG_RESET_IMX7) += reset-imx7.o 12obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
12obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o 13obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
diff --git a/drivers/reset/reset-brcmstb.c b/drivers/reset/reset-brcmstb.c
new file mode 100644
index 000000000000..a608f445dad6
--- /dev/null
+++ b/drivers/reset/reset-brcmstb.c
@@ -0,0 +1,132 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Broadcom STB generic reset controller for SW_INIT style reset controller
4 *
5 * Author: Florian Fainelli <f.fainelli@gmail.com>
6 * Copyright (C) 2018 Broadcom
7 */
8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/platform_device.h>
14#include <linux/reset-controller.h>
15#include <linux/types.h>
16
17struct brcmstb_reset {
18 void __iomem *base;
19 struct reset_controller_dev rcdev;
20};
21
22#define SW_INIT_SET 0x00
23#define SW_INIT_CLEAR 0x04
24#define SW_INIT_STATUS 0x08
25
26#define SW_INIT_BIT(id) BIT((id) & 0x1f)
27#define SW_INIT_BANK(id) ((id) >> 5)
28
29/* A full bank contains extra registers that we are not utilizing but still
30 * qualify as a single bank.
31 */
32#define SW_INIT_BANK_SIZE 0x18
33
34static inline
35struct brcmstb_reset *to_brcmstb(struct reset_controller_dev *rcdev)
36{
37 return container_of(rcdev, struct brcmstb_reset, rcdev);
38}
39
40static int brcmstb_reset_assert(struct reset_controller_dev *rcdev,
41 unsigned long id)
42{
43 unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
44 struct brcmstb_reset *priv = to_brcmstb(rcdev);
45
46 writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_SET);
47
48 return 0;
49}
50
51static int brcmstb_reset_deassert(struct reset_controller_dev *rcdev,
52 unsigned long id)
53{
54 unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
55 struct brcmstb_reset *priv = to_brcmstb(rcdev);
56
57 writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_CLEAR);
58 /* Maximum reset delay after de-asserting a line and seeing block
59 * operation is typically 14us for the worst case, build some slack
60 * here.
61 */
62 usleep_range(100, 200);
63
64 return 0;
65}
66
67static int brcmstb_reset_status(struct reset_controller_dev *rcdev,
68 unsigned long id)
69{
70 unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
71 struct brcmstb_reset *priv = to_brcmstb(rcdev);
72
73 return readl_relaxed(priv->base + off + SW_INIT_STATUS) &
74 SW_INIT_BIT(id);
75}
76
77static const struct reset_control_ops brcmstb_reset_ops = {
78 .assert = brcmstb_reset_assert,
79 .deassert = brcmstb_reset_deassert,
80 .status = brcmstb_reset_status,
81};
82
83static int brcmstb_reset_probe(struct platform_device *pdev)
84{
85 struct device *kdev = &pdev->dev;
86 struct brcmstb_reset *priv;
87 struct resource *res;
88
89 priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
90 if (!priv)
91 return -ENOMEM;
92
93 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
94 if (!IS_ALIGNED(res->start, SW_INIT_BANK_SIZE) ||
95 !IS_ALIGNED(resource_size(res), SW_INIT_BANK_SIZE)) {
96 dev_err(kdev, "incorrect register range\n");
97 return -EINVAL;
98 }
99
100 priv->base = devm_ioremap_resource(kdev, res);
101 if (IS_ERR(priv->base))
102 return PTR_ERR(priv->base);
103
104 dev_set_drvdata(kdev, priv);
105
106 priv->rcdev.owner = THIS_MODULE;
107 priv->rcdev.nr_resets = DIV_ROUND_DOWN_ULL(resource_size(res),
108 SW_INIT_BANK_SIZE) * 32;
109 priv->rcdev.ops = &brcmstb_reset_ops;
110 priv->rcdev.of_node = kdev->of_node;
111 /* Use defaults: 1 cell and simple xlate function */
112
113 return devm_reset_controller_register(kdev, &priv->rcdev);
114}
115
116static const struct of_device_id brcmstb_reset_of_match[] = {
117 { .compatible = "brcm,brcmstb-reset" },
118 { /* sentinel */ }
119};
120
121static struct platform_driver brcmstb_reset_driver = {
122 .probe = brcmstb_reset_probe,
123 .driver = {
124 .name = "brcmstb-reset",
125 .of_match_table = brcmstb_reset_of_match,
126 },
127};
128module_platform_driver(brcmstb_reset_driver);
129
130MODULE_AUTHOR("Broadcom");
131MODULE_DESCRIPTION("Broadcom STB reset controller");
132MODULE_LICENSE("GPL");
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index 77911fa8f31d..aed76e33a0a9 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -17,14 +17,27 @@
17 17
18#include <linux/mfd/syscon.h> 18#include <linux/mfd/syscon.h>
19#include <linux/mod_devicetable.h> 19#include <linux/mod_devicetable.h>
20#include <linux/of_device.h>
20#include <linux/platform_device.h> 21#include <linux/platform_device.h>
21#include <linux/reset-controller.h> 22#include <linux/reset-controller.h>
22#include <linux/regmap.h> 23#include <linux/regmap.h>
23#include <dt-bindings/reset/imx7-reset.h> 24#include <dt-bindings/reset/imx7-reset.h>
25#include <dt-bindings/reset/imx8mq-reset.h>
26
27struct imx7_src_signal {
28 unsigned int offset, bit;
29};
30
31struct imx7_src_variant {
32 const struct imx7_src_signal *signals;
33 unsigned int signals_num;
34 struct reset_control_ops ops;
35};
24 36
25struct imx7_src { 37struct imx7_src {
26 struct reset_controller_dev rcdev; 38 struct reset_controller_dev rcdev;
27 struct regmap *regmap; 39 struct regmap *regmap;
40 const struct imx7_src_signal *signals;
28}; 41};
29 42
30enum imx7_src_registers { 43enum imx7_src_registers {
@@ -39,9 +52,14 @@ enum imx7_src_registers {
39 SRC_DDRC_RCR = 0x1000, 52 SRC_DDRC_RCR = 0x1000,
40}; 53};
41 54
42struct imx7_src_signal { 55static int imx7_reset_update(struct imx7_src *imx7src,
43 unsigned int offset, bit; 56 unsigned long id, unsigned int value)
44}; 57{
58 const struct imx7_src_signal *signal = &imx7src->signals[id];
59
60 return regmap_update_bits(imx7src->regmap,
61 signal->offset, signal->bit, value);
62}
45 63
46static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = { 64static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
47 [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) }, 65 [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
@@ -81,8 +99,8 @@ static int imx7_reset_set(struct reset_controller_dev *rcdev,
81 unsigned long id, bool assert) 99 unsigned long id, bool assert)
82{ 100{
83 struct imx7_src *imx7src = to_imx7_src(rcdev); 101 struct imx7_src *imx7src = to_imx7_src(rcdev);
84 const struct imx7_src_signal *signal = &imx7_src_signals[id]; 102 const unsigned int bit = imx7src->signals[id].bit;
85 unsigned int value = assert ? signal->bit : 0; 103 unsigned int value = assert ? bit : 0;
86 104
87 switch (id) { 105 switch (id) {
88 case IMX7_RESET_PCIEPHY: 106 case IMX7_RESET_PCIEPHY:
@@ -95,12 +113,11 @@ static int imx7_reset_set(struct reset_controller_dev *rcdev,
95 break; 113 break;
96 114
97 case IMX7_RESET_PCIE_CTRL_APPS_EN: 115 case IMX7_RESET_PCIE_CTRL_APPS_EN:
98 value = (assert) ? 0 : signal->bit; 116 value = assert ? 0 : bit;
99 break; 117 break;
100 } 118 }
101 119
102 return regmap_update_bits(imx7src->regmap, 120 return imx7_reset_update(imx7src, id, value);
103 signal->offset, signal->bit, value);
104} 121}
105 122
106static int imx7_reset_assert(struct reset_controller_dev *rcdev, 123static int imx7_reset_assert(struct reset_controller_dev *rcdev,
@@ -115,9 +132,133 @@ static int imx7_reset_deassert(struct reset_controller_dev *rcdev,
115 return imx7_reset_set(rcdev, id, false); 132 return imx7_reset_set(rcdev, id, false);
116} 133}
117 134
118static const struct reset_control_ops imx7_reset_ops = { 135static const struct imx7_src_variant variant_imx7 = {
119 .assert = imx7_reset_assert, 136 .signals = imx7_src_signals,
120 .deassert = imx7_reset_deassert, 137 .signals_num = ARRAY_SIZE(imx7_src_signals),
138 .ops = {
139 .assert = imx7_reset_assert,
140 .deassert = imx7_reset_deassert,
141 },
142};
143
144enum imx8mq_src_registers {
145 SRC_A53RCR0 = 0x0004,
146 SRC_HDMI_RCR = 0x0030,
147 SRC_DISP_RCR = 0x0034,
148 SRC_GPU_RCR = 0x0040,
149 SRC_VPU_RCR = 0x0044,
150 SRC_PCIE2_RCR = 0x0048,
151 SRC_MIPIPHY1_RCR = 0x004c,
152 SRC_MIPIPHY2_RCR = 0x0050,
153 SRC_DDRC2_RCR = 0x1004,
154};
155
156static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
157 [IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
158 [IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
159 [IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
160 [IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
161 [IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
162 [IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
163 [IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
164 [IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
165 [IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
166 [IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
167 [IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
168 [IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
169 [IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
170 [IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
171 [IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
172 [IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
173 [IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
174 [IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
175 [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) },
176 [IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
177 [IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
178 [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) },
179 [IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) },
180 [IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) },
181 [IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) },
182 [IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) },
183 [IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR,
184 BIT(2) | BIT(1) },
185 [IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
186 [IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
187 [IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
188 [IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
189 [IMX8MQ_RESET_DISP_RESET] = { SRC_DISP_RCR, BIT(0) },
190 [IMX8MQ_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
191 [IMX8MQ_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
192 [IMX8MQ_RESET_PCIEPHY2] = { SRC_PCIE2_RCR,
193 BIT(2) | BIT(1) },
194 [IMX8MQ_RESET_PCIEPHY2_PERST] = { SRC_PCIE2_RCR, BIT(3) },
195 [IMX8MQ_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, BIT(6) },
196 [IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, BIT(11) },
197 [IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) },
198 [IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET] = { SRC_MIPIPHY1_RCR, BIT(1) },
199 [IMX8MQ_RESET_MIPI_CSI1_ESC_RESET] = { SRC_MIPIPHY1_RCR, BIT(2) },
200 [IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) },
201 [IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET] = { SRC_MIPIPHY2_RCR, BIT(1) },
202 [IMX8MQ_RESET_MIPI_CSI2_ESC_RESET] = { SRC_MIPIPHY2_RCR, BIT(2) },
203 [IMX8MQ_RESET_DDRC1_PRST] = { SRC_DDRC_RCR, BIT(0) },
204 [IMX8MQ_RESET_DDRC1_CORE_RESET] = { SRC_DDRC_RCR, BIT(1) },
205 [IMX8MQ_RESET_DDRC1_PHY_RESET] = { SRC_DDRC_RCR, BIT(2) },
206 [IMX8MQ_RESET_DDRC2_PHY_RESET] = { SRC_DDRC2_RCR, BIT(0) },
207 [IMX8MQ_RESET_DDRC2_CORE_RESET] = { SRC_DDRC2_RCR, BIT(1) },
208 [IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) },
209};
210
211static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
212 unsigned long id, bool assert)
213{
214 struct imx7_src *imx7src = to_imx7_src(rcdev);
215 const unsigned int bit = imx7src->signals[id].bit;
216 unsigned int value = assert ? bit : 0;
217
218 switch (id) {
219 case IMX8MQ_RESET_PCIEPHY:
220 case IMX8MQ_RESET_PCIEPHY2: /* fallthrough */
221 /*
222 * wait for more than 10us to release phy g_rst and
223 * btnrst
224 */
225 if (!assert)
226 udelay(10);
227 break;
228
229 case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
230 case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */
231 case IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N: /* fallthrough */
232 case IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N: /* fallthrough */
233 case IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N: /* fallthrough */
234 case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */
235 case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */
236 value = assert ? 0 : bit;
237 break;
238 }
239
240 return imx7_reset_update(imx7src, id, value);
241}
242
243static int imx8mq_reset_assert(struct reset_controller_dev *rcdev,
244 unsigned long id)
245{
246 return imx8mq_reset_set(rcdev, id, true);
247}
248
249static int imx8mq_reset_deassert(struct reset_controller_dev *rcdev,
250 unsigned long id)
251{
252 return imx8mq_reset_set(rcdev, id, false);
253}
254
255static const struct imx7_src_variant variant_imx8mq = {
256 .signals = imx8mq_src_signals,
257 .signals_num = ARRAY_SIZE(imx8mq_src_signals),
258 .ops = {
259 .assert = imx8mq_reset_assert,
260 .deassert = imx8mq_reset_deassert,
261 },
121}; 262};
122 263
123static int imx7_reset_probe(struct platform_device *pdev) 264static int imx7_reset_probe(struct platform_device *pdev)
@@ -125,11 +266,13 @@ static int imx7_reset_probe(struct platform_device *pdev)
125 struct imx7_src *imx7src; 266 struct imx7_src *imx7src;
126 struct device *dev = &pdev->dev; 267 struct device *dev = &pdev->dev;
127 struct regmap_config config = { .name = "src" }; 268 struct regmap_config config = { .name = "src" };
269 const struct imx7_src_variant *variant = of_device_get_match_data(dev);
128 270
129 imx7src = devm_kzalloc(dev, sizeof(*imx7src), GFP_KERNEL); 271 imx7src = devm_kzalloc(dev, sizeof(*imx7src), GFP_KERNEL);
130 if (!imx7src) 272 if (!imx7src)
131 return -ENOMEM; 273 return -ENOMEM;
132 274
275 imx7src->signals = variant->signals;
133 imx7src->regmap = syscon_node_to_regmap(dev->of_node); 276 imx7src->regmap = syscon_node_to_regmap(dev->of_node);
134 if (IS_ERR(imx7src->regmap)) { 277 if (IS_ERR(imx7src->regmap)) {
135 dev_err(dev, "Unable to get imx7-src regmap"); 278 dev_err(dev, "Unable to get imx7-src regmap");
@@ -138,15 +281,16 @@ static int imx7_reset_probe(struct platform_device *pdev)
138 regmap_attach_dev(dev, imx7src->regmap, &config); 281 regmap_attach_dev(dev, imx7src->regmap, &config);
139 282
140 imx7src->rcdev.owner = THIS_MODULE; 283 imx7src->rcdev.owner = THIS_MODULE;
141 imx7src->rcdev.nr_resets = IMX7_RESET_NUM; 284 imx7src->rcdev.nr_resets = variant->signals_num;
142 imx7src->rcdev.ops = &imx7_reset_ops; 285 imx7src->rcdev.ops = &variant->ops;
143 imx7src->rcdev.of_node = dev->of_node; 286 imx7src->rcdev.of_node = dev->of_node;
144 287
145 return devm_reset_controller_register(dev, &imx7src->rcdev); 288 return devm_reset_controller_register(dev, &imx7src->rcdev);
146} 289}
147 290
148static const struct of_device_id imx7_reset_dt_ids[] = { 291static const struct of_device_id imx7_reset_dt_ids[] = {
149 { .compatible = "fsl,imx7d-src", }, 292 { .compatible = "fsl,imx7d-src", .data = &variant_imx7 },
293 { .compatible = "fsl,imx8mq-src", .data = &variant_imx8mq },
150 { /* sentinel */ }, 294 { /* sentinel */ },
151}; 295};
152 296
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index 318cfc51c441..96953992c2bb 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -11,6 +11,7 @@
11#include <linux/of_address.h> 11#include <linux/of_address.h>
12#include <linux/platform_device.h> 12#include <linux/platform_device.h>
13#include <linux/reset-controller.h> 13#include <linux/reset-controller.h>
14#include <linux/reset/socfpga.h>
14#include <linux/slab.h> 15#include <linux/slab.h>
15#include <linux/spinlock.h> 16#include <linux/spinlock.h>
16#include <linux/types.h> 17#include <linux/types.h>
@@ -18,7 +19,6 @@
18#include "reset-simple.h" 19#include "reset-simple.h"
19 20
20#define SOCFPGA_NR_BANKS 8 21#define SOCFPGA_NR_BANKS 8
21void __init socfpga_reset_init(void);
22 22
23static int a10_reset_init(struct device_node *np) 23static int a10_reset_init(struct device_node *np)
24{ 24{
diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c
index db9a1a75523f..b06d724d8f21 100644
--- a/drivers/reset/reset-sunxi.c
+++ b/drivers/reset/reset-sunxi.c
@@ -18,6 +18,7 @@
18#include <linux/of_address.h> 18#include <linux/of_address.h>
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <linux/reset-controller.h> 20#include <linux/reset-controller.h>
21#include <linux/reset/sunxi.h>
21#include <linux/slab.h> 22#include <linux/slab.h>
22#include <linux/spinlock.h> 23#include <linux/spinlock.h>
23#include <linux/types.h> 24#include <linux/types.h>
diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
new file mode 100644
index 000000000000..8063e8314eef
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
@@ -0,0 +1,134 @@
1/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
2/*
3 * Copyright (c) 2019 BayLibre, SAS.
4 * Author: Jerome Brunet <jbrunet@baylibre.com>
5 *
6 */
7
8#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
9#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
10
11/* RESET0 */
12#define RESET_HIU 0
13/* 1 */
14#define RESET_DOS 2
15/* 3-4 */
16#define RESET_VIU 5
17#define RESET_AFIFO 6
18#define RESET_VID_PLL_DIV 7
19/* 8-9 */
20#define RESET_VENC 10
21#define RESET_ASSIST 11
22#define RESET_PCIE_CTRL_A 12
23#define RESET_VCBUS 13
24#define RESET_PCIE_PHY 14
25#define RESET_PCIE_APB 15
26#define RESET_GIC 16
27#define RESET_CAPB3_DECODE 17
28/* 18 */
29#define RESET_HDMITX_CAPB3 19
30#define RESET_DVALIN_CAPB3 20
31#define RESET_DOS_CAPB3 21
32/* 22 */
33#define RESET_CBUS_CAPB3 23
34#define RESET_AHB_CNTL 24
35#define RESET_AHB_DATA 25
36#define RESET_VCBUS_CLK81 26
37/* 27-31 */
38/* RESET1 */
39/* 32 */
40#define RESET_DEMUX 33
41#define RESET_USB 34
42#define RESET_DDR 35
43/* 36 */
44#define RESET_BT656 37
45#define RESET_AHB_SRAM 38
46/* 39 */
47#define RESET_PARSER 40
48/* 41 */
49#define RESET_ISA 42
50#define RESET_ETHERNET 43
51#define RESET_SD_EMMC_A 44
52#define RESET_SD_EMMC_B 45
53#define RESET_SD_EMMC_C 46
54/* 47-60 */
55#define RESET_AUDIO_CODEC 61
56/* 62-63 */
57/* RESET2 */
58/* 64 */
59#define RESET_AUDIO 65
60#define RESET_HDMITX_PHY 66
61/* 67 */
62#define RESET_MIPI_DSI_HOST 68
63#define RESET_ALOCKER 69
64#define RESET_GE2D 70
65#define RESET_PARSER_REG 71
66#define RESET_PARSER_FETCH 72
67#define RESET_CTL 73
68#define RESET_PARSER_TOP 74
69/* 75-77 */
70#define RESET_DVALIN 78
71#define RESET_HDMITX 79
72/* 80-95 */
73/* RESET3 */
74/* 96-95 */
75#define RESET_DEMUX_TOP 105
76#define RESET_DEMUX_DES_PL 106
77#define RESET_DEMUX_S2P_0 107
78#define RESET_DEMUX_S2P_1 108
79#define RESET_DEMUX_0 109
80#define RESET_DEMUX_1 110
81#define RESET_DEMUX_2 111
82/* 112-127 */
83/* RESET4 */
84/* 128-129 */
85#define RESET_MIPI_DSI_PHY 130
86/* 131-132 */
87#define RESET_RDMA 133
88#define RESET_VENCI 134
89#define RESET_VENCP 135
90/* 136 */
91#define RESET_VDAC 137
92/* 138-139 */
93#define RESET_VDI6 140
94#define RESET_VENCL 141
95#define RESET_I2C_M1 142
96#define RESET_I2C_M2 143
97/* 144-159 */
98/* RESET5 */
99/* 160-191 */
100/* RESET6 */
101#define RESET_GEN 192
102#define RESET_SPICC0 193
103#define RESET_SC 194
104#define RESET_SANA_3 195
105#define RESET_I2C_M0 196
106#define RESET_TS_PLL 197
107#define RESET_SPICC1 198
108#define RESET_STREAM 199
109#define RESET_TS_CPU 200
110#define RESET_UART0 201
111#define RESET_UART1_2 202
112#define RESET_ASYNC0 203
113#define RESET_ASYNC1 204
114#define RESET_SPIFC0 205
115#define RESET_I2C_M3 206
116/* 207-223 */
117/* RESET7 */
118#define RESET_USB_DDR_0 224
119#define RESET_USB_DDR_1 225
120#define RESET_USB_DDR_2 226
121#define RESET_USB_DDR_3 227
122#define RESET_TS_GPU 228
123#define RESET_DEVICE_MMC_ARB 229
124#define RESET_DVALIN_DMC_PIPL 230
125#define RESET_VID_LOCK 231
126#define RESET_NIC_DMC_PIPL 232
127#define RESET_DMC_VPU_PIPL 233
128#define RESET_GE2D_DMC_PIPL 234
129#define RESET_HCODEC_DMC_PIPL 235
130#define RESET_WAVE420_DMC_PIPL 236
131#define RESET_HEVCF_DMC_PIPL 237
132/* 238-255 */
133
134#endif
diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h
new file mode 100644
index 000000000000..57c592498aa0
--- /dev/null
+++ b/include/dt-bindings/reset/imx8mq-reset.h
@@ -0,0 +1,64 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018 Zodiac Inflight Innovations
4 *
5 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
6 */
7
8#ifndef DT_BINDING_RESET_IMX8MQ_H
9#define DT_BINDING_RESET_IMX8MQ_H
10
11#define IMX8MQ_RESET_A53_CORE_POR_RESET0 0
12#define IMX8MQ_RESET_A53_CORE_POR_RESET1 1
13#define IMX8MQ_RESET_A53_CORE_POR_RESET2 2
14#define IMX8MQ_RESET_A53_CORE_POR_RESET3 3
15#define IMX8MQ_RESET_A53_CORE_RESET0 4
16#define IMX8MQ_RESET_A53_CORE_RESET1 5
17#define IMX8MQ_RESET_A53_CORE_RESET2 6
18#define IMX8MQ_RESET_A53_CORE_RESET3 7
19#define IMX8MQ_RESET_A53_DBG_RESET0 8
20#define IMX8MQ_RESET_A53_DBG_RESET1 9
21#define IMX8MQ_RESET_A53_DBG_RESET2 10
22#define IMX8MQ_RESET_A53_DBG_RESET3 11
23#define IMX8MQ_RESET_A53_ETM_RESET0 12
24#define IMX8MQ_RESET_A53_ETM_RESET1 13
25#define IMX8MQ_RESET_A53_ETM_RESET2 14
26#define IMX8MQ_RESET_A53_ETM_RESET3 15
27#define IMX8MQ_RESET_A53_SOC_DBG_RESET 16
28#define IMX8MQ_RESET_A53_L2RESET 17
29#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18
30#define IMX8MQ_RESET_OTG1_PHY_RESET 19
31#define IMX8MQ_RESET_OTG2_PHY_RESET 20
32#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21
33#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22
34#define IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N 23
35#define IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N 24
36#define IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N 25
37#define IMX8MQ_RESET_PCIEPHY 26
38#define IMX8MQ_RESET_PCIEPHY_PERST 27
39#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28
40#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29
41#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30
42#define IMX8MQ_RESET_DISP_RESET 31
43#define IMX8MQ_RESET_GPU_RESET 32
44#define IMX8MQ_RESET_VPU_RESET 33
45#define IMX8MQ_RESET_PCIEPHY2 34
46#define IMX8MQ_RESET_PCIEPHY2_PERST 35
47#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36
48#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37
49#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38
50#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39
51#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40
52#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41
53#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42
54#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43
55#define IMX8MQ_RESET_DDRC1_PRST 44
56#define IMX8MQ_RESET_DDRC1_CORE_RESET 45
57#define IMX8MQ_RESET_DDRC1_PHY_RESET 46
58#define IMX8MQ_RESET_DDRC2_PRST 47
59#define IMX8MQ_RESET_DDRC2_CORE_RESET 48
60#define IMX8MQ_RESET_DDRC2_PHY_RESET 49
61
62#define IMX8MQ_RESET_NUM 50
63
64#endif
diff --git a/include/linux/reset/socfpga.h b/include/linux/reset/socfpga.h
new file mode 100644
index 000000000000..b11a2047c342
--- /dev/null
+++ b/include/linux/reset/socfpga.h
@@ -0,0 +1,7 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __LINUX_RESET_SOCFPGA_H__
3#define __LINUX_RESET_SOCFPGA_H__
4
5void __init socfpga_reset_init(void);
6
7#endif /* __LINUX_RESET_SOCFPGA_H__ */
diff --git a/include/linux/reset/sunxi.h b/include/linux/reset/sunxi.h
new file mode 100644
index 000000000000..1ad7fffb413e
--- /dev/null
+++ b/include/linux/reset/sunxi.h
@@ -0,0 +1,7 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __LINUX_RESET_SUNXI_H__
3#define __LINUX_RESET_SUNXI_H__
4
5void __init sun6i_reset_init(void);
6
7#endif /* __LINUX_RESET_SUNXI_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-25 12:18:00 -0500