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-rw-r--r--drivers/gpu/drm/i915/i915_reg.h76
1 files changed, 38 insertions, 38 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8af945d8a995..73946055aa15 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10349,8 +10349,8 @@ enum skl_power_gate {
10349#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) 10349#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
10350 10350
10351/* Icelake Display Stream Compression Registers */ 10351/* Icelake Display Stream Compression Registers */
10352#define DSCA_PICTURE_PARAMETER_SET_0 0x6B200 10352#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
10353#define DSCC_PICTURE_PARAMETER_SET_0 0x6BA00 10353#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
10354#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 10354#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
10355#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 10355#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
10356#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 10356#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
@@ -10370,8 +10370,8 @@ enum skl_power_gate {
10370#define DSC_VER_MIN_SHIFT 4 10370#define DSC_VER_MIN_SHIFT 4
10371#define DSC_VER_MAJ (0x1 << 0) 10371#define DSC_VER_MAJ (0x1 << 0)
10372 10372
10373#define DSCA_PICTURE_PARAMETER_SET_1 0x6B204 10373#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
10374#define DSCC_PICTURE_PARAMETER_SET_1 0x6BA04 10374#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
10375#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274 10375#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
10376#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374 10376#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
10377#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474 10377#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
@@ -10384,8 +10384,8 @@ enum skl_power_gate {
10384 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC) 10384 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
10385#define DSC_BPP(bpp) ((bpp) << 0) 10385#define DSC_BPP(bpp) ((bpp) << 0)
10386 10386
10387#define DSCA_PICTURE_PARAMETER_SET_2 0x6B208 10387#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
10388#define DSCC_PICTURE_PARAMETER_SET_2 0x6BA08 10388#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
10389#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278 10389#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
10390#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378 10390#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
10391#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478 10391#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
@@ -10399,8 +10399,8 @@ enum skl_power_gate {
10399#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16) 10399#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
10400#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0) 10400#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
10401 10401
10402#define DSCA_PICTURE_PARAMETER_SET_3 0x6B20C 10402#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
10403#define DSCC_PICTURE_PARAMETER_SET_3 0x6BA0C 10403#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
10404#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C 10404#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
10405#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C 10405#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
10406#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C 10406#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
@@ -10414,8 +10414,8 @@ enum skl_power_gate {
10414#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16) 10414#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
10415#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0) 10415#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
10416 10416
10417#define DSCA_PICTURE_PARAMETER_SET_4 0x6B210 10417#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
10418#define DSCC_PICTURE_PARAMETER_SET_4 0x6BA10 10418#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
10419#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280 10419#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
10420#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380 10420#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
10421#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480 10421#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
@@ -10429,8 +10429,8 @@ enum skl_power_gate {
10429#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16) 10429#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
10430#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0) 10430#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
10431 10431
10432#define DSCA_PICTURE_PARAMETER_SET_5 0x6B214 10432#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
10433#define DSCC_PICTURE_PARAMETER_SET_5 0x6BA14 10433#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
10434#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284 10434#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
10435#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384 10435#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
10436#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484 10436#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
@@ -10441,11 +10441,11 @@ enum skl_power_gate {
10441#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 10441#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10442 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC, \ 10442 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC, \
10443 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC) 10443 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
10444#define DSC_SCALE_DEC_INTINT(scale_dec) ((scale_dec) << 16) 10444#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
10445#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0) 10445#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
10446 10446
10447#define DSCA_PICTURE_PARAMETER_SET_6 0x6B218 10447#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
10448#define DSCC_PICTURE_PARAMETER_SET_6 0x6BA18 10448#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
10449#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288 10449#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
10450#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388 10450#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
10451#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488 10451#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
@@ -10456,13 +10456,13 @@ enum skl_power_gate {
10456#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 10456#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10457 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \ 10457 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
10458 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC) 10458 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
10459#define DSC_FLATNESS_MAX_QP(max_qp) (qp << 24) 10459#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
10460#define DSC_FLATNESS_MIN_QP(min_qp) (qp << 16) 10460#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
10461#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8) 10461#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
10462#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0) 10462#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
10463 10463
10464#define DSCA_PICTURE_PARAMETER_SET_7 0x6B21C 10464#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
10465#define DSCC_PICTURE_PARAMETER_SET_7 0x6BA1C 10465#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
10466#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C 10466#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
10467#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C 10467#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
10468#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C 10468#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
@@ -10476,8 +10476,8 @@ enum skl_power_gate {
10476#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16) 10476#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
10477#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0) 10477#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
10478 10478
10479#define DSCA_PICTURE_PARAMETER_SET_8 0x6B220 10479#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
10480#define DSCC_PICTURE_PARAMETER_SET_8 0x6BA20 10480#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
10481#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290 10481#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
10482#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390 10482#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
10483#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490 10483#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
@@ -10491,8 +10491,8 @@ enum skl_power_gate {
10491#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16) 10491#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
10492#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0) 10492#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
10493 10493
10494#define DSCA_PICTURE_PARAMETER_SET_9 0x6B224 10494#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
10495#define DSCC_PICTURE_PARAMETER_SET_9 0x6BA24 10495#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
10496#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294 10496#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
10497#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394 10497#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
10498#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494 10498#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
@@ -10506,8 +10506,8 @@ enum skl_power_gate {
10506#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16) 10506#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
10507#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0) 10507#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
10508 10508
10509#define DSCA_PICTURE_PARAMETER_SET_10 0x6B228 10509#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
10510#define DSCC_PICTURE_PARAMETER_SET_10 0x6BA28 10510#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
10511#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298 10511#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
10512#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398 10512#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
10513#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498 10513#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
@@ -10523,8 +10523,8 @@ enum skl_power_gate {
10523#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8) 10523#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
10524#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0) 10524#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
10525 10525
10526#define DSCA_PICTURE_PARAMETER_SET_11 0x6B22C 10526#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
10527#define DSCC_PICTURE_PARAMETER_SET_11 0x6BA2C 10527#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
10528#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C 10528#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
10529#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C 10529#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
10530#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C 10530#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
@@ -10536,8 +10536,8 @@ enum skl_power_gate {
10536 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \ 10536 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
10537 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC) 10537 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
10538 10538
10539#define DSCA_PICTURE_PARAMETER_SET_12 0x6B260 10539#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
10540#define DSCC_PICTURE_PARAMETER_SET_12 0x6BA60 10540#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
10541#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0 10541#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
10542#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0 10542#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
10543#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0 10543#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
@@ -10549,8 +10549,8 @@ enum skl_power_gate {
10549 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \ 10549 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
10550 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC) 10550 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
10551 10551
10552#define DSCA_PICTURE_PARAMETER_SET_13 0x6B264 10552#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
10553#define DSCC_PICTURE_PARAMETER_SET_13 0x6BA64 10553#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
10554#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4 10554#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
10555#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4 10555#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
10556#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4 10556#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
@@ -10562,8 +10562,8 @@ enum skl_power_gate {
10562 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \ 10562 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
10563 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC) 10563 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
10564 10564
10565#define DSCA_PICTURE_PARAMETER_SET_14 0x6B268 10565#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
10566#define DSCC_PICTURE_PARAMETER_SET_14 0x6BA68 10566#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
10567#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8 10567#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
10568#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8 10568#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
10569#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8 10569#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
@@ -10575,8 +10575,8 @@ enum skl_power_gate {
10575 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \ 10575 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
10576 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC) 10576 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
10577 10577
10578#define DSCA_PICTURE_PARAMETER_SET_15 0x6B26C 10578#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
10579#define DSCC_PICTURE_PARAMETER_SET_15 0x6BA6C 10579#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
10580#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC 10580#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
10581#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC 10581#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
10582#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC 10582#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
@@ -10588,8 +10588,8 @@ enum skl_power_gate {
10588 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \ 10588 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
10589 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC) 10589 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
10590 10590
10591#define DSCA_PICTURE_PARAMETER_SET_16 0x6B270 10591#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
10592#define DSCC_PICTURE_PARAMETER_SET_16 0x6BA70 10592#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
10593#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0 10593#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
10594#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0 10594#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
10595#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0 10595#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
@@ -10601,7 +10601,7 @@ enum skl_power_gate {
10601 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ 10601 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
10602 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) 10602 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
10603#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) 10603#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
10604#define DSC_SLICE_CHUNK_SIZE(slice_chunk_aize) (slice_chunk_size << 0) 10604#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
10605 10605
10606/* Icelake Rate Control Buffer Threshold Registers */ 10606/* Icelake Rate Control Buffer Threshold Registers */
10607#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) 10607#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)