diff options
-rw-r--r-- | drivers/infiniband/hw/mlx5/main.c | 14 | ||||
-rw-r--r-- | drivers/infiniband/hw/mlx5/mlx5_ib.h | 3 | ||||
-rw-r--r-- | drivers/infiniband/hw/mlx5/qp.c | 59 |
3 files changed, 39 insertions, 37 deletions
diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c index d45772da0963..0c79983c8b1a 100644 --- a/drivers/infiniband/hw/mlx5/main.c +++ b/drivers/infiniband/hw/mlx5/main.c | |||
@@ -2979,6 +2979,18 @@ error_0: | |||
2979 | return ret; | 2979 | return ret; |
2980 | } | 2980 | } |
2981 | 2981 | ||
2982 | static u8 mlx5_get_umr_fence(u8 umr_fence_cap) | ||
2983 | { | ||
2984 | switch (umr_fence_cap) { | ||
2985 | case MLX5_CAP_UMR_FENCE_NONE: | ||
2986 | return MLX5_FENCE_MODE_NONE; | ||
2987 | case MLX5_CAP_UMR_FENCE_SMALL: | ||
2988 | return MLX5_FENCE_MODE_INITIATOR_SMALL; | ||
2989 | default: | ||
2990 | return MLX5_FENCE_MODE_STRONG_ORDERING; | ||
2991 | } | ||
2992 | } | ||
2993 | |||
2982 | static int create_dev_resources(struct mlx5_ib_resources *devr) | 2994 | static int create_dev_resources(struct mlx5_ib_resources *devr) |
2983 | { | 2995 | { |
2984 | struct ib_srq_init_attr attr; | 2996 | struct ib_srq_init_attr attr; |
@@ -3693,6 +3705,8 @@ static void *mlx5_ib_add(struct mlx5_core_dev *mdev) | |||
3693 | 3705 | ||
3694 | mlx5_ib_internal_fill_odp_caps(dev); | 3706 | mlx5_ib_internal_fill_odp_caps(dev); |
3695 | 3707 | ||
3708 | dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); | ||
3709 | |||
3696 | if (MLX5_CAP_GEN(mdev, imaicl)) { | 3710 | if (MLX5_CAP_GEN(mdev, imaicl)) { |
3697 | dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; | 3711 | dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; |
3698 | dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; | 3712 | dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; |
diff --git a/drivers/infiniband/hw/mlx5/mlx5_ib.h b/drivers/infiniband/hw/mlx5/mlx5_ib.h index 38c877bc45e5..bdcf25410c99 100644 --- a/drivers/infiniband/hw/mlx5/mlx5_ib.h +++ b/drivers/infiniband/hw/mlx5/mlx5_ib.h | |||
@@ -349,7 +349,7 @@ struct mlx5_ib_qp { | |||
349 | struct mlx5_ib_wq rq; | 349 | struct mlx5_ib_wq rq; |
350 | 350 | ||
351 | u8 sq_signal_bits; | 351 | u8 sq_signal_bits; |
352 | u8 fm_cache; | 352 | u8 next_fence; |
353 | struct mlx5_ib_wq sq; | 353 | struct mlx5_ib_wq sq; |
354 | 354 | ||
355 | /* serialize qp state modifications | 355 | /* serialize qp state modifications |
@@ -654,6 +654,7 @@ struct mlx5_ib_dev { | |||
654 | struct mlx5_ib_port *port; | 654 | struct mlx5_ib_port *port; |
655 | struct mlx5_sq_bfreg bfreg; | 655 | struct mlx5_sq_bfreg bfreg; |
656 | struct mlx5_sq_bfreg fp_bfreg; | 656 | struct mlx5_sq_bfreg fp_bfreg; |
657 | u8 umr_fence; | ||
657 | }; | 658 | }; |
658 | 659 | ||
659 | static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) | 660 | static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) |
diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c index 93959e1e43a3..ebb6768684de 100644 --- a/drivers/infiniband/hw/mlx5/qp.c +++ b/drivers/infiniband/hw/mlx5/qp.c | |||
@@ -3738,24 +3738,6 @@ static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) | |||
3738 | } | 3738 | } |
3739 | } | 3739 | } |
3740 | 3740 | ||
3741 | static u8 get_fence(u8 fence, struct ib_send_wr *wr) | ||
3742 | { | ||
3743 | if (unlikely(wr->opcode == IB_WR_LOCAL_INV && | ||
3744 | wr->send_flags & IB_SEND_FENCE)) | ||
3745 | return MLX5_FENCE_MODE_STRONG_ORDERING; | ||
3746 | |||
3747 | if (unlikely(fence)) { | ||
3748 | if (wr->send_flags & IB_SEND_FENCE) | ||
3749 | return MLX5_FENCE_MODE_SMALL_AND_FENCE; | ||
3750 | else | ||
3751 | return fence; | ||
3752 | } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) { | ||
3753 | return MLX5_FENCE_MODE_FENCE; | ||
3754 | } | ||
3755 | |||
3756 | return 0; | ||
3757 | } | ||
3758 | |||
3759 | static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, | 3741 | static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, |
3760 | struct mlx5_wqe_ctrl_seg **ctrl, | 3742 | struct mlx5_wqe_ctrl_seg **ctrl, |
3761 | struct ib_send_wr *wr, unsigned *idx, | 3743 | struct ib_send_wr *wr, unsigned *idx, |
@@ -3784,8 +3766,7 @@ static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, | |||
3784 | static void finish_wqe(struct mlx5_ib_qp *qp, | 3766 | static void finish_wqe(struct mlx5_ib_qp *qp, |
3785 | struct mlx5_wqe_ctrl_seg *ctrl, | 3767 | struct mlx5_wqe_ctrl_seg *ctrl, |
3786 | u8 size, unsigned idx, u64 wr_id, | 3768 | u8 size, unsigned idx, u64 wr_id, |
3787 | int nreq, u8 fence, u8 next_fence, | 3769 | int nreq, u8 fence, u32 mlx5_opcode) |
3788 | u32 mlx5_opcode) | ||
3789 | { | 3770 | { |
3790 | u8 opmod = 0; | 3771 | u8 opmod = 0; |
3791 | 3772 | ||
@@ -3793,7 +3774,6 @@ static void finish_wqe(struct mlx5_ib_qp *qp, | |||
3793 | mlx5_opcode | ((u32)opmod << 24)); | 3774 | mlx5_opcode | ((u32)opmod << 24)); |
3794 | ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); | 3775 | ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); |
3795 | ctrl->fm_ce_se |= fence; | 3776 | ctrl->fm_ce_se |= fence; |
3796 | qp->fm_cache = next_fence; | ||
3797 | if (unlikely(qp->wq_sig)) | 3777 | if (unlikely(qp->wq_sig)) |
3798 | ctrl->signature = wq_sig(ctrl); | 3778 | ctrl->signature = wq_sig(ctrl); |
3799 | 3779 | ||
@@ -3853,7 +3833,6 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |||
3853 | goto out; | 3833 | goto out; |
3854 | } | 3834 | } |
3855 | 3835 | ||
3856 | fence = qp->fm_cache; | ||
3857 | num_sge = wr->num_sge; | 3836 | num_sge = wr->num_sge; |
3858 | if (unlikely(num_sge > qp->sq.max_gs)) { | 3837 | if (unlikely(num_sge > qp->sq.max_gs)) { |
3859 | mlx5_ib_warn(dev, "\n"); | 3838 | mlx5_ib_warn(dev, "\n"); |
@@ -3870,6 +3849,19 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |||
3870 | goto out; | 3849 | goto out; |
3871 | } | 3850 | } |
3872 | 3851 | ||
3852 | if (wr->opcode == IB_WR_LOCAL_INV || | ||
3853 | wr->opcode == IB_WR_REG_MR) { | ||
3854 | fence = dev->umr_fence; | ||
3855 | next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; | ||
3856 | } else if (wr->send_flags & IB_SEND_FENCE) { | ||
3857 | if (qp->next_fence) | ||
3858 | fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; | ||
3859 | else | ||
3860 | fence = MLX5_FENCE_MODE_FENCE; | ||
3861 | } else { | ||
3862 | fence = qp->next_fence; | ||
3863 | } | ||
3864 | |||
3873 | switch (ibqp->qp_type) { | 3865 | switch (ibqp->qp_type) { |
3874 | case IB_QPT_XRC_INI: | 3866 | case IB_QPT_XRC_INI: |
3875 | xrc = seg; | 3867 | xrc = seg; |
@@ -3896,7 +3888,6 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |||
3896 | goto out; | 3888 | goto out; |
3897 | 3889 | ||
3898 | case IB_WR_LOCAL_INV: | 3890 | case IB_WR_LOCAL_INV: |
3899 | next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; | ||
3900 | qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; | 3891 | qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; |
3901 | ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); | 3892 | ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); |
3902 | set_linv_wr(qp, &seg, &size); | 3893 | set_linv_wr(qp, &seg, &size); |
@@ -3904,7 +3895,6 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |||
3904 | break; | 3895 | break; |
3905 | 3896 | ||
3906 | case IB_WR_REG_MR: | 3897 | case IB_WR_REG_MR: |
3907 | next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; | ||
3908 | qp->sq.wr_data[idx] = IB_WR_REG_MR; | 3898 | qp->sq.wr_data[idx] = IB_WR_REG_MR; |
3909 | ctrl->imm = cpu_to_be32(reg_wr(wr)->key); | 3899 | ctrl->imm = cpu_to_be32(reg_wr(wr)->key); |
3910 | err = set_reg_wr(qp, reg_wr(wr), &seg, &size); | 3900 | err = set_reg_wr(qp, reg_wr(wr), &seg, &size); |
@@ -3927,9 +3917,8 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |||
3927 | goto out; | 3917 | goto out; |
3928 | } | 3918 | } |
3929 | 3919 | ||
3930 | finish_wqe(qp, ctrl, size, idx, wr->wr_id, | 3920 | finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, |
3931 | nreq, get_fence(fence, wr), | 3921 | fence, MLX5_OPCODE_UMR); |
3932 | next_fence, MLX5_OPCODE_UMR); | ||
3933 | /* | 3922 | /* |
3934 | * SET_PSV WQEs are not signaled and solicited | 3923 | * SET_PSV WQEs are not signaled and solicited |
3935 | * on error | 3924 | * on error |
@@ -3954,9 +3943,8 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |||
3954 | goto out; | 3943 | goto out; |
3955 | } | 3944 | } |
3956 | 3945 | ||
3957 | finish_wqe(qp, ctrl, size, idx, wr->wr_id, | 3946 | finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, |
3958 | nreq, get_fence(fence, wr), | 3947 | fence, MLX5_OPCODE_SET_PSV); |
3959 | next_fence, MLX5_OPCODE_SET_PSV); | ||
3960 | err = begin_wqe(qp, &seg, &ctrl, wr, | 3948 | err = begin_wqe(qp, &seg, &ctrl, wr, |
3961 | &idx, &size, nreq); | 3949 | &idx, &size, nreq); |
3962 | if (err) { | 3950 | if (err) { |
@@ -3966,7 +3954,6 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |||
3966 | goto out; | 3954 | goto out; |
3967 | } | 3955 | } |
3968 | 3956 | ||
3969 | next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; | ||
3970 | err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, | 3957 | err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, |
3971 | mr->sig->psv_wire.psv_idx, &seg, | 3958 | mr->sig->psv_wire.psv_idx, &seg, |
3972 | &size); | 3959 | &size); |
@@ -3976,9 +3963,9 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |||
3976 | goto out; | 3963 | goto out; |
3977 | } | 3964 | } |
3978 | 3965 | ||
3979 | finish_wqe(qp, ctrl, size, idx, wr->wr_id, | 3966 | finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, |
3980 | nreq, get_fence(fence, wr), | 3967 | fence, MLX5_OPCODE_SET_PSV); |
3981 | next_fence, MLX5_OPCODE_SET_PSV); | 3968 | qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; |
3982 | num_sge = 0; | 3969 | num_sge = 0; |
3983 | goto skip_psv; | 3970 | goto skip_psv; |
3984 | 3971 | ||
@@ -4089,8 +4076,8 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |||
4089 | } | 4076 | } |
4090 | } | 4077 | } |
4091 | 4078 | ||
4092 | finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, | 4079 | qp->next_fence = next_fence; |
4093 | get_fence(fence, wr), next_fence, | 4080 | finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence, |
4094 | mlx5_ib_opcode[wr->opcode]); | 4081 | mlx5_ib_opcode[wr->opcode]); |
4095 | skip_psv: | 4082 | skip_psv: |
4096 | if (0) | 4083 | if (0) |