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-rw-r--r--Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt3
-rw-r--r--drivers/clk/meson/axg-audio.c1219
-rw-r--r--drivers/clk/meson/axg-audio.h36
-rw-r--r--include/dt-bindings/clock/axg-audio-clkc.h10
4 files changed, 736 insertions, 532 deletions
diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
index 61777ad24f61..0f777749f4f1 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
@@ -6,7 +6,8 @@ devices.
6 6
7Required Properties: 7Required Properties:
8 8
9- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D 9- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
10 "amlogic,g12a-audio-clkc" for G12A.
10- reg : physical base address of the clock controller and length of 11- reg : physical base address of the clock controller and length of
11 memory mapped region. 12 memory mapped region.
12- clocks : a list of phandle + clock-specifier pairs for the clocks listed 13- clocks : a list of phandle + clock-specifier pairs for the clocks listed
diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index 7ab200b6c3bf..8028ff6f6610 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -20,18 +20,18 @@
20#include "clk-phase.h" 20#include "clk-phase.h"
21#include "sclk-div.h" 21#include "sclk-div.h"
22 22
23#define AXG_MST_IN_COUNT 8 23#define AUD_MST_IN_COUNT 8
24#define AXG_SLV_SCLK_COUNT 10 24#define AUD_SLV_SCLK_COUNT 10
25#define AXG_SLV_LRCLK_COUNT 10 25#define AUD_SLV_LRCLK_COUNT 10
26 26
27#define AXG_AUD_GATE(_name, _reg, _bit, _pname, _iflags) \ 27#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) \
28struct clk_regmap axg_##_name = { \ 28struct clk_regmap aud_##_name = { \
29 .data = &(struct clk_regmap_gate_data){ \ 29 .data = &(struct clk_regmap_gate_data){ \
30 .offset = (_reg), \ 30 .offset = (_reg), \
31 .bit_idx = (_bit), \ 31 .bit_idx = (_bit), \
32 }, \ 32 }, \
33 .hw.init = &(struct clk_init_data) { \ 33 .hw.init = &(struct clk_init_data) { \
34 .name = "axg_"#_name, \ 34 .name = "aud_"#_name, \
35 .ops = &clk_regmap_gate_ops, \ 35 .ops = &clk_regmap_gate_ops, \
36 .parent_names = (const char *[]){ _pname }, \ 36 .parent_names = (const char *[]){ _pname }, \
37 .num_parents = 1, \ 37 .num_parents = 1, \
@@ -39,8 +39,8 @@ struct clk_regmap axg_##_name = { \
39 }, \ 39 }, \
40} 40}
41 41
42#define AXG_AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags) \ 42#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags) \
43struct clk_regmap axg_##_name = { \ 43struct clk_regmap aud_##_name = { \
44 .data = &(struct clk_regmap_mux_data){ \ 44 .data = &(struct clk_regmap_mux_data){ \
45 .offset = (_reg), \ 45 .offset = (_reg), \
46 .mask = (_mask), \ 46 .mask = (_mask), \
@@ -48,7 +48,7 @@ struct clk_regmap axg_##_name = { \
48 .flags = (_dflags), \ 48 .flags = (_dflags), \
49 }, \ 49 }, \
50 .hw.init = &(struct clk_init_data){ \ 50 .hw.init = &(struct clk_init_data){ \
51 .name = "axg_"#_name, \ 51 .name = "aud_"#_name, \
52 .ops = &clk_regmap_mux_ops, \ 52 .ops = &clk_regmap_mux_ops, \
53 .parent_names = (_pnames), \ 53 .parent_names = (_pnames), \
54 .num_parents = ARRAY_SIZE(_pnames), \ 54 .num_parents = ARRAY_SIZE(_pnames), \
@@ -56,8 +56,8 @@ struct clk_regmap axg_##_name = { \
56 }, \ 56 }, \
57} 57}
58 58
59#define AXG_AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) \ 59#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) \
60struct clk_regmap axg_##_name = { \ 60struct clk_regmap aud_##_name = { \
61 .data = &(struct clk_regmap_div_data){ \ 61 .data = &(struct clk_regmap_div_data){ \
62 .offset = (_reg), \ 62 .offset = (_reg), \
63 .shift = (_shift), \ 63 .shift = (_shift), \
@@ -65,7 +65,7 @@ struct clk_regmap axg_##_name = { \
65 .flags = (_dflags), \ 65 .flags = (_dflags), \
66 }, \ 66 }, \
67 .hw.init = &(struct clk_init_data){ \ 67 .hw.init = &(struct clk_init_data){ \
68 .name = "axg_"#_name, \ 68 .name = "aud_"#_name, \
69 .ops = &clk_regmap_divider_ops, \ 69 .ops = &clk_regmap_divider_ops, \
70 .parent_names = (const char *[]) { _pname }, \ 70 .parent_names = (const char *[]) { _pname }, \
71 .num_parents = 1, \ 71 .num_parents = 1, \
@@ -73,109 +73,113 @@ struct clk_regmap axg_##_name = { \
73 }, \ 73 }, \
74} 74}
75 75
76#define AXG_PCLK_GATE(_name, _bit) \ 76#define AUD_PCLK_GATE(_name, _bit) \
77 AXG_AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "axg_audio_pclk", 0) 77 AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "audio_pclk", 0)
78 78
79/* Audio peripheral clocks */ 79/* Audio peripheral clocks */
80static AXG_PCLK_GATE(ddr_arb, 0); 80static AUD_PCLK_GATE(ddr_arb, 0);
81static AXG_PCLK_GATE(pdm, 1); 81static AUD_PCLK_GATE(pdm, 1);
82static AXG_PCLK_GATE(tdmin_a, 2); 82static AUD_PCLK_GATE(tdmin_a, 2);
83static AXG_PCLK_GATE(tdmin_b, 3); 83static AUD_PCLK_GATE(tdmin_b, 3);
84static AXG_PCLK_GATE(tdmin_c, 4); 84static AUD_PCLK_GATE(tdmin_c, 4);
85static AXG_PCLK_GATE(tdmin_lb, 5); 85static AUD_PCLK_GATE(tdmin_lb, 5);
86static AXG_PCLK_GATE(tdmout_a, 6); 86static AUD_PCLK_GATE(tdmout_a, 6);
87static AXG_PCLK_GATE(tdmout_b, 7); 87static AUD_PCLK_GATE(tdmout_b, 7);
88static AXG_PCLK_GATE(tdmout_c, 8); 88static AUD_PCLK_GATE(tdmout_c, 8);
89static AXG_PCLK_GATE(frddr_a, 9); 89static AUD_PCLK_GATE(frddr_a, 9);
90static AXG_PCLK_GATE(frddr_b, 10); 90static AUD_PCLK_GATE(frddr_b, 10);
91static AXG_PCLK_GATE(frddr_c, 11); 91static AUD_PCLK_GATE(frddr_c, 11);
92static AXG_PCLK_GATE(toddr_a, 12); 92static AUD_PCLK_GATE(toddr_a, 12);
93static AXG_PCLK_GATE(toddr_b, 13); 93static AUD_PCLK_GATE(toddr_b, 13);
94static AXG_PCLK_GATE(toddr_c, 14); 94static AUD_PCLK_GATE(toddr_c, 14);
95static AXG_PCLK_GATE(loopback, 15); 95static AUD_PCLK_GATE(loopback, 15);
96static AXG_PCLK_GATE(spdifin, 16); 96static AUD_PCLK_GATE(spdifin, 16);
97static AXG_PCLK_GATE(spdifout, 17); 97static AUD_PCLK_GATE(spdifout, 17);
98static AXG_PCLK_GATE(resample, 18); 98static AUD_PCLK_GATE(resample, 18);
99static AXG_PCLK_GATE(power_detect, 19); 99static AUD_PCLK_GATE(power_detect, 19);
100static AUD_PCLK_GATE(spdifout_b, 21);
100 101
101/* Audio Master Clocks */ 102/* Audio Master Clocks */
102static const char * const mst_mux_parent_names[] = { 103static const char * const mst_mux_parent_names[] = {
103 "axg_mst_in0", "axg_mst_in1", "axg_mst_in2", "axg_mst_in3", 104 "aud_mst_in0", "aud_mst_in1", "aud_mst_in2", "aud_mst_in3",
104 "axg_mst_in4", "axg_mst_in5", "axg_mst_in6", "axg_mst_in7", 105 "aud_mst_in4", "aud_mst_in5", "aud_mst_in6", "aud_mst_in7",
105}; 106};
106 107
107#define AXG_MST_MUX(_name, _reg, _flag) \ 108#define AUD_MST_MUX(_name, _reg, _flag) \
108 AXG_AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \ 109 AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \
109 mst_mux_parent_names, CLK_SET_RATE_PARENT) 110 mst_mux_parent_names, CLK_SET_RATE_PARENT)
110 111
111#define AXG_MST_MCLK_MUX(_name, _reg) \ 112#define AUD_MST_MCLK_MUX(_name, _reg) \
112 AXG_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST) 113 AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
113 114
114#define AXG_MST_SYS_MUX(_name, _reg) \ 115#define AUD_MST_SYS_MUX(_name, _reg) \
115 AXG_MST_MUX(_name, _reg, 0) 116 AUD_MST_MUX(_name, _reg, 0)
116 117
117static AXG_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL); 118static AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
118static AXG_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL); 119static AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);
119static AXG_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL); 120static AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);
120static AXG_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL); 121static AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);
121static AXG_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL); 122static AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL);
122static AXG_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL); 123static AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL);
123static AXG_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); 124static AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
124static AXG_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0); 125static AUD_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
125static AXG_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); 126static AUD_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
126static AXG_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 127static AUD_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
127 128static AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
128#define AXG_MST_DIV(_name, _reg, _flag) \ 129
129 AXG_AUD_DIV(_name##_div, _reg, 0, 16, _flag, \ 130#define AUD_MST_DIV(_name, _reg, _flag) \
130 "axg_"#_name"_sel", CLK_SET_RATE_PARENT) \ 131 AUD_DIV(_name##_div, _reg, 0, 16, _flag, \
131 132 "aud_"#_name"_sel", CLK_SET_RATE_PARENT) \
132#define AXG_MST_MCLK_DIV(_name, _reg) \ 133
133 AXG_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST) 134#define AUD_MST_MCLK_DIV(_name, _reg) \
134 135 AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
135#define AXG_MST_SYS_DIV(_name, _reg) \ 136
136 AXG_MST_DIV(_name, _reg, 0) 137#define AUD_MST_SYS_DIV(_name, _reg) \
137 138 AUD_MST_DIV(_name, _reg, 0)
138static AXG_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL); 139
139static AXG_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL); 140static AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);
140static AXG_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL); 141static AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);
141static AXG_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL); 142static AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL);
142static AXG_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL); 143static AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);
143static AXG_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL); 144static AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL);
144static AXG_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); 145static AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL);
145static AXG_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0); 146static AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
146static AXG_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); 147static AUD_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
147static AXG_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 148static AUD_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
148 149static AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
149#define AXG_MST_MCLK_GATE(_name, _reg) \ 150static AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
150 AXG_AUD_GATE(_name, _reg, 31, "axg_"#_name"_div", \ 151
151 CLK_SET_RATE_PARENT) 152#define AUD_MST_MCLK_GATE(_name, _reg) \
152 153 AUD_GATE(_name, _reg, 31, "aud_"#_name"_div", \
153static AXG_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL); 154 CLK_SET_RATE_PARENT)
154static AXG_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL); 155
155static AXG_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL); 156static AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
156static AXG_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL); 157static AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL);
157static AXG_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL); 158static AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL);
158static AXG_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL); 159static AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL);
159static AXG_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); 160static AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL);
160static AXG_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); 161static AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL);
161static AXG_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0); 162static AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
162static AXG_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 163static AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
164static AUD_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
165static AUD_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
166static AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
163 167
164/* Sample Clocks */ 168/* Sample Clocks */
165#define AXG_MST_SCLK_PRE_EN(_name, _reg) \ 169#define AUD_MST_SCLK_PRE_EN(_name, _reg) \
166 AXG_AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \ 170 AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \
167 "axg_mst_"#_name"_mclk", 0) 171 "aud_mst_"#_name"_mclk", 0)
168 172
169static AXG_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0); 173static AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
170static AXG_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0); 174static AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
171static AXG_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0); 175static AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
172static AXG_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0); 176static AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
173static AXG_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0); 177static AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
174static AXG_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0); 178static AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
175 179
176#define AXG_AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ 180#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \
177 _hi_shift, _hi_width, _pname, _iflags) \ 181 _hi_shift, _hi_width, _pname, _iflags) \
178struct clk_regmap axg_##_name = { \ 182struct clk_regmap aud_##_name = { \
179 .data = &(struct meson_sclk_div_data) { \ 183 .data = &(struct meson_sclk_div_data) { \
180 .div = { \ 184 .div = { \
181 .reg_off = (_reg), \ 185 .reg_off = (_reg), \
@@ -189,7 +193,7 @@ struct clk_regmap axg_##_name = { \
189 }, \ 193 }, \
190 }, \ 194 }, \
191 .hw.init = &(struct clk_init_data) { \ 195 .hw.init = &(struct clk_init_data) { \
192 .name = "axg_"#_name, \ 196 .name = "aud_"#_name, \
193 .ops = &meson_sclk_div_ops, \ 197 .ops = &meson_sclk_div_ops, \
194 .parent_names = (const char *[]) { _pname }, \ 198 .parent_names = (const char *[]) { _pname }, \
195 .num_parents = 1, \ 199 .num_parents = 1, \
@@ -197,32 +201,32 @@ struct clk_regmap axg_##_name = { \
197 }, \ 201 }, \
198} 202}
199 203
200#define AXG_MST_SCLK_DIV(_name, _reg) \ 204#define AUD_MST_SCLK_DIV(_name, _reg) \
201 AXG_AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \ 205 AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \
202 "axg_mst_"#_name"_sclk_pre_en", \ 206 "aud_mst_"#_name"_sclk_pre_en", \
203 CLK_SET_RATE_PARENT) 207 CLK_SET_RATE_PARENT)
204 208
205static AXG_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0); 209static AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
206static AXG_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0); 210static AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
207static AXG_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0); 211static AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
208static AXG_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0); 212static AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
209static AXG_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0); 213static AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
210static AXG_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0); 214static AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
211 215
212#define AXG_MST_SCLK_POST_EN(_name, _reg) \ 216#define AUD_MST_SCLK_POST_EN(_name, _reg) \
213 AXG_AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \ 217 AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \
214 "axg_mst_"#_name"_sclk_div", CLK_SET_RATE_PARENT) 218 "aud_mst_"#_name"_sclk_div", CLK_SET_RATE_PARENT)
215 219
216static AXG_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0); 220static AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
217static AXG_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0); 221static AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
218static AXG_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0); 222static AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
219static AXG_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0); 223static AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
220static AXG_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0); 224static AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
221static AXG_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0); 225static AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
222 226
223#define AXG_AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ 227#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
224 _pname, _iflags) \ 228 _pname, _iflags) \
225struct clk_regmap axg_##_name = { \ 229struct clk_regmap aud_##_name = { \
226 .data = &(struct meson_clk_triphase_data) { \ 230 .data = &(struct meson_clk_triphase_data) { \
227 .ph0 = { \ 231 .ph0 = { \
228 .reg_off = (_reg), \ 232 .reg_off = (_reg), \
@@ -241,7 +245,7 @@ struct clk_regmap axg_##_name = { \
241 }, \ 245 }, \
242 }, \ 246 }, \
243 .hw.init = &(struct clk_init_data) { \ 247 .hw.init = &(struct clk_init_data) { \
244 .name = "axg_"#_name, \ 248 .name = "aud_"#_name, \
245 .ops = &meson_clk_triphase_ops, \ 249 .ops = &meson_clk_triphase_ops, \
246 .parent_names = (const char *[]) { _pname }, \ 250 .parent_names = (const char *[]) { _pname }, \
247 .num_parents = 1, \ 251 .num_parents = 1, \
@@ -249,87 +253,87 @@ struct clk_regmap axg_##_name = { \
249 }, \ 253 }, \
250} 254}
251 255
252#define AXG_MST_SCLK(_name, _reg) \ 256#define AUD_MST_SCLK(_name, _reg) \
253 AXG_AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \ 257 AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \
254 "axg_mst_"#_name"_sclk_post_en", CLK_SET_RATE_PARENT) 258 "aud_mst_"#_name"_sclk_post_en", CLK_SET_RATE_PARENT)
255 259
256static AXG_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1); 260static AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
257static AXG_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1); 261static AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
258static AXG_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1); 262static AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
259static AXG_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1); 263static AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
260static AXG_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1); 264static AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
261static AXG_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1); 265static AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
262 266
263#define AXG_MST_LRCLK_DIV(_name, _reg) \ 267#define AUD_MST_LRCLK_DIV(_name, _reg) \
264 AXG_AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \ 268 AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \
265 "axg_mst_"#_name"_sclk_post_en", 0) \ 269 "aud_mst_"#_name"_sclk_post_en", 0) \
266 270
267static AXG_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0); 271static AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
268static AXG_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0); 272static AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
269static AXG_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0); 273static AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
270static AXG_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0); 274static AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
271static AXG_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0); 275static AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
272static AXG_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0); 276static AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
273 277
274#define AXG_MST_LRCLK(_name, _reg) \ 278#define AUD_MST_LRCLK(_name, _reg) \
275 AXG_AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \ 279 AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \
276 "axg_mst_"#_name"_lrclk_div", CLK_SET_RATE_PARENT) 280 "aud_mst_"#_name"_lrclk_div", CLK_SET_RATE_PARENT)
277 281
278static AXG_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1); 282static AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
279static AXG_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1); 283static AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
280static AXG_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1); 284static AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
281static AXG_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1); 285static AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
282static AXG_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1); 286static AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
283static AXG_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1); 287static AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
284 288
285static const char * const tdm_sclk_parent_names[] = { 289static const char * const tdm_sclk_parent_names[] = {
286 "axg_mst_a_sclk", "axg_mst_b_sclk", "axg_mst_c_sclk", 290 "aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk",
287 "axg_mst_d_sclk", "axg_mst_e_sclk", "axg_mst_f_sclk", 291 "aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk",
288 "axg_slv_sclk0", "axg_slv_sclk1", "axg_slv_sclk2", 292 "aud_slv_sclk0", "aud_slv_sclk1", "aud_slv_sclk2",
289 "axg_slv_sclk3", "axg_slv_sclk4", "axg_slv_sclk5", 293 "aud_slv_sclk3", "aud_slv_sclk4", "aud_slv_sclk5",
290 "axg_slv_sclk6", "axg_slv_sclk7", "axg_slv_sclk8", 294 "aud_slv_sclk6", "aud_slv_sclk7", "aud_slv_sclk8",
291 "axg_slv_sclk9" 295 "aud_slv_sclk9"
292}; 296};
293 297
294#define AXG_TDM_SCLK_MUX(_name, _reg) \ 298#define AUD_TDM_SCLK_MUX(_name, _reg) \
295 AXG_AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \ 299 AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \
296 CLK_MUX_ROUND_CLOSEST, \ 300 CLK_MUX_ROUND_CLOSEST, \
297 tdm_sclk_parent_names, 0) 301 tdm_sclk_parent_names, 0)
298 302
299static AXG_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL); 303static AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);
300static AXG_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL); 304static AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);
301static AXG_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL); 305static AUD_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL);
302static AXG_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 306static AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
303static AXG_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 307static AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
304static AXG_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 308static AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
305static AXG_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 309static AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
306 310
307#define AXG_TDM_SCLK_PRE_EN(_name, _reg) \ 311#define AUD_TDM_SCLK_PRE_EN(_name, _reg) \
308 AXG_AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \ 312 AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \
309 "axg_tdm"#_name"_sclk_sel", CLK_SET_RATE_PARENT) 313 "aud_tdm"#_name"_sclk_sel", CLK_SET_RATE_PARENT)
310 314
311static AXG_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL); 315static AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
312static AXG_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL); 316static AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
313static AXG_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL); 317static AUD_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
314static AXG_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 318static AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
315static AXG_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 319static AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
316static AXG_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 320static AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
317static AXG_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 321static AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
318 322
319#define AXG_TDM_SCLK_POST_EN(_name, _reg) \ 323#define AUD_TDM_SCLK_POST_EN(_name, _reg) \
320 AXG_AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \ 324 AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \
321 "axg_tdm"#_name"_sclk_pre_en", CLK_SET_RATE_PARENT) 325 "aud_tdm"#_name"_sclk_pre_en", CLK_SET_RATE_PARENT)
322 326
323static AXG_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL); 327static AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
324static AXG_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL); 328static AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
325static AXG_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL); 329static AUD_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
326static AXG_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 330static AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
327static AXG_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 331static AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
328static AXG_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 332static AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
329static AXG_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 333static AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
330 334
331#define AXG_TDM_SCLK(_name, _reg) \ 335#define AUD_TDM_SCLK(_name, _reg) \
332 struct clk_regmap axg_tdm##_name##_sclk = { \ 336 struct clk_regmap aud_tdm##_name##_sclk = { \
333 .data = &(struct meson_clk_phase_data) { \ 337 .data = &(struct meson_clk_phase_data) { \
334 .ph = { \ 338 .ph = { \
335 .reg_off = (_reg), \ 339 .reg_off = (_reg), \
@@ -338,44 +342,83 @@ static AXG_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
338 }, \ 342 }, \
339 }, \ 343 }, \
340 .hw.init = &(struct clk_init_data) { \ 344 .hw.init = &(struct clk_init_data) { \
341 .name = "axg_tdm"#_name"_sclk", \ 345 .name = "aud_tdm"#_name"_sclk", \
342 .ops = &meson_clk_phase_ops, \ 346 .ops = &meson_clk_phase_ops, \
343 .parent_names = (const char *[]) \ 347 .parent_names = (const char *[]) \
344 { "axg_tdm"#_name"_sclk_post_en" }, \ 348 { "aud_tdm"#_name"_sclk_post_en" }, \
345 .num_parents = 1, \ 349 .num_parents = 1, \
346 .flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT, \ 350 .flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT, \
347 }, \ 351 }, \
348} 352}
349 353
350static AXG_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL); 354static AUD_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
351static AXG_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL); 355static AUD_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
352static AXG_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL); 356static AUD_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
353static AXG_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 357static AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
354static AXG_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 358static AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
355static AXG_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 359static AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
356static AXG_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 360static AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
357 361
358static const char * const tdm_lrclk_parent_names[] = { 362static const char * const tdm_lrclk_parent_names[] = {
359 "axg_mst_a_lrclk", "axg_mst_b_lrclk", "axg_mst_c_lrclk", 363 "aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk",
360 "axg_mst_d_lrclk", "axg_mst_e_lrclk", "axg_mst_f_lrclk", 364 "aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk",
361 "axg_slv_lrclk0", "axg_slv_lrclk1", "axg_slv_lrclk2", 365 "aud_slv_lrclk0", "aud_slv_lrclk1", "aud_slv_lrclk2",
362 "axg_slv_lrclk3", "axg_slv_lrclk4", "axg_slv_lrclk5", 366 "aud_slv_lrclk3", "aud_slv_lrclk4", "aud_slv_lrclk5",
363 "axg_slv_lrclk6", "axg_slv_lrclk7", "axg_slv_lrclk8", 367 "aud_slv_lrclk6", "aud_slv_lrclk7", "aud_slv_lrclk8",
364 "axg_slv_lrclk9" 368 "aud_slv_lrclk9"
365}; 369};
366 370
367#define AXG_TDM_LRLCK(_name, _reg) \ 371#define AUD_TDM_LRLCK(_name, _reg) \
368 AXG_AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \ 372 AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \
369 CLK_MUX_ROUND_CLOSEST, \ 373 CLK_MUX_ROUND_CLOSEST, \
370 tdm_lrclk_parent_names, 0) 374 tdm_lrclk_parent_names, 0)
375
376static AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
377static AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
378static AUD_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
379static AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
380static AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
381static AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
382static AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
383
384/* G12a Pad control */
385#define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents) \
386 AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents, \
387 CLK_SET_RATE_NO_REPARENT)
388
389static const char * const mclk_pad_ctrl_parent_names[] = {
390 "aud_mst_a_mclk", "aud_mst_b_mclk", "aud_mst_c_mclk",
391 "aud_mst_d_mclk", "aud_mst_e_mclk", "aud_mst_f_mclk",
392};
393
394static AUD_TDM_PAD_CTRL(mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0,
395 mclk_pad_ctrl_parent_names);
396static AUD_TDM_PAD_CTRL(mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4,
397 mclk_pad_ctrl_parent_names);
398
399static const char * const lrclk_pad_ctrl_parent_names[] = {
400 "aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk",
401 "aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk",
402};
371 403
372static AXG_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL); 404static AUD_TDM_PAD_CTRL(lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16,
373static AXG_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL); 405 lrclk_pad_ctrl_parent_names);
374static AXG_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL); 406static AUD_TDM_PAD_CTRL(lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20,
375static AXG_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 407 lrclk_pad_ctrl_parent_names);
376static AXG_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 408static AUD_TDM_PAD_CTRL(lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24,
377static AXG_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 409 lrclk_pad_ctrl_parent_names);
378static AXG_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 410
411static const char * const sclk_pad_ctrl_parent_names[] = {
412 "aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk",
413 "aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk",
414};
415
416static AUD_TDM_PAD_CTRL(sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0,
417 sclk_pad_ctrl_parent_names);
418static AUD_TDM_PAD_CTRL(sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4,
419 sclk_pad_ctrl_parent_names);
420static AUD_TDM_PAD_CTRL(sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8,
421 sclk_pad_ctrl_parent_names);
379 422
380/* 423/*
381 * Array of all clocks provided by this provider 424 * Array of all clocks provided by this provider
@@ -383,255 +426,416 @@ static AXG_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
383 */ 426 */
384static struct clk_hw_onecell_data axg_audio_hw_onecell_data = { 427static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
385 .hws = { 428 .hws = {
386 [AUD_CLKID_DDR_ARB] = &axg_ddr_arb.hw, 429 [AUD_CLKID_DDR_ARB] = &aud_ddr_arb.hw,
387 [AUD_CLKID_PDM] = &axg_pdm.hw, 430 [AUD_CLKID_PDM] = &aud_pdm.hw,
388 [AUD_CLKID_TDMIN_A] = &axg_tdmin_a.hw, 431 [AUD_CLKID_TDMIN_A] = &aud_tdmin_a.hw,
389 [AUD_CLKID_TDMIN_B] = &axg_tdmin_b.hw, 432 [AUD_CLKID_TDMIN_B] = &aud_tdmin_b.hw,
390 [AUD_CLKID_TDMIN_C] = &axg_tdmin_c.hw, 433 [AUD_CLKID_TDMIN_C] = &aud_tdmin_c.hw,
391 [AUD_CLKID_TDMIN_LB] = &axg_tdmin_lb.hw, 434 [AUD_CLKID_TDMIN_LB] = &aud_tdmin_lb.hw,
392 [AUD_CLKID_TDMOUT_A] = &axg_tdmout_a.hw, 435 [AUD_CLKID_TDMOUT_A] = &aud_tdmout_a.hw,
393 [AUD_CLKID_TDMOUT_B] = &axg_tdmout_b.hw, 436 [AUD_CLKID_TDMOUT_B] = &aud_tdmout_b.hw,
394 [AUD_CLKID_TDMOUT_C] = &axg_tdmout_c.hw, 437 [AUD_CLKID_TDMOUT_C] = &aud_tdmout_c.hw,
395 [AUD_CLKID_FRDDR_A] = &axg_frddr_a.hw, 438 [AUD_CLKID_FRDDR_A] = &aud_frddr_a.hw,
396 [AUD_CLKID_FRDDR_B] = &axg_frddr_b.hw, 439 [AUD_CLKID_FRDDR_B] = &aud_frddr_b.hw,
397 [AUD_CLKID_FRDDR_C] = &axg_frddr_c.hw, 440 [AUD_CLKID_FRDDR_C] = &aud_frddr_c.hw,
398 [AUD_CLKID_TODDR_A] = &axg_toddr_a.hw, 441 [AUD_CLKID_TODDR_A] = &aud_toddr_a.hw,
399 [AUD_CLKID_TODDR_B] = &axg_toddr_b.hw, 442 [AUD_CLKID_TODDR_B] = &aud_toddr_b.hw,
400 [AUD_CLKID_TODDR_C] = &axg_toddr_c.hw, 443 [AUD_CLKID_TODDR_C] = &aud_toddr_c.hw,
401 [AUD_CLKID_LOOPBACK] = &axg_loopback.hw, 444 [AUD_CLKID_LOOPBACK] = &aud_loopback.hw,
402 [AUD_CLKID_SPDIFIN] = &axg_spdifin.hw, 445 [AUD_CLKID_SPDIFIN] = &aud_spdifin.hw,
403 [AUD_CLKID_SPDIFOUT] = &axg_spdifout.hw, 446 [AUD_CLKID_SPDIFOUT] = &aud_spdifout.hw,
404 [AUD_CLKID_RESAMPLE] = &axg_resample.hw, 447 [AUD_CLKID_RESAMPLE] = &aud_resample.hw,
405 [AUD_CLKID_POWER_DETECT] = &axg_power_detect.hw, 448 [AUD_CLKID_POWER_DETECT] = &aud_power_detect.hw,
406 [AUD_CLKID_MST_A_MCLK_SEL] = &axg_mst_a_mclk_sel.hw, 449 [AUD_CLKID_MST_A_MCLK_SEL] = &aud_mst_a_mclk_sel.hw,
407 [AUD_CLKID_MST_B_MCLK_SEL] = &axg_mst_b_mclk_sel.hw, 450 [AUD_CLKID_MST_B_MCLK_SEL] = &aud_mst_b_mclk_sel.hw,
408 [AUD_CLKID_MST_C_MCLK_SEL] = &axg_mst_c_mclk_sel.hw, 451 [AUD_CLKID_MST_C_MCLK_SEL] = &aud_mst_c_mclk_sel.hw,
409 [AUD_CLKID_MST_D_MCLK_SEL] = &axg_mst_d_mclk_sel.hw, 452 [AUD_CLKID_MST_D_MCLK_SEL] = &aud_mst_d_mclk_sel.hw,
410 [AUD_CLKID_MST_E_MCLK_SEL] = &axg_mst_e_mclk_sel.hw, 453 [AUD_CLKID_MST_E_MCLK_SEL] = &aud_mst_e_mclk_sel.hw,
411 [AUD_CLKID_MST_F_MCLK_SEL] = &axg_mst_f_mclk_sel.hw, 454 [AUD_CLKID_MST_F_MCLK_SEL] = &aud_mst_f_mclk_sel.hw,
412 [AUD_CLKID_MST_A_MCLK_DIV] = &axg_mst_a_mclk_div.hw, 455 [AUD_CLKID_MST_A_MCLK_DIV] = &aud_mst_a_mclk_div.hw,
413 [AUD_CLKID_MST_B_MCLK_DIV] = &axg_mst_b_mclk_div.hw, 456 [AUD_CLKID_MST_B_MCLK_DIV] = &aud_mst_b_mclk_div.hw,
414 [AUD_CLKID_MST_C_MCLK_DIV] = &axg_mst_c_mclk_div.hw, 457 [AUD_CLKID_MST_C_MCLK_DIV] = &aud_mst_c_mclk_div.hw,
415 [AUD_CLKID_MST_D_MCLK_DIV] = &axg_mst_d_mclk_div.hw, 458 [AUD_CLKID_MST_D_MCLK_DIV] = &aud_mst_d_mclk_div.hw,
416 [AUD_CLKID_MST_E_MCLK_DIV] = &axg_mst_e_mclk_div.hw, 459 [AUD_CLKID_MST_E_MCLK_DIV] = &aud_mst_e_mclk_div.hw,
417 [AUD_CLKID_MST_F_MCLK_DIV] = &axg_mst_f_mclk_div.hw, 460 [AUD_CLKID_MST_F_MCLK_DIV] = &aud_mst_f_mclk_div.hw,
418 [AUD_CLKID_MST_A_MCLK] = &axg_mst_a_mclk.hw, 461 [AUD_CLKID_MST_A_MCLK] = &aud_mst_a_mclk.hw,
419 [AUD_CLKID_MST_B_MCLK] = &axg_mst_b_mclk.hw, 462 [AUD_CLKID_MST_B_MCLK] = &aud_mst_b_mclk.hw,
420 [AUD_CLKID_MST_C_MCLK] = &axg_mst_c_mclk.hw, 463 [AUD_CLKID_MST_C_MCLK] = &aud_mst_c_mclk.hw,
421 [AUD_CLKID_MST_D_MCLK] = &axg_mst_d_mclk.hw, 464 [AUD_CLKID_MST_D_MCLK] = &aud_mst_d_mclk.hw,
422 [AUD_CLKID_MST_E_MCLK] = &axg_mst_e_mclk.hw, 465 [AUD_CLKID_MST_E_MCLK] = &aud_mst_e_mclk.hw,
423 [AUD_CLKID_MST_F_MCLK] = &axg_mst_f_mclk.hw, 466 [AUD_CLKID_MST_F_MCLK] = &aud_mst_f_mclk.hw,
424 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &axg_spdifout_clk_sel.hw, 467 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &aud_spdifout_clk_sel.hw,
425 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &axg_spdifout_clk_div.hw, 468 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &aud_spdifout_clk_div.hw,
426 [AUD_CLKID_SPDIFOUT_CLK] = &axg_spdifout_clk.hw, 469 [AUD_CLKID_SPDIFOUT_CLK] = &aud_spdifout_clk.hw,
427 [AUD_CLKID_SPDIFIN_CLK_SEL] = &axg_spdifin_clk_sel.hw, 470 [AUD_CLKID_SPDIFIN_CLK_SEL] = &aud_spdifin_clk_sel.hw,
428 [AUD_CLKID_SPDIFIN_CLK_DIV] = &axg_spdifin_clk_div.hw, 471 [AUD_CLKID_SPDIFIN_CLK_DIV] = &aud_spdifin_clk_div.hw,
429 [AUD_CLKID_SPDIFIN_CLK] = &axg_spdifin_clk.hw, 472 [AUD_CLKID_SPDIFIN_CLK] = &aud_spdifin_clk.hw,
430 [AUD_CLKID_PDM_DCLK_SEL] = &axg_pdm_dclk_sel.hw, 473 [AUD_CLKID_PDM_DCLK_SEL] = &aud_pdm_dclk_sel.hw,
431 [AUD_CLKID_PDM_DCLK_DIV] = &axg_pdm_dclk_div.hw, 474 [AUD_CLKID_PDM_DCLK_DIV] = &aud_pdm_dclk_div.hw,
432 [AUD_CLKID_PDM_DCLK] = &axg_pdm_dclk.hw, 475 [AUD_CLKID_PDM_DCLK] = &aud_pdm_dclk.hw,
433 [AUD_CLKID_PDM_SYSCLK_SEL] = &axg_pdm_sysclk_sel.hw, 476 [AUD_CLKID_PDM_SYSCLK_SEL] = &aud_pdm_sysclk_sel.hw,
434 [AUD_CLKID_PDM_SYSCLK_DIV] = &axg_pdm_sysclk_div.hw, 477 [AUD_CLKID_PDM_SYSCLK_DIV] = &aud_pdm_sysclk_div.hw,
435 [AUD_CLKID_PDM_SYSCLK] = &axg_pdm_sysclk.hw, 478 [AUD_CLKID_PDM_SYSCLK] = &aud_pdm_sysclk.hw,
436 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &axg_mst_a_sclk_pre_en.hw, 479 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &aud_mst_a_sclk_pre_en.hw,
437 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &axg_mst_b_sclk_pre_en.hw, 480 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &aud_mst_b_sclk_pre_en.hw,
438 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &axg_mst_c_sclk_pre_en.hw, 481 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &aud_mst_c_sclk_pre_en.hw,
439 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &axg_mst_d_sclk_pre_en.hw, 482 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &aud_mst_d_sclk_pre_en.hw,
440 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &axg_mst_e_sclk_pre_en.hw, 483 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &aud_mst_e_sclk_pre_en.hw,
441 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &axg_mst_f_sclk_pre_en.hw, 484 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &aud_mst_f_sclk_pre_en.hw,
442 [AUD_CLKID_MST_A_SCLK_DIV] = &axg_mst_a_sclk_div.hw, 485 [AUD_CLKID_MST_A_SCLK_DIV] = &aud_mst_a_sclk_div.hw,
443 [AUD_CLKID_MST_B_SCLK_DIV] = &axg_mst_b_sclk_div.hw, 486 [AUD_CLKID_MST_B_SCLK_DIV] = &aud_mst_b_sclk_div.hw,
444 [AUD_CLKID_MST_C_SCLK_DIV] = &axg_mst_c_sclk_div.hw, 487 [AUD_CLKID_MST_C_SCLK_DIV] = &aud_mst_c_sclk_div.hw,
445 [AUD_CLKID_MST_D_SCLK_DIV] = &axg_mst_d_sclk_div.hw, 488 [AUD_CLKID_MST_D_SCLK_DIV] = &aud_mst_d_sclk_div.hw,
446 [AUD_CLKID_MST_E_SCLK_DIV] = &axg_mst_e_sclk_div.hw, 489 [AUD_CLKID_MST_E_SCLK_DIV] = &aud_mst_e_sclk_div.hw,
447 [AUD_CLKID_MST_F_SCLK_DIV] = &axg_mst_f_sclk_div.hw, 490 [AUD_CLKID_MST_F_SCLK_DIV] = &aud_mst_f_sclk_div.hw,
448 [AUD_CLKID_MST_A_SCLK_POST_EN] = &axg_mst_a_sclk_post_en.hw, 491 [AUD_CLKID_MST_A_SCLK_POST_EN] = &aud_mst_a_sclk_post_en.hw,
449 [AUD_CLKID_MST_B_SCLK_POST_EN] = &axg_mst_b_sclk_post_en.hw, 492 [AUD_CLKID_MST_B_SCLK_POST_EN] = &aud_mst_b_sclk_post_en.hw,
450 [AUD_CLKID_MST_C_SCLK_POST_EN] = &axg_mst_c_sclk_post_en.hw, 493 [AUD_CLKID_MST_C_SCLK_POST_EN] = &aud_mst_c_sclk_post_en.hw,
451 [AUD_CLKID_MST_D_SCLK_POST_EN] = &axg_mst_d_sclk_post_en.hw, 494 [AUD_CLKID_MST_D_SCLK_POST_EN] = &aud_mst_d_sclk_post_en.hw,
452 [AUD_CLKID_MST_E_SCLK_POST_EN] = &axg_mst_e_sclk_post_en.hw, 495 [AUD_CLKID_MST_E_SCLK_POST_EN] = &aud_mst_e_sclk_post_en.hw,
453 [AUD_CLKID_MST_F_SCLK_POST_EN] = &axg_mst_f_sclk_post_en.hw, 496 [AUD_CLKID_MST_F_SCLK_POST_EN] = &aud_mst_f_sclk_post_en.hw,
454 [AUD_CLKID_MST_A_SCLK] = &axg_mst_a_sclk.hw, 497 [AUD_CLKID_MST_A_SCLK] = &aud_mst_a_sclk.hw,
455 [AUD_CLKID_MST_B_SCLK] = &axg_mst_b_sclk.hw, 498 [AUD_CLKID_MST_B_SCLK] = &aud_mst_b_sclk.hw,
456 [AUD_CLKID_MST_C_SCLK] = &axg_mst_c_sclk.hw, 499 [AUD_CLKID_MST_C_SCLK] = &aud_mst_c_sclk.hw,
457 [AUD_CLKID_MST_D_SCLK] = &axg_mst_d_sclk.hw, 500 [AUD_CLKID_MST_D_SCLK] = &aud_mst_d_sclk.hw,
458 [AUD_CLKID_MST_E_SCLK] = &axg_mst_e_sclk.hw, 501 [AUD_CLKID_MST_E_SCLK] = &aud_mst_e_sclk.hw,
459 [AUD_CLKID_MST_F_SCLK] = &axg_mst_f_sclk.hw, 502 [AUD_CLKID_MST_F_SCLK] = &aud_mst_f_sclk.hw,
460 [AUD_CLKID_MST_A_LRCLK_DIV] = &axg_mst_a_lrclk_div.hw, 503 [AUD_CLKID_MST_A_LRCLK_DIV] = &aud_mst_a_lrclk_div.hw,
461 [AUD_CLKID_MST_B_LRCLK_DIV] = &axg_mst_b_lrclk_div.hw, 504 [AUD_CLKID_MST_B_LRCLK_DIV] = &aud_mst_b_lrclk_div.hw,
462 [AUD_CLKID_MST_C_LRCLK_DIV] = &axg_mst_c_lrclk_div.hw, 505 [AUD_CLKID_MST_C_LRCLK_DIV] = &aud_mst_c_lrclk_div.hw,
463 [AUD_CLKID_MST_D_LRCLK_DIV] = &axg_mst_d_lrclk_div.hw, 506 [AUD_CLKID_MST_D_LRCLK_DIV] = &aud_mst_d_lrclk_div.hw,
464 [AUD_CLKID_MST_E_LRCLK_DIV] = &axg_mst_e_lrclk_div.hw, 507 [AUD_CLKID_MST_E_LRCLK_DIV] = &aud_mst_e_lrclk_div.hw,
465 [AUD_CLKID_MST_F_LRCLK_DIV] = &axg_mst_f_lrclk_div.hw, 508 [AUD_CLKID_MST_F_LRCLK_DIV] = &aud_mst_f_lrclk_div.hw,
466 [AUD_CLKID_MST_A_LRCLK] = &axg_mst_a_lrclk.hw, 509 [AUD_CLKID_MST_A_LRCLK] = &aud_mst_a_lrclk.hw,
467 [AUD_CLKID_MST_B_LRCLK] = &axg_mst_b_lrclk.hw, 510 [AUD_CLKID_MST_B_LRCLK] = &aud_mst_b_lrclk.hw,
468 [AUD_CLKID_MST_C_LRCLK] = &axg_mst_c_lrclk.hw, 511 [AUD_CLKID_MST_C_LRCLK] = &aud_mst_c_lrclk.hw,
469 [AUD_CLKID_MST_D_LRCLK] = &axg_mst_d_lrclk.hw, 512 [AUD_CLKID_MST_D_LRCLK] = &aud_mst_d_lrclk.hw,
470 [AUD_CLKID_MST_E_LRCLK] = &axg_mst_e_lrclk.hw, 513 [AUD_CLKID_MST_E_LRCLK] = &aud_mst_e_lrclk.hw,
471 [AUD_CLKID_MST_F_LRCLK] = &axg_mst_f_lrclk.hw, 514 [AUD_CLKID_MST_F_LRCLK] = &aud_mst_f_lrclk.hw,
472 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &axg_tdmin_a_sclk_sel.hw, 515 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &aud_tdmin_a_sclk_sel.hw,
473 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &axg_tdmin_b_sclk_sel.hw, 516 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &aud_tdmin_b_sclk_sel.hw,
474 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &axg_tdmin_c_sclk_sel.hw, 517 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &aud_tdmin_c_sclk_sel.hw,
475 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &axg_tdmin_lb_sclk_sel.hw, 518 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &aud_tdmin_lb_sclk_sel.hw,
476 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &axg_tdmout_a_sclk_sel.hw, 519 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &aud_tdmout_a_sclk_sel.hw,
477 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &axg_tdmout_b_sclk_sel.hw, 520 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &aud_tdmout_b_sclk_sel.hw,
478 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &axg_tdmout_c_sclk_sel.hw, 521 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &aud_tdmout_c_sclk_sel.hw,
479 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &axg_tdmin_a_sclk_pre_en.hw, 522 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &aud_tdmin_a_sclk_pre_en.hw,
480 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &axg_tdmin_b_sclk_pre_en.hw, 523 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &aud_tdmin_b_sclk_pre_en.hw,
481 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &axg_tdmin_c_sclk_pre_en.hw, 524 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &aud_tdmin_c_sclk_pre_en.hw,
482 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &axg_tdmin_lb_sclk_pre_en.hw, 525 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &aud_tdmin_lb_sclk_pre_en.hw,
483 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &axg_tdmout_a_sclk_pre_en.hw, 526 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &aud_tdmout_a_sclk_pre_en.hw,
484 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &axg_tdmout_b_sclk_pre_en.hw, 527 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &aud_tdmout_b_sclk_pre_en.hw,
485 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &axg_tdmout_c_sclk_pre_en.hw, 528 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &aud_tdmout_c_sclk_pre_en.hw,
486 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &axg_tdmin_a_sclk_post_en.hw, 529 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &aud_tdmin_a_sclk_post_en.hw,
487 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &axg_tdmin_b_sclk_post_en.hw, 530 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &aud_tdmin_b_sclk_post_en.hw,
488 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &axg_tdmin_c_sclk_post_en.hw, 531 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &aud_tdmin_c_sclk_post_en.hw,
489 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &axg_tdmin_lb_sclk_post_en.hw, 532 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &aud_tdmin_lb_sclk_post_en.hw,
490 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &axg_tdmout_a_sclk_post_en.hw, 533 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &aud_tdmout_a_sclk_post_en.hw,
491 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &axg_tdmout_b_sclk_post_en.hw, 534 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &aud_tdmout_b_sclk_post_en.hw,
492 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &axg_tdmout_c_sclk_post_en.hw, 535 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &aud_tdmout_c_sclk_post_en.hw,
493 [AUD_CLKID_TDMIN_A_SCLK] = &axg_tdmin_a_sclk.hw, 536 [AUD_CLKID_TDMIN_A_SCLK] = &aud_tdmin_a_sclk.hw,
494 [AUD_CLKID_TDMIN_B_SCLK] = &axg_tdmin_b_sclk.hw, 537 [AUD_CLKID_TDMIN_B_SCLK] = &aud_tdmin_b_sclk.hw,
495 [AUD_CLKID_TDMIN_C_SCLK] = &axg_tdmin_c_sclk.hw, 538 [AUD_CLKID_TDMIN_C_SCLK] = &aud_tdmin_c_sclk.hw,
496 [AUD_CLKID_TDMIN_LB_SCLK] = &axg_tdmin_lb_sclk.hw, 539 [AUD_CLKID_TDMIN_LB_SCLK] = &aud_tdmin_lb_sclk.hw,
497 [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw, 540 [AUD_CLKID_TDMOUT_A_SCLK] = &aud_tdmout_a_sclk.hw,
498 [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw, 541 [AUD_CLKID_TDMOUT_B_SCLK] = &aud_tdmout_b_sclk.hw,
499 [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw, 542 [AUD_CLKID_TDMOUT_C_SCLK] = &aud_tdmout_c_sclk.hw,
500 [AUD_CLKID_TDMIN_A_LRCLK] = &axg_tdmin_a_lrclk.hw, 543 [AUD_CLKID_TDMIN_A_LRCLK] = &aud_tdmin_a_lrclk.hw,
501 [AUD_CLKID_TDMIN_B_LRCLK] = &axg_tdmin_b_lrclk.hw, 544 [AUD_CLKID_TDMIN_B_LRCLK] = &aud_tdmin_b_lrclk.hw,
502 [AUD_CLKID_TDMIN_C_LRCLK] = &axg_tdmin_c_lrclk.hw, 545 [AUD_CLKID_TDMIN_C_LRCLK] = &aud_tdmin_c_lrclk.hw,
503 [AUD_CLKID_TDMIN_LB_LRCLK] = &axg_tdmin_lb_lrclk.hw, 546 [AUD_CLKID_TDMIN_LB_LRCLK] = &aud_tdmin_lb_lrclk.hw,
504 [AUD_CLKID_TDMOUT_A_LRCLK] = &axg_tdmout_a_lrclk.hw, 547 [AUD_CLKID_TDMOUT_A_LRCLK] = &aud_tdmout_a_lrclk.hw,
505 [AUD_CLKID_TDMOUT_B_LRCLK] = &axg_tdmout_b_lrclk.hw, 548 [AUD_CLKID_TDMOUT_B_LRCLK] = &aud_tdmout_b_lrclk.hw,
506 [AUD_CLKID_TDMOUT_C_LRCLK] = &axg_tdmout_c_lrclk.hw, 549 [AUD_CLKID_TDMOUT_C_LRCLK] = &aud_tdmout_c_lrclk.hw,
507 [NR_CLKS] = NULL, 550 [NR_CLKS] = NULL,
508 }, 551 },
509 .num = NR_CLKS, 552 .num = NR_CLKS,
510}; 553};
511 554
512/* Convenience table to populate regmap in .probe() */ 555/*
513static struct clk_regmap *const axg_audio_clk_regmaps[] = { 556 * Array of all G12A clocks provided by this provider
514 &axg_ddr_arb, 557 * The input clocks of the controller will be populated at runtime
515 &axg_pdm, 558 */
516 &axg_tdmin_a, 559static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
517 &axg_tdmin_b, 560 .hws = {
518 &axg_tdmin_c, 561 [AUD_CLKID_DDR_ARB] = &aud_ddr_arb.hw,
519 &axg_tdmin_lb, 562 [AUD_CLKID_PDM] = &aud_pdm.hw,
520 &axg_tdmout_a, 563 [AUD_CLKID_TDMIN_A] = &aud_tdmin_a.hw,
521 &axg_tdmout_b, 564 [AUD_CLKID_TDMIN_B] = &aud_tdmin_b.hw,
522 &axg_tdmout_c, 565 [AUD_CLKID_TDMIN_C] = &aud_tdmin_c.hw,
523 &axg_frddr_a, 566 [AUD_CLKID_TDMIN_LB] = &aud_tdmin_lb.hw,
524 &axg_frddr_b, 567 [AUD_CLKID_TDMOUT_A] = &aud_tdmout_a.hw,
525 &axg_frddr_c, 568 [AUD_CLKID_TDMOUT_B] = &aud_tdmout_b.hw,
526 &axg_toddr_a, 569 [AUD_CLKID_TDMOUT_C] = &aud_tdmout_c.hw,
527 &axg_toddr_b, 570 [AUD_CLKID_FRDDR_A] = &aud_frddr_a.hw,
528 &axg_toddr_c, 571 [AUD_CLKID_FRDDR_B] = &aud_frddr_b.hw,
529 &axg_loopback, 572 [AUD_CLKID_FRDDR_C] = &aud_frddr_c.hw,
530 &axg_spdifin, 573 [AUD_CLKID_TODDR_A] = &aud_toddr_a.hw,
531 &axg_spdifout, 574 [AUD_CLKID_TODDR_B] = &aud_toddr_b.hw,
532 &axg_resample, 575 [AUD_CLKID_TODDR_C] = &aud_toddr_c.hw,
533 &axg_power_detect, 576 [AUD_CLKID_LOOPBACK] = &aud_loopback.hw,
534 &axg_mst_a_mclk_sel, 577 [AUD_CLKID_SPDIFIN] = &aud_spdifin.hw,
535 &axg_mst_b_mclk_sel, 578 [AUD_CLKID_SPDIFOUT] = &aud_spdifout.hw,
536 &axg_mst_c_mclk_sel, 579 [AUD_CLKID_RESAMPLE] = &aud_resample.hw,
537 &axg_mst_d_mclk_sel, 580 [AUD_CLKID_POWER_DETECT] = &aud_power_detect.hw,
538 &axg_mst_e_mclk_sel, 581 [AUD_CLKID_SPDIFOUT_B] = &aud_spdifout_b.hw,
539 &axg_mst_f_mclk_sel, 582 [AUD_CLKID_MST_A_MCLK_SEL] = &aud_mst_a_mclk_sel.hw,
540 &axg_mst_a_mclk_div, 583 [AUD_CLKID_MST_B_MCLK_SEL] = &aud_mst_b_mclk_sel.hw,
541 &axg_mst_b_mclk_div, 584 [AUD_CLKID_MST_C_MCLK_SEL] = &aud_mst_c_mclk_sel.hw,
542 &axg_mst_c_mclk_div, 585 [AUD_CLKID_MST_D_MCLK_SEL] = &aud_mst_d_mclk_sel.hw,
543 &axg_mst_d_mclk_div, 586 [AUD_CLKID_MST_E_MCLK_SEL] = &aud_mst_e_mclk_sel.hw,
544 &axg_mst_e_mclk_div, 587 [AUD_CLKID_MST_F_MCLK_SEL] = &aud_mst_f_mclk_sel.hw,
545 &axg_mst_f_mclk_div, 588 [AUD_CLKID_MST_A_MCLK_DIV] = &aud_mst_a_mclk_div.hw,
546 &axg_mst_a_mclk, 589 [AUD_CLKID_MST_B_MCLK_DIV] = &aud_mst_b_mclk_div.hw,
547 &axg_mst_b_mclk, 590 [AUD_CLKID_MST_C_MCLK_DIV] = &aud_mst_c_mclk_div.hw,
548 &axg_mst_c_mclk, 591 [AUD_CLKID_MST_D_MCLK_DIV] = &aud_mst_d_mclk_div.hw,
549 &axg_mst_d_mclk, 592 [AUD_CLKID_MST_E_MCLK_DIV] = &aud_mst_e_mclk_div.hw,
550 &axg_mst_e_mclk, 593 [AUD_CLKID_MST_F_MCLK_DIV] = &aud_mst_f_mclk_div.hw,
551 &axg_mst_f_mclk, 594 [AUD_CLKID_MST_A_MCLK] = &aud_mst_a_mclk.hw,
552 &axg_spdifout_clk_sel, 595 [AUD_CLKID_MST_B_MCLK] = &aud_mst_b_mclk.hw,
553 &axg_spdifout_clk_div, 596 [AUD_CLKID_MST_C_MCLK] = &aud_mst_c_mclk.hw,
554 &axg_spdifout_clk, 597 [AUD_CLKID_MST_D_MCLK] = &aud_mst_d_mclk.hw,
555 &axg_spdifin_clk_sel, 598 [AUD_CLKID_MST_E_MCLK] = &aud_mst_e_mclk.hw,
556 &axg_spdifin_clk_div, 599 [AUD_CLKID_MST_F_MCLK] = &aud_mst_f_mclk.hw,
557 &axg_spdifin_clk, 600 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &aud_spdifout_clk_sel.hw,
558 &axg_pdm_dclk_sel, 601 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &aud_spdifout_clk_div.hw,
559 &axg_pdm_dclk_div, 602 [AUD_CLKID_SPDIFOUT_CLK] = &aud_spdifout_clk.hw,
560 &axg_pdm_dclk, 603 [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &aud_spdifout_b_clk_sel.hw,
561 &axg_pdm_sysclk_sel, 604 [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &aud_spdifout_b_clk_div.hw,
562 &axg_pdm_sysclk_div, 605 [AUD_CLKID_SPDIFOUT_B_CLK] = &aud_spdifout_b_clk.hw,
563 &axg_pdm_sysclk, 606 [AUD_CLKID_SPDIFIN_CLK_SEL] = &aud_spdifin_clk_sel.hw,
564 &axg_mst_a_sclk_pre_en, 607 [AUD_CLKID_SPDIFIN_CLK_DIV] = &aud_spdifin_clk_div.hw,
565 &axg_mst_b_sclk_pre_en, 608 [AUD_CLKID_SPDIFIN_CLK] = &aud_spdifin_clk.hw,
566 &axg_mst_c_sclk_pre_en, 609 [AUD_CLKID_PDM_DCLK_SEL] = &aud_pdm_dclk_sel.hw,
567 &axg_mst_d_sclk_pre_en, 610 [AUD_CLKID_PDM_DCLK_DIV] = &aud_pdm_dclk_div.hw,
568 &axg_mst_e_sclk_pre_en, 611 [AUD_CLKID_PDM_DCLK] = &aud_pdm_dclk.hw,
569 &axg_mst_f_sclk_pre_en, 612 [AUD_CLKID_PDM_SYSCLK_SEL] = &aud_pdm_sysclk_sel.hw,
570 &axg_mst_a_sclk_div, 613 [AUD_CLKID_PDM_SYSCLK_DIV] = &aud_pdm_sysclk_div.hw,
571 &axg_mst_b_sclk_div, 614 [AUD_CLKID_PDM_SYSCLK] = &aud_pdm_sysclk.hw,
572 &axg_mst_c_sclk_div, 615 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &aud_mst_a_sclk_pre_en.hw,
573 &axg_mst_d_sclk_div, 616 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &aud_mst_b_sclk_pre_en.hw,
574 &axg_mst_e_sclk_div, 617 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &aud_mst_c_sclk_pre_en.hw,
575 &axg_mst_f_sclk_div, 618 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &aud_mst_d_sclk_pre_en.hw,
576 &axg_mst_a_sclk_post_en, 619 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &aud_mst_e_sclk_pre_en.hw,
577 &axg_mst_b_sclk_post_en, 620 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &aud_mst_f_sclk_pre_en.hw,
578 &axg_mst_c_sclk_post_en, 621 [AUD_CLKID_MST_A_SCLK_DIV] = &aud_mst_a_sclk_div.hw,
579 &axg_mst_d_sclk_post_en, 622 [AUD_CLKID_MST_B_SCLK_DIV] = &aud_mst_b_sclk_div.hw,
580 &axg_mst_e_sclk_post_en, 623 [AUD_CLKID_MST_C_SCLK_DIV] = &aud_mst_c_sclk_div.hw,
581 &axg_mst_f_sclk_post_en, 624 [AUD_CLKID_MST_D_SCLK_DIV] = &aud_mst_d_sclk_div.hw,
582 &axg_mst_a_sclk, 625 [AUD_CLKID_MST_E_SCLK_DIV] = &aud_mst_e_sclk_div.hw,
583 &axg_mst_b_sclk, 626 [AUD_CLKID_MST_F_SCLK_DIV] = &aud_mst_f_sclk_div.hw,
584 &axg_mst_c_sclk, 627 [AUD_CLKID_MST_A_SCLK_POST_EN] = &aud_mst_a_sclk_post_en.hw,
585 &axg_mst_d_sclk, 628 [AUD_CLKID_MST_B_SCLK_POST_EN] = &aud_mst_b_sclk_post_en.hw,
586 &axg_mst_e_sclk, 629 [AUD_CLKID_MST_C_SCLK_POST_EN] = &aud_mst_c_sclk_post_en.hw,
587 &axg_mst_f_sclk, 630 [AUD_CLKID_MST_D_SCLK_POST_EN] = &aud_mst_d_sclk_post_en.hw,
588 &axg_mst_a_lrclk_div, 631 [AUD_CLKID_MST_E_SCLK_POST_EN] = &aud_mst_e_sclk_post_en.hw,
589 &axg_mst_b_lrclk_div, 632 [AUD_CLKID_MST_F_SCLK_POST_EN] = &aud_mst_f_sclk_post_en.hw,
590 &axg_mst_c_lrclk_div, 633 [AUD_CLKID_MST_A_SCLK] = &aud_mst_a_sclk.hw,
591 &axg_mst_d_lrclk_div, 634 [AUD_CLKID_MST_B_SCLK] = &aud_mst_b_sclk.hw,
592 &axg_mst_e_lrclk_div, 635 [AUD_CLKID_MST_C_SCLK] = &aud_mst_c_sclk.hw,
593 &axg_mst_f_lrclk_div, 636 [AUD_CLKID_MST_D_SCLK] = &aud_mst_d_sclk.hw,
594 &axg_mst_a_lrclk, 637 [AUD_CLKID_MST_E_SCLK] = &aud_mst_e_sclk.hw,
595 &axg_mst_b_lrclk, 638 [AUD_CLKID_MST_F_SCLK] = &aud_mst_f_sclk.hw,
596 &axg_mst_c_lrclk, 639 [AUD_CLKID_MST_A_LRCLK_DIV] = &aud_mst_a_lrclk_div.hw,
597 &axg_mst_d_lrclk, 640 [AUD_CLKID_MST_B_LRCLK_DIV] = &aud_mst_b_lrclk_div.hw,
598 &axg_mst_e_lrclk, 641 [AUD_CLKID_MST_C_LRCLK_DIV] = &aud_mst_c_lrclk_div.hw,
599 &axg_mst_f_lrclk, 642 [AUD_CLKID_MST_D_LRCLK_DIV] = &aud_mst_d_lrclk_div.hw,
600 &axg_tdmin_a_sclk_sel, 643 [AUD_CLKID_MST_E_LRCLK_DIV] = &aud_mst_e_lrclk_div.hw,
601 &axg_tdmin_b_sclk_sel, 644 [AUD_CLKID_MST_F_LRCLK_DIV] = &aud_mst_f_lrclk_div.hw,
602 &axg_tdmin_c_sclk_sel, 645 [AUD_CLKID_MST_A_LRCLK] = &aud_mst_a_lrclk.hw,
603 &axg_tdmin_lb_sclk_sel, 646 [AUD_CLKID_MST_B_LRCLK] = &aud_mst_b_lrclk.hw,
604 &axg_tdmout_a_sclk_sel, 647 [AUD_CLKID_MST_C_LRCLK] = &aud_mst_c_lrclk.hw,
605 &axg_tdmout_b_sclk_sel, 648 [AUD_CLKID_MST_D_LRCLK] = &aud_mst_d_lrclk.hw,
606 &axg_tdmout_c_sclk_sel, 649 [AUD_CLKID_MST_E_LRCLK] = &aud_mst_e_lrclk.hw,
607 &axg_tdmin_a_sclk_pre_en, 650 [AUD_CLKID_MST_F_LRCLK] = &aud_mst_f_lrclk.hw,
608 &axg_tdmin_b_sclk_pre_en, 651 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &aud_tdmin_a_sclk_sel.hw,
609 &axg_tdmin_c_sclk_pre_en, 652 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &aud_tdmin_b_sclk_sel.hw,
610 &axg_tdmin_lb_sclk_pre_en, 653 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &aud_tdmin_c_sclk_sel.hw,
611 &axg_tdmout_a_sclk_pre_en, 654 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &aud_tdmin_lb_sclk_sel.hw,
612 &axg_tdmout_b_sclk_pre_en, 655 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &aud_tdmout_a_sclk_sel.hw,
613 &axg_tdmout_c_sclk_pre_en, 656 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &aud_tdmout_b_sclk_sel.hw,
614 &axg_tdmin_a_sclk_post_en, 657 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &aud_tdmout_c_sclk_sel.hw,
615 &axg_tdmin_b_sclk_post_en, 658 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &aud_tdmin_a_sclk_pre_en.hw,
616 &axg_tdmin_c_sclk_post_en, 659 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &aud_tdmin_b_sclk_pre_en.hw,
617 &axg_tdmin_lb_sclk_post_en, 660 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &aud_tdmin_c_sclk_pre_en.hw,
618 &axg_tdmout_a_sclk_post_en, 661 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &aud_tdmin_lb_sclk_pre_en.hw,
619 &axg_tdmout_b_sclk_post_en, 662 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &aud_tdmout_a_sclk_pre_en.hw,
620 &axg_tdmout_c_sclk_post_en, 663 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &aud_tdmout_b_sclk_pre_en.hw,
621 &axg_tdmin_a_sclk, 664 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &aud_tdmout_c_sclk_pre_en.hw,
622 &axg_tdmin_b_sclk, 665 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &aud_tdmin_a_sclk_post_en.hw,
623 &axg_tdmin_c_sclk, 666 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &aud_tdmin_b_sclk_post_en.hw,
624 &axg_tdmin_lb_sclk, 667 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &aud_tdmin_c_sclk_post_en.hw,
625 &axg_tdmout_a_sclk, 668 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &aud_tdmin_lb_sclk_post_en.hw,
626 &axg_tdmout_b_sclk, 669 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &aud_tdmout_a_sclk_post_en.hw,
627 &axg_tdmout_c_sclk, 670 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &aud_tdmout_b_sclk_post_en.hw,
628 &axg_tdmin_a_lrclk, 671 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &aud_tdmout_c_sclk_post_en.hw,
629 &axg_tdmin_b_lrclk, 672 [AUD_CLKID_TDMIN_A_SCLK] = &aud_tdmin_a_sclk.hw,
630 &axg_tdmin_c_lrclk, 673 [AUD_CLKID_TDMIN_B_SCLK] = &aud_tdmin_b_sclk.hw,
631 &axg_tdmin_lb_lrclk, 674 [AUD_CLKID_TDMIN_C_SCLK] = &aud_tdmin_c_sclk.hw,
632 &axg_tdmout_a_lrclk, 675 [AUD_CLKID_TDMIN_LB_SCLK] = &aud_tdmin_lb_sclk.hw,
633 &axg_tdmout_b_lrclk, 676 [AUD_CLKID_TDMOUT_A_SCLK] = &aud_tdmout_a_sclk.hw,
634 &axg_tdmout_c_lrclk, 677 [AUD_CLKID_TDMOUT_B_SCLK] = &aud_tdmout_b_sclk.hw,
678 [AUD_CLKID_TDMOUT_C_SCLK] = &aud_tdmout_c_sclk.hw,
679 [AUD_CLKID_TDMIN_A_LRCLK] = &aud_tdmin_a_lrclk.hw,
680 [AUD_CLKID_TDMIN_B_LRCLK] = &aud_tdmin_b_lrclk.hw,
681 [AUD_CLKID_TDMIN_C_LRCLK] = &aud_tdmin_c_lrclk.hw,
682 [AUD_CLKID_TDMIN_LB_LRCLK] = &aud_tdmin_lb_lrclk.hw,
683 [AUD_CLKID_TDMOUT_A_LRCLK] = &aud_tdmout_a_lrclk.hw,
684 [AUD_CLKID_TDMOUT_B_LRCLK] = &aud_tdmout_b_lrclk.hw,
685 [AUD_CLKID_TDMOUT_C_LRCLK] = &aud_tdmout_c_lrclk.hw,
686 [AUD_CLKID_TDM_MCLK_PAD0] = &aud_tdm_mclk_pad_0.hw,
687 [AUD_CLKID_TDM_MCLK_PAD1] = &aud_tdm_mclk_pad_1.hw,
688 [AUD_CLKID_TDM_LRCLK_PAD0] = &aud_tdm_lrclk_pad_0.hw,
689 [AUD_CLKID_TDM_LRCLK_PAD1] = &aud_tdm_lrclk_pad_1.hw,
690 [AUD_CLKID_TDM_LRCLK_PAD2] = &aud_tdm_lrclk_pad_2.hw,
691 [AUD_CLKID_TDM_SCLK_PAD0] = &aud_tdm_sclk_pad_0.hw,
692 [AUD_CLKID_TDM_SCLK_PAD1] = &aud_tdm_sclk_pad_1.hw,
693 [AUD_CLKID_TDM_SCLK_PAD2] = &aud_tdm_sclk_pad_2.hw,
694 [NR_CLKS] = NULL,
695 },
696 .num = NR_CLKS,
697};
698
699/* Convenience table to populate regmap in .probe()
700 * Note that this table is shared between both AXG and G12A,
701 * with spdifout_b clocks being exclusive to G12A. Since those
702 * clocks are not declared within the AXG onecell table, we do not
703 * feel the need to have separate AXG/G12A regmap tables.
704 */
705static struct clk_regmap *const aud_clk_regmaps[] = {
706 &aud_ddr_arb,
707 &aud_pdm,
708 &aud_tdmin_a,
709 &aud_tdmin_b,
710 &aud_tdmin_c,
711 &aud_tdmin_lb,
712 &aud_tdmout_a,
713 &aud_tdmout_b,
714 &aud_tdmout_c,
715 &aud_frddr_a,
716 &aud_frddr_b,
717 &aud_frddr_c,
718 &aud_toddr_a,
719 &aud_toddr_b,
720 &aud_toddr_c,
721 &aud_loopback,
722 &aud_spdifin,
723 &aud_spdifout,
724 &aud_resample,
725 &aud_power_detect,
726 &aud_spdifout_b,
727 &aud_mst_a_mclk_sel,
728 &aud_mst_b_mclk_sel,
729 &aud_mst_c_mclk_sel,
730 &aud_mst_d_mclk_sel,
731 &aud_mst_e_mclk_sel,
732 &aud_mst_f_mclk_sel,
733 &aud_mst_a_mclk_div,
734 &aud_mst_b_mclk_div,
735 &aud_mst_c_mclk_div,
736 &aud_mst_d_mclk_div,
737 &aud_mst_e_mclk_div,
738 &aud_mst_f_mclk_div,
739 &aud_mst_a_mclk,
740 &aud_mst_b_mclk,
741 &aud_mst_c_mclk,
742 &aud_mst_d_mclk,
743 &aud_mst_e_mclk,
744 &aud_mst_f_mclk,
745 &aud_spdifout_clk_sel,
746 &aud_spdifout_clk_div,
747 &aud_spdifout_clk,
748 &aud_spdifin_clk_sel,
749 &aud_spdifin_clk_div,
750 &aud_spdifin_clk,
751 &aud_pdm_dclk_sel,
752 &aud_pdm_dclk_div,
753 &aud_pdm_dclk,
754 &aud_pdm_sysclk_sel,
755 &aud_pdm_sysclk_div,
756 &aud_pdm_sysclk,
757 &aud_mst_a_sclk_pre_en,
758 &aud_mst_b_sclk_pre_en,
759 &aud_mst_c_sclk_pre_en,
760 &aud_mst_d_sclk_pre_en,
761 &aud_mst_e_sclk_pre_en,
762 &aud_mst_f_sclk_pre_en,
763 &aud_mst_a_sclk_div,
764 &aud_mst_b_sclk_div,
765 &aud_mst_c_sclk_div,
766 &aud_mst_d_sclk_div,
767 &aud_mst_e_sclk_div,
768 &aud_mst_f_sclk_div,
769 &aud_mst_a_sclk_post_en,
770 &aud_mst_b_sclk_post_en,
771 &aud_mst_c_sclk_post_en,
772 &aud_mst_d_sclk_post_en,
773 &aud_mst_e_sclk_post_en,
774 &aud_mst_f_sclk_post_en,
775 &aud_mst_a_sclk,
776 &aud_mst_b_sclk,
777 &aud_mst_c_sclk,
778 &aud_mst_d_sclk,
779 &aud_mst_e_sclk,
780 &aud_mst_f_sclk,
781 &aud_mst_a_lrclk_div,
782 &aud_mst_b_lrclk_div,
783 &aud_mst_c_lrclk_div,
784 &aud_mst_d_lrclk_div,
785 &aud_mst_e_lrclk_div,
786 &aud_mst_f_lrclk_div,
787 &aud_mst_a_lrclk,
788 &aud_mst_b_lrclk,
789 &aud_mst_c_lrclk,
790 &aud_mst_d_lrclk,
791 &aud_mst_e_lrclk,
792 &aud_mst_f_lrclk,
793 &aud_tdmin_a_sclk_sel,
794 &aud_tdmin_b_sclk_sel,
795 &aud_tdmin_c_sclk_sel,
796 &aud_tdmin_lb_sclk_sel,
797 &aud_tdmout_a_sclk_sel,
798 &aud_tdmout_b_sclk_sel,
799 &aud_tdmout_c_sclk_sel,
800 &aud_tdmin_a_sclk_pre_en,
801 &aud_tdmin_b_sclk_pre_en,
802 &aud_tdmin_c_sclk_pre_en,
803 &aud_tdmin_lb_sclk_pre_en,
804 &aud_tdmout_a_sclk_pre_en,
805 &aud_tdmout_b_sclk_pre_en,
806 &aud_tdmout_c_sclk_pre_en,
807 &aud_tdmin_a_sclk_post_en,
808 &aud_tdmin_b_sclk_post_en,
809 &aud_tdmin_c_sclk_post_en,
810 &aud_tdmin_lb_sclk_post_en,
811 &aud_tdmout_a_sclk_post_en,
812 &aud_tdmout_b_sclk_post_en,
813 &aud_tdmout_c_sclk_post_en,
814 &aud_tdmin_a_sclk,
815 &aud_tdmin_b_sclk,
816 &aud_tdmin_c_sclk,
817 &aud_tdmin_lb_sclk,
818 &aud_tdmout_a_sclk,
819 &aud_tdmout_b_sclk,
820 &aud_tdmout_c_sclk,
821 &aud_tdmin_a_lrclk,
822 &aud_tdmin_b_lrclk,
823 &aud_tdmin_c_lrclk,
824 &aud_tdmin_lb_lrclk,
825 &aud_tdmout_a_lrclk,
826 &aud_tdmout_b_lrclk,
827 &aud_tdmout_c_lrclk,
828 &aud_spdifout_b_clk_sel,
829 &aud_spdifout_b_clk_div,
830 &aud_spdifout_b_clk,
831 &aud_tdm_mclk_pad_0,
832 &aud_tdm_mclk_pad_1,
833 &aud_tdm_lrclk_pad_0,
834 &aud_tdm_lrclk_pad_1,
835 &aud_tdm_lrclk_pad_2,
836 &aud_tdm_sclk_pad_0,
837 &aud_tdm_sclk_pad_1,
838 &aud_tdm_sclk_pad_2,
635}; 839};
636 840
637static int devm_clk_get_enable(struct device *dev, char *id) 841static int devm_clk_get_enable(struct device *dev, char *id)
@@ -665,14 +869,13 @@ static int devm_clk_get_enable(struct device *dev, char *id)
665} 869}
666 870
667static int axg_register_clk_hw_input(struct device *dev, 871static int axg_register_clk_hw_input(struct device *dev,
668 const char *name, 872 const char *name)
669 unsigned int clkid)
670{ 873{
671 char *clk_name; 874 char *clk_name;
672 struct clk_hw *hw; 875 struct clk_hw *hw;
673 int err = 0; 876 int err = 0;
674 877
675 clk_name = kasprintf(GFP_KERNEL, "axg_%s", name); 878 clk_name = kasprintf(GFP_KERNEL, "aud_%s", name);
676 if (!clk_name) 879 if (!clk_name)
677 return -ENOMEM; 880 return -ENOMEM;
678 881
@@ -686,8 +889,6 @@ static int axg_register_clk_hw_input(struct device *dev,
686 if (err != -EPROBE_DEFER) 889 if (err != -EPROBE_DEFER)
687 dev_err(dev, "failed to get %s clock", name); 890 dev_err(dev, "failed to get %s clock", name);
688 } 891 }
689 } else {
690 axg_audio_hw_onecell_data.hws[clkid] = hw;
691 } 892 }
692 893
693 kfree(clk_name); 894 kfree(clk_name);
@@ -696,8 +897,7 @@ static int axg_register_clk_hw_input(struct device *dev,
696 897
697static int axg_register_clk_hw_inputs(struct device *dev, 898static int axg_register_clk_hw_inputs(struct device *dev,
698 const char *basename, 899 const char *basename,
699 unsigned int count, 900 unsigned int count)
700 unsigned int clkid)
701{ 901{
702 char *name; 902 char *name;
703 int i, ret; 903 int i, ret;
@@ -707,7 +907,7 @@ static int axg_register_clk_hw_inputs(struct device *dev,
707 if (!name) 907 if (!name)
708 return -ENOMEM; 908 return -ENOMEM;
709 909
710 ret = axg_register_clk_hw_input(dev, name, clkid + i); 910 ret = axg_register_clk_hw_input(dev, name);
711 kfree(name); 911 kfree(name);
712 if (ret) 912 if (ret)
713 return ret; 913 return ret;
@@ -723,15 +923,24 @@ static const struct regmap_config axg_audio_regmap_cfg = {
723 .max_register = AUDIO_CLK_PDMIN_CTRL1, 923 .max_register = AUDIO_CLK_PDMIN_CTRL1,
724}; 924};
725 925
926struct audioclk_data {
927 struct clk_hw_onecell_data *hw_onecell_data;
928};
929
726static int axg_audio_clkc_probe(struct platform_device *pdev) 930static int axg_audio_clkc_probe(struct platform_device *pdev)
727{ 931{
728 struct device *dev = &pdev->dev; 932 struct device *dev = &pdev->dev;
933 const struct audioclk_data *data;
729 struct regmap *map; 934 struct regmap *map;
730 struct resource *res; 935 struct resource *res;
731 void __iomem *regs; 936 void __iomem *regs;
732 struct clk_hw *hw; 937 struct clk_hw *hw;
733 int ret, i; 938 int ret, i;
734 939
940 data = of_device_get_match_data(dev);
941 if (!data)
942 return -EINVAL;
943
735 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 944 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
736 regs = devm_ioremap_resource(dev, res); 945 regs = devm_ioremap_resource(dev, res);
737 if (IS_ERR(regs)) 946 if (IS_ERR(regs))
@@ -755,40 +964,35 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
755 } 964 }
756 965
757 /* Register the peripheral input clock */ 966 /* Register the peripheral input clock */
758 hw = meson_clk_hw_register_input(dev, "pclk", "axg_audio_pclk", 0); 967 hw = meson_clk_hw_register_input(dev, "pclk", "audio_pclk", 0);
759 if (IS_ERR(hw)) 968 if (IS_ERR(hw))
760 return PTR_ERR(hw); 969 return PTR_ERR(hw);
761 970
762 axg_audio_hw_onecell_data.hws[AUD_CLKID_PCLK] = hw;
763
764 /* Register optional input master clocks */ 971 /* Register optional input master clocks */
765 ret = axg_register_clk_hw_inputs(dev, "mst_in", 972 ret = axg_register_clk_hw_inputs(dev, "mst_in",
766 AXG_MST_IN_COUNT, 973 AUD_MST_IN_COUNT);
767 AUD_CLKID_MST0);
768 if (ret) 974 if (ret)
769 return ret; 975 return ret;
770 976
771 /* Register optional input slave sclks */ 977 /* Register optional input slave sclks */
772 ret = axg_register_clk_hw_inputs(dev, "slv_sclk", 978 ret = axg_register_clk_hw_inputs(dev, "slv_sclk",
773 AXG_SLV_SCLK_COUNT, 979 AUD_SLV_SCLK_COUNT);
774 AUD_CLKID_SLV_SCLK0);
775 if (ret) 980 if (ret)
776 return ret; 981 return ret;
777 982
778 /* Register optional input slave lrclks */ 983 /* Register optional input slave lrclks */
779 ret = axg_register_clk_hw_inputs(dev, "slv_lrclk", 984 ret = axg_register_clk_hw_inputs(dev, "slv_lrclk",
780 AXG_SLV_LRCLK_COUNT, 985 AUD_SLV_LRCLK_COUNT);
781 AUD_CLKID_SLV_LRCLK0);
782 if (ret) 986 if (ret)
783 return ret; 987 return ret;
784 988
785 /* Populate regmap for the regmap backed clocks */ 989 /* Populate regmap for the regmap backed clocks */
786 for (i = 0; i < ARRAY_SIZE(axg_audio_clk_regmaps); i++) 990 for (i = 0; i < ARRAY_SIZE(aud_clk_regmaps); i++)
787 axg_audio_clk_regmaps[i]->map = map; 991 aud_clk_regmaps[i]->map = map;
788 992
789 /* Take care to skip the registered input clocks */ 993 /* Take care to skip the registered input clocks */
790 for (i = AUD_CLKID_DDR_ARB; i < axg_audio_hw_onecell_data.num; i++) { 994 for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
791 hw = axg_audio_hw_onecell_data.hws[i]; 995 hw = data->hw_onecell_data->hws[i];
792 /* array might be sparse */ 996 /* array might be sparse */
793 if (!hw) 997 if (!hw)
794 continue; 998 continue;
@@ -802,12 +1006,25 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
802 } 1006 }
803 1007
804 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 1008 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
805 &axg_audio_hw_onecell_data); 1009 data->hw_onecell_data);
806} 1010}
807 1011
1012static const struct audioclk_data axg_audioclk_data = {
1013 .hw_onecell_data = &axg_audio_hw_onecell_data,
1014};
1015
1016static const struct audioclk_data g12a_audioclk_data = {
1017 .hw_onecell_data = &g12a_audio_hw_onecell_data,
1018};
1019
808static const struct of_device_id clkc_match_table[] = { 1020static const struct of_device_id clkc_match_table[] = {
809 { .compatible = "amlogic,axg-audio-clkc" }, 1021 {
810 {} 1022 .compatible = "amlogic,axg-audio-clkc",
1023 .data = &axg_audioclk_data
1024 }, {
1025 .compatible = "amlogic,g12a-audio-clkc",
1026 .data = &g12a_audioclk_data
1027 }, {}
811}; 1028};
812MODULE_DEVICE_TABLE(of, clkc_match_table); 1029MODULE_DEVICE_TABLE(of, clkc_match_table);
813 1030
@@ -820,6 +1037,6 @@ static struct platform_driver axg_audio_driver = {
820}; 1037};
821module_platform_driver(axg_audio_driver); 1038module_platform_driver(axg_audio_driver);
822 1039
823MODULE_DESCRIPTION("Amlogic A113x Audio Clock driver"); 1040MODULE_DESCRIPTION("Amlogic AXG/G12A Audio Clock driver");
824MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>"); 1041MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
825MODULE_LICENSE("GPL v2"); 1042MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
index 644f0b0fddf2..5d972d55d6c7 100644
--- a/drivers/clk/meson/axg-audio.h
+++ b/drivers/clk/meson/axg-audio.h
@@ -20,6 +20,8 @@
20#define AUDIO_MCLK_D_CTRL 0x010 20#define AUDIO_MCLK_D_CTRL 0x010
21#define AUDIO_MCLK_E_CTRL 0x014 21#define AUDIO_MCLK_E_CTRL 0x014
22#define AUDIO_MCLK_F_CTRL 0x018 22#define AUDIO_MCLK_F_CTRL 0x018
23#define AUDIO_MST_PAD_CTRL0 0x01c
24#define AUDIO_MST_PAD_CTRL1 0x020
23#define AUDIO_MST_A_SCLK_CTRL0 0x040 25#define AUDIO_MST_A_SCLK_CTRL0 0x040
24#define AUDIO_MST_A_SCLK_CTRL1 0x044 26#define AUDIO_MST_A_SCLK_CTRL1 0x044
25#define AUDIO_MST_B_SCLK_CTRL0 0x048 27#define AUDIO_MST_B_SCLK_CTRL0 0x048
@@ -45,41 +47,13 @@
45#define AUDIO_CLK_LOCKER_CTRL 0x0A8 47#define AUDIO_CLK_LOCKER_CTRL 0x0A8
46#define AUDIO_CLK_PDMIN_CTRL0 0x0AC 48#define AUDIO_CLK_PDMIN_CTRL0 0x0AC
47#define AUDIO_CLK_PDMIN_CTRL1 0x0B0 49#define AUDIO_CLK_PDMIN_CTRL1 0x0B0
50#define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4
48 51
49/* 52/*
50 * CLKID index values 53 * CLKID index values
51 * These indices are entirely contrived and do not map onto the hardware. 54 * These indices are entirely contrived and do not map onto the hardware.
52 */ 55 */
53 56
54#define AUD_CLKID_PCLK 0
55#define AUD_CLKID_MST0 1
56#define AUD_CLKID_MST1 2
57#define AUD_CLKID_MST2 3
58#define AUD_CLKID_MST3 4
59#define AUD_CLKID_MST4 5
60#define AUD_CLKID_MST5 6
61#define AUD_CLKID_MST6 7
62#define AUD_CLKID_MST7 8
63#define AUD_CLKID_SLV_SCLK0 9
64#define AUD_CLKID_SLV_SCLK1 10
65#define AUD_CLKID_SLV_SCLK2 11
66#define AUD_CLKID_SLV_SCLK3 12
67#define AUD_CLKID_SLV_SCLK4 13
68#define AUD_CLKID_SLV_SCLK5 14
69#define AUD_CLKID_SLV_SCLK6 15
70#define AUD_CLKID_SLV_SCLK7 16
71#define AUD_CLKID_SLV_SCLK8 17
72#define AUD_CLKID_SLV_SCLK9 18
73#define AUD_CLKID_SLV_LRCLK0 19
74#define AUD_CLKID_SLV_LRCLK1 20
75#define AUD_CLKID_SLV_LRCLK2 21
76#define AUD_CLKID_SLV_LRCLK3 22
77#define AUD_CLKID_SLV_LRCLK4 23
78#define AUD_CLKID_SLV_LRCLK5 24
79#define AUD_CLKID_SLV_LRCLK6 25
80#define AUD_CLKID_SLV_LRCLK7 26
81#define AUD_CLKID_SLV_LRCLK8 27
82#define AUD_CLKID_SLV_LRCLK9 28
83#define AUD_CLKID_MST_A_MCLK_SEL 59 57#define AUD_CLKID_MST_A_MCLK_SEL 59
84#define AUD_CLKID_MST_B_MCLK_SEL 60 58#define AUD_CLKID_MST_B_MCLK_SEL 60
85#define AUD_CLKID_MST_C_MCLK_SEL 61 59#define AUD_CLKID_MST_C_MCLK_SEL 61
@@ -138,10 +112,12 @@
138#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148 112#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148
139#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149 113#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149
140#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150 114#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150
115#define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153
116#define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154
141 117
142/* include the CLKIDs which are part of the DT bindings */ 118/* include the CLKIDs which are part of the DT bindings */
143#include <dt-bindings/clock/axg-audio-clkc.h> 119#include <dt-bindings/clock/axg-audio-clkc.h>
144 120
145#define NR_CLKS 151 121#define NR_CLKS 163
146 122
147#endif /*__AXG_AUDIO_CLKC_H */ 123#endif /*__AXG_AUDIO_CLKC_H */
diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
index eafb0de8466b..75901c636893 100644
--- a/include/dt-bindings/clock/axg-audio-clkc.h
+++ b/include/dt-bindings/clock/axg-audio-clkc.h
@@ -70,5 +70,15 @@
70#define AUD_CLKID_TDMOUT_A_LRCLK 134 70#define AUD_CLKID_TDMOUT_A_LRCLK 134
71#define AUD_CLKID_TDMOUT_B_LRCLK 135 71#define AUD_CLKID_TDMOUT_B_LRCLK 135
72#define AUD_CLKID_TDMOUT_C_LRCLK 136 72#define AUD_CLKID_TDMOUT_C_LRCLK 136
73#define AUD_CLKID_SPDIFOUT_B 151
74#define AUD_CLKID_SPDIFOUT_B_CLK 152
75#define AUD_CLKID_TDM_MCLK_PAD0 155
76#define AUD_CLKID_TDM_MCLK_PAD1 156
77#define AUD_CLKID_TDM_LRCLK_PAD0 157
78#define AUD_CLKID_TDM_LRCLK_PAD1 158
79#define AUD_CLKID_TDM_LRCLK_PAD2 159
80#define AUD_CLKID_TDM_SCLK_PAD0 160
81#define AUD_CLKID_TDM_SCLK_PAD1 161
82#define AUD_CLKID_TDM_SCLK_PAD2 162
73 83
74#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ 84#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-04 17:45:50 -0400