diff options
-rw-r--r-- | drivers/ata/ahci_ceva.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c index ec9cfb52c6f6..113c1f617da9 100644 --- a/drivers/ata/ahci_ceva.c +++ b/drivers/ata/ahci_ceva.c | |||
@@ -134,14 +134,6 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv) | |||
134 | u32 tmp; | 134 | u32 tmp; |
135 | int i; | 135 | int i; |
136 | 136 | ||
137 | /* | ||
138 | * AXI Data bus width to 64 | ||
139 | * Set Mem Addr Read, Write ID for data transfers | ||
140 | * Transfer limit to 72 DWord | ||
141 | */ | ||
142 | tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL; | ||
143 | writel(tmp, mmio + AHCI_VEND_PAXIC); | ||
144 | |||
145 | /* Set AHCI Enable */ | 137 | /* Set AHCI Enable */ |
146 | tmp = readl(mmio + HOST_CTL); | 138 | tmp = readl(mmio + HOST_CTL); |
147 | tmp |= HOST_AHCI_EN; | 139 | tmp |= HOST_AHCI_EN; |
@@ -152,6 +144,14 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv) | |||
152 | tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i); | 144 | tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i); |
153 | writel(tmp, mmio + AHCI_VEND_PCFG); | 145 | writel(tmp, mmio + AHCI_VEND_PCFG); |
154 | 146 | ||
147 | /* | ||
148 | * AXI Data bus width to 64 | ||
149 | * Set Mem Addr Read, Write ID for data transfers | ||
150 | * Transfer limit to 72 DWord | ||
151 | */ | ||
152 | tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL; | ||
153 | writel(tmp, mmio + AHCI_VEND_PAXIC); | ||
154 | |||
155 | /* Set AXI cache control register if CCi is enabled */ | 155 | /* Set AXI cache control register if CCi is enabled */ |
156 | if (cevapriv->is_cci_enabled) { | 156 | if (cevapriv->is_cci_enabled) { |
157 | tmp = readl(mmio + AHCI_VEND_AXICC); | 157 | tmp = readl(mmio + AHCI_VEND_AXICC); |