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-rw-r--r--arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts143
-rw-r--r--arch/arm64/boot/dts/bitmain/bm1880.dtsi68
2 files changed, 211 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
index 6a3255597138..3e8c70778e24 100644
--- a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
+++ b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
@@ -8,6 +8,28 @@
8 8
9#include "bm1880.dtsi" 9#include "bm1880.dtsi"
10 10
11/*
12 * GPIO name legend: proper name = the GPIO line is used as GPIO
13 * NC = not connected (pin out but not routed from the chip to
14 * anything the board)
15 * "[PER]" = pin is muxed for [peripheral] (not GPIO)
16 * LSEC = Low Speed External Connector
17 * HSEC = High Speed External Connector
18 *
19 * Line names are taken from the schematic "sophon-edge-schematics"
20 * version, 1.0210.
21 *
22 * For the lines routed to the external connectors the
23 * lines are named after the 96Boards CE Specification 1.0,
24 * Appendix "Expansion Connector Signal Description".
25 *
26 * When the 96Board naming of a line and the schematic name of
27 * the same line are in conflict, the 96Board specification
28 * takes precedence. This is only for the informational
29 * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L"
30 * are the only ones actually used for GPIO.
31 */
32
11/ { 33/ {
12 compatible = "bitmain,sophon-edge", "bitmain,bm1880"; 34 compatible = "bitmain,sophon-edge", "bitmain,bm1880";
13 model = "Sophon Edge"; 35 model = "Sophon Edge";
@@ -32,19 +54,140 @@
32 clock-frequency = <500000000>; 54 clock-frequency = <500000000>;
33 #clock-cells = <0>; 55 #clock-cells = <0>;
34 }; 56 };
57
58 soc {
59 gpio0: gpio@50027000 {
60 porta: gpio-controller@0 {
61 gpio-line-names =
62 "GPIO-A", /* GPIO0, LSEC pin 23 */
63 "GPIO-C", /* GPIO1, LSEC pin 25 */
64 "[GPIO2_PHY0_RST]", /* GPIO2 */
65 "GPIO-E", /* GPIO3, LSEC pin 27 */
66 "[USB_DET]", /* GPIO4 */
67 "[EN_P5V]", /* GPIO5 */
68 "[VDDIO_MS1_SEL]", /* GPIO6 */
69 "GPIO-G", /* GPIO7, LSEC pin 29 */
70 "[BM_TUSB_RST_L]", /* GPIO8 */
71 "[EN_P5V_USBHUB]", /* GPIO9 */
72 "NC",
73 "LED_WIFI", /* GPIO11 */
74 "LED_BT", /* GPIO12 */
75 "[BM_BLM8221_EN_L]", /* GPIO13 */
76 "NC", /* GPIO14 */
77 "NC", /* GPIO15 */
78 "NC", /* GPIO16 */
79 "NC", /* GPIO17 */
80 "NC", /* GPIO18 */
81 "NC", /* GPIO19 */
82 "NC", /* GPIO20 */
83 "NC", /* GPIO21 */
84 "NC", /* GPIO22 */
85 "NC", /* GPIO23 */
86 "NC", /* GPIO24 */
87 "NC", /* GPIO25 */
88 "NC", /* GPIO26 */
89 "NC", /* GPIO27 */
90 "NC", /* GPIO28 */
91 "NC", /* GPIO29 */
92 "NC", /* GPIO30 */
93 "NC"; /* GPIO31 */
94 };
95 };
96
97 gpio1: gpio@50027400 {
98 portb: gpio-controller@0 {
99 gpio-line-names =
100 "NC", /* GPIO32 */
101 "NC", /* GPIO33 */
102 "[I2C0_SDA]", /* GPIO34, LSEC pin 17 */
103 "[I2C0_SCL]", /* GPIO35, LSEC pin 15 */
104 "[JTAG0_TDO]", /* GPIO36 */
105 "[JTAG0_TCK]", /* GPIO37 */
106 "[JTAG0_TDI]", /* GPIO38 */
107 "[JTAG0_TMS]", /* GPIO39 */
108 "[JTAG0_TRST_X]", /* GPIO40 */
109 "[JTAG1_TDO]", /* GPIO41 */
110 "[JTAG1_TCK]", /* GPIO42 */
111 "[JTAG1_TDI]", /* GPIO43 */
112 "[CPU_TX]", /* GPIO44 */
113 "[CPU_RX]", /* GPIO45 */
114 "[UART1_TXD]", /* GPIO46 */
115 "[UART1_RXD]", /* GPIO47 */
116 "[UART0_TXD]", /* GPIO48 */
117 "[UART0_RXD]", /* GPIO49 */
118 "GPIO-I", /* GPIO50, LSEC pin 31 */
119 "GPIO-K", /* GPIO51, LSEC pin 33 */
120 "USER_LED2", /* GPIO52 */
121 "USER_LED1", /* GPIO53 */
122 "[UART0_RTS]", /* GPIO54 */
123 "[UART0_CTS]", /* GPIO55 */
124 "USER_LED4", /* GPIO56, JTAG1_TRST_X */
125 "USER_LED3", /* GPIO57, JTAG1_TMS */
126 "[I2S0_SCLK]", /* GPIO58 */
127 "[I2S0_FS]", /* GPIO59 */
128 "[I2S0_SDI]", /* GPIO60 */
129 "[I2S0_SDO]", /* GPIO61 */
130 "GPIO-B", /* GPIO62, LSEC pin 24 */
131 "GPIO-F"; /* GPIO63, I2S1_SCLK, LSEC pin 28 */
132 };
133 };
134
135 gpio2: gpio@50027800 {
136 portc: gpio-controller@0 {
137 gpio-line-names =
138 "GPIO-D", /* GPIO64, I2S1_FS, LSEC pin 26 */
139 "GPIO-J", /* GPIO65, I2S1_SDI, LSEC pin 32 */
140 "GPIO-H", /* GPIO66, I2S1_SDO, LSEC pin 30 */
141 "GPIO-L", /* GPIO67, LSEC pin 34 */
142 "[SPI0_CS]", /* GPIO68, SPI1_CS, LSEC pin 12 */
143 "[SPI0_DIN]", /* GPIO69, SPI1_SDI, LSEC pin 10 */
144 "[SPI0_DOUT]", /* GPIO70, SPI1_SDO, LSEC pin 14 */
145 "[SPI0_SCLK]"; /* GPIO71, SPI1_SCK, LSEC pin 8 */
146 };
147 };
148 };
149};
150
151&pinctrl {
152 pinctrl_uart0_default: pinctrl-uart0-default {
153 pinmux {
154 groups = "uart0_grp";
155 function = "uart0";
156 };
157 };
158
159 pinctrl_uart1_default: pinctrl-uart1-default {
160 pinmux {
161 groups = "uart1_grp";
162 function = "uart1";
163 };
164 };
165
166 pinctrl_uart2_default: pinctrl-uart2-default {
167 pinmux {
168 groups = "uart2_grp";
169 function = "uart2";
170 };
171 };
35}; 172};
36 173
37&uart0 { 174&uart0 {
38 status = "okay"; 175 status = "okay";
39 clocks = <&uart_clk>; 176 clocks = <&uart_clk>;
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_uart0_default>;
40}; 179};
41 180
42&uart1 { 181&uart1 {
43 status = "okay"; 182 status = "okay";
44 clocks = <&uart_clk>; 183 clocks = <&uart_clk>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_uart1_default>;
45}; 186};
46 187
47&uart2 { 188&uart2 {
48 status = "okay"; 189 status = "okay";
49 clocks = <&uart_clk>; 190 clocks = <&uart_clk>;
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_uart2_default>;
50}; 193};
diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
index 55a4769e0de2..7726fd4c6be6 100644
--- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi
+++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
@@ -80,6 +80,74 @@
80 #interrupt-cells = <3>; 80 #interrupt-cells = <3>;
81 }; 81 };
82 82
83 sctrl: system-controller@50010000 {
84 compatible = "bitmain,bm1880-sctrl", "syscon",
85 "simple-mfd";
86 reg = <0x0 0x50010000 0x0 0x1000>;
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges = <0x0 0x0 0x50010000 0x1000>;
90
91 pinctrl: pinctrl@50 {
92 compatible = "bitmain,bm1880-pinctrl";
93 reg = <0x50 0x4B0>;
94 };
95 };
96
97 gpio0: gpio@50027000 {
98 #address-cells = <1>;
99 #size-cells = <0>;
100 compatible = "snps,dw-apb-gpio";
101 reg = <0x0 0x50027000 0x0 0x400>;
102
103 porta: gpio-controller@0 {
104 compatible = "snps,dw-apb-gpio-port";
105 gpio-controller;
106 #gpio-cells = <2>;
107 snps,nr-gpios = <32>;
108 reg = <0>;
109 interrupt-controller;
110 #interrupt-cells = <2>;
111 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
112 };
113 };
114
115 gpio1: gpio@50027400 {
116 #address-cells = <1>;
117 #size-cells = <0>;
118 compatible = "snps,dw-apb-gpio";
119 reg = <0x0 0x50027400 0x0 0x400>;
120
121 portb: gpio-controller@0 {
122 compatible = "snps,dw-apb-gpio-port";
123 gpio-controller;
124 #gpio-cells = <2>;
125 snps,nr-gpios = <32>;
126 reg = <0>;
127 interrupt-controller;
128 #interrupt-cells = <2>;
129 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
130 };
131 };
132
133 gpio2: gpio@50027800 {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 compatible = "snps,dw-apb-gpio";
137 reg = <0x0 0x50027800 0x0 0x400>;
138
139 portc: gpio-controller@0 {
140 compatible = "snps,dw-apb-gpio-port";
141 gpio-controller;
142 #gpio-cells = <2>;
143 snps,nr-gpios = <8>;
144 reg = <0>;
145 interrupt-controller;
146 #interrupt-cells = <2>;
147 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
148 };
149 };
150
83 uart0: serial@58018000 { 151 uart0: serial@58018000 {
84 compatible = "snps,dw-apb-uart"; 152 compatible = "snps,dw-apb-uart";
85 reg = <0x0 0x58018000 0x0 0x2000>; 153 reg = <0x0 0x58018000 0x0 0x2000>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-30 16:07:28 -0500