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-rw-r--r--Documentation/devicetree/bindings/eeprom/at24.txt3
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mtk.txt1
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-xscale.txt20
-rw-r--r--Documentation/i2c/fault-codes4
-rw-r--r--Documentation/i2c/gpio-fault-injection61
-rw-r--r--MAINTAINERS1
-rw-r--r--arch/arm/mach-omap1/board-nokia770.c18
-rw-r--r--drivers/i2c/algos/i2c-algo-bit.c25
-rw-r--r--drivers/i2c/busses/i2c-aspeed.c120
-rw-r--r--drivers/i2c/busses/i2c-brcmstb.c13
-rw-r--r--drivers/i2c/busses/i2c-cbus-gpio.c80
-rw-r--r--drivers/i2c/busses/i2c-designware-core.h2
-rw-r--r--drivers/i2c/busses/i2c-designware-master.c6
-rw-r--r--drivers/i2c/busses/i2c-designware-pcidrv.c7
-rw-r--r--drivers/i2c/busses/i2c-designware-platdrv.c3
-rw-r--r--drivers/i2c/busses/i2c-exynos5.c11
-rw-r--r--drivers/i2c/busses/i2c-gpio.c134
-rw-r--r--drivers/i2c/busses/i2c-imx.c37
-rw-r--r--drivers/i2c/busses/i2c-iop3xx.c8
-rw-r--r--drivers/i2c/busses/i2c-mt65xx.c6
-rw-r--r--drivers/i2c/busses/i2c-ocores.c308
-rw-r--r--drivers/i2c/busses/i2c-rcar.c49
-rw-r--r--drivers/i2c/busses/i2c-s3c2410.c8
-rw-r--r--drivers/i2c/busses/i2c-sh_mobile.c121
-rw-r--r--drivers/i2c/busses/i2c-sprd.c34
-rw-r--r--drivers/i2c/busses/i2c-synquacer.c5
-rw-r--r--drivers/i2c/busses/i2c-tegra.c740
-rw-r--r--drivers/i2c/busses/i2c-zx2967.c8
-rw-r--r--drivers/i2c/i2c-core-base.c12
-rw-r--r--drivers/i2c/i2c-core-of.c14
-rw-r--r--drivers/i2c/i2c-core-smbus.c2
-rw-r--r--drivers/i2c/i2c-dev.c2
-rw-r--r--drivers/misc/eeprom/at24.c169
-rw-r--r--include/linux/acpi.h11
-rw-r--r--include/linux/i2c-algo-bit.h33
-rw-r--r--include/linux/i2c.h45
-rw-r--r--include/linux/platform_data/at24.h60
-rw-r--r--include/linux/platform_data/i2c-cbus-gpio.h27
-rw-r--r--include/linux/platform_data/i2c-ocores.h6
-rw-r--r--include/trace/events/smbus.h6
40 files changed, 1560 insertions, 660 deletions
diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt
index f9a7c984274c..0e456bbc1213 100644
--- a/Documentation/devicetree/bindings/eeprom/at24.txt
+++ b/Documentation/devicetree/bindings/eeprom/at24.txt
@@ -75,6 +75,8 @@ Optional properties:
75 75
76 - address-width: number of address bits (one of 8, 16). 76 - address-width: number of address bits (one of 8, 16).
77 77
78 - num-addresses: total number of i2c slave addresses this device takes
79
78Example: 80Example:
79 81
80eeprom@52 { 82eeprom@52 {
@@ -82,4 +84,5 @@ eeprom@52 {
82 reg = <0x52>; 84 reg = <0x52>;
83 pagesize = <32>; 85 pagesize = <32>;
84 wp-gpios = <&gpio1 3 0>; 86 wp-gpios = <&gpio1 3 0>;
87 num-addresses = <8>;
85}; 88};
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
index e199695b1c96..ee4c32454198 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
@@ -10,6 +10,7 @@ Required properties:
10 "mediatek,mt6589-i2c": for MediaTek MT6589 10 "mediatek,mt6589-i2c": for MediaTek MT6589
11 "mediatek,mt7622-i2c": for MediaTek MT7622 11 "mediatek,mt7622-i2c": for MediaTek MT7622
12 "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623 12 "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
13 "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
13 "mediatek,mt8173-i2c": for MediaTek MT8173 14 "mediatek,mt8173-i2c": for MediaTek MT8173
14 - reg: physical base address of the controller and dma base, length of memory 15 - reg: physical base address of the controller and dma base, length of memory
15 mapped region. 16 mapped region.
diff --git a/Documentation/devicetree/bindings/i2c/i2c-xscale.txt b/Documentation/devicetree/bindings/i2c/i2c-xscale.txt
new file mode 100644
index 000000000000..dcc8390e0d24
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-xscale.txt
@@ -0,0 +1,20 @@
1i2c Controller on XScale platforms such as IOP3xx and IXP4xx
2
3Required properties:
4- compatible : Must be one of
5 "intel,iop3xx-i2c"
6 "intel,ixp4xx-i2c";
7- reg
8- #address-cells = <1>;
9- #size-cells = <0>;
10
11Optional properties:
12- Child nodes conforming to i2c bus binding
13
14Example:
15
16i2c@c8011000 {
17 compatible = "intel,ixp4xx-i2c";
18 reg = <0xc8011000 0x18>;
19 interrupts = <33 IRQ_TYPE_LEVEL_LOW>;
20};
diff --git a/Documentation/i2c/fault-codes b/Documentation/i2c/fault-codes
index 47c25abb7d52..0cee0fc545b4 100644
--- a/Documentation/i2c/fault-codes
+++ b/Documentation/i2c/fault-codes
@@ -112,6 +112,10 @@ EPROTO
112 case is when the length of an SMBus block data response 112 case is when the length of an SMBus block data response
113 (from the SMBus slave) is outside the range 1-32 bytes. 113 (from the SMBus slave) is outside the range 1-32 bytes.
114 114
115ESHUTDOWN
116 Returned when a transfer was requested using an adapter
117 which is already suspended.
118
115ETIMEDOUT 119ETIMEDOUT
116 This is returned by drivers when an operation took too much 120 This is returned by drivers when an operation took too much
117 time, and was aborted before it completed. 121 time, and was aborted before it completed.
diff --git a/Documentation/i2c/gpio-fault-injection b/Documentation/i2c/gpio-fault-injection
index a4ce62090fd5..c87f416d53dd 100644
--- a/Documentation/i2c/gpio-fault-injection
+++ b/Documentation/i2c/gpio-fault-injection
@@ -1,3 +1,4 @@
1=========================
1Linux I2C fault injection 2Linux I2C fault injection
2========================= 3=========================
3 4
@@ -13,6 +14,9 @@ mounted at /sys/kernel/debug. There will be a separate subdirectory per GPIO
13driven I2C bus. Each subdirectory will contain files to trigger the fault 14driven I2C bus. Each subdirectory will contain files to trigger the fault
14injection. They will be described now along with their intended use-cases. 15injection. They will be described now along with their intended use-cases.
15 16
17Wire states
18===========
19
16"scl" 20"scl"
17----- 21-----
18 22
@@ -34,10 +38,10 @@ I2C specification version 4, section 3.1.16) using the helpers of the Linux I2C
34core (see 'struct bus_recovery_info'). However, the bus recovery will not 38core (see 'struct bus_recovery_info'). However, the bus recovery will not
35succeed because SDA is still pinned low until you manually release it again 39succeed because SDA is still pinned low until you manually release it again
36with "echo 1 > sda". A test with an automatic release can be done with the 40with "echo 1 > sda". A test with an automatic release can be done with the
37following class of fault injectors. 41"incomplete transfers" class of fault injectors.
38 42
39Introduction to incomplete transfers 43Incomplete transfers
40------------------------------------ 44====================
41 45
42The following fault injectors create situations where SDA will be held low by a 46The following fault injectors create situations where SDA will be held low by a
43device. Bus recovery should be able to fix these situations. But please note: 47device. Bus recovery should be able to fix these situations. But please note:
@@ -79,3 +83,54 @@ This is why bus recovery (up to 9 clock pulses) must either check SDA or send
79additional STOP conditions to ensure the bus has been released. Otherwise 83additional STOP conditions to ensure the bus has been released. Otherwise
80random data will be written to a device! 84random data will be written to a device!
81 85
86Lost arbitration
87================
88
89Here, we want to simulate the condition where the master under test loses the
90bus arbitration against another master in a multi-master setup.
91
92"lose_arbitration"
93------------------
94
95This file is write only and you need to write the duration of the arbitration
96intereference (in µs, maximum is 100ms). The calling process will then sleep
97and wait for the next bus clock. The process is interruptible, though.
98
99Arbitration lost is achieved by waiting for SCL going down by the master under
100test and then pulling SDA low for some time. So, the I2C address sent out
101should be corrupted and that should be detected properly. That means that the
102address sent out should have a lot of '1' bits to be able to detect corruption.
103There doesn't need to be a device at this address because arbitration lost
104should be detected beforehand. Also note, that SCL going down is monitored
105using interrupts, so the interrupt latency might cause the first bits to be not
106corrupted. A good starting point for using this fault injector on an otherwise
107idle bus is:
108
109# echo 200 > lose_arbitration &
110# i2cget -y <bus_to_test> 0x3f
111
112Panic during transfer
113=====================
114
115This fault injector will create a Kernel panic once the master under test
116started a transfer. This usually means that the state machine of the bus master
117driver will be ungracefully interrupted and the bus may end up in an unusual
118state. Use this to check if your shutdown/reboot/boot code can handle this
119scenario.
120
121"inject_panic"
122--------------
123
124This file is write only and you need to write the delay between the detected
125start of a transmission and the induced Kernel panic (in µs, maximum is 100ms).
126The calling process will then sleep and wait for the next bus clock. The
127process is interruptible, though.
128
129Start of a transfer is detected by waiting for SCL going down by the master
130under test. A good starting point for using this fault injector is:
131
132# echo 0 > inject_panic &
133# i2cget -y <bus_to_test> <some_address>
134
135Note that there doesn't need to be a device listening to the address you are
136using. Results may vary depending on that, though.
diff --git a/MAINTAINERS b/MAINTAINERS
index 58de951ee4ba..a5f9d5759604 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2554,7 +2554,6 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git
2554S: Maintained 2554S: Maintained
2555F: Documentation/devicetree/bindings/eeprom/at24.txt 2555F: Documentation/devicetree/bindings/eeprom/at24.txt
2556F: drivers/misc/eeprom/at24.c 2556F: drivers/misc/eeprom/at24.c
2557F: include/linux/platform_data/at24.h
2558 2557
2559ATA OVER ETHERNET (AOE) DRIVER 2558ATA OVER ETHERNET (AOE) DRIVER
2560M: "Ed L. Cashin" <ed.cashin@acm.org> 2559M: "Ed L. Cashin" <ed.cashin@acm.org>
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index eb41db78cd47..10848f573d37 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -10,6 +10,7 @@
10#include <linux/clkdev.h> 10#include <linux/clkdev.h>
11#include <linux/irq.h> 11#include <linux/irq.h>
12#include <linux/gpio.h> 12#include <linux/gpio.h>
13#include <linux/gpio/machine.h>
13#include <linux/kernel.h> 14#include <linux/kernel.h>
14#include <linux/init.h> 15#include <linux/init.h>
15#include <linux/mutex.h> 16#include <linux/mutex.h>
@@ -25,7 +26,6 @@
25#include <linux/platform_data/keypad-omap.h> 26#include <linux/platform_data/keypad-omap.h>
26#include <linux/platform_data/lcd-mipid.h> 27#include <linux/platform_data/lcd-mipid.h>
27#include <linux/platform_data/gpio-omap.h> 28#include <linux/platform_data/gpio-omap.h>
28#include <linux/platform_data/i2c-cbus-gpio.h>
29 29
30#include <asm/mach-types.h> 30#include <asm/mach-types.h>
31#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
@@ -217,18 +217,19 @@ static inline void nokia770_mmc_init(void)
217#endif 217#endif
218 218
219#if IS_ENABLED(CONFIG_I2C_CBUS_GPIO) 219#if IS_ENABLED(CONFIG_I2C_CBUS_GPIO)
220static struct i2c_cbus_platform_data nokia770_cbus_data = { 220static struct gpiod_lookup_table nokia770_cbus_gpio_table = {
221 .clk_gpio = OMAP_MPUIO(9), 221 .dev_id = "i2c-cbus-gpio.2",
222 .dat_gpio = OMAP_MPUIO(10), 222 .table = {
223 .sel_gpio = OMAP_MPUIO(11), 223 GPIO_LOOKUP_IDX("mpuio", 9, NULL, 0, 0), /* clk */
224 GPIO_LOOKUP_IDX("mpuio", 10, NULL, 1, 0), /* dat */
225 GPIO_LOOKUP_IDX("mpuio", 11, NULL, 2, 0), /* sel */
226 { },
227 },
224}; 228};
225 229
226static struct platform_device nokia770_cbus_device = { 230static struct platform_device nokia770_cbus_device = {
227 .name = "i2c-cbus-gpio", 231 .name = "i2c-cbus-gpio",
228 .id = 2, 232 .id = 2,
229 .dev = {
230 .platform_data = &nokia770_cbus_data,
231 },
232}; 233};
233 234
234static struct i2c_board_info nokia770_i2c_board_info_2[] __initdata = { 235static struct i2c_board_info nokia770_i2c_board_info_2[] __initdata = {
@@ -257,6 +258,7 @@ static void __init nokia770_cbus_init(void)
257 nokia770_i2c_board_info_2[1].irq = gpio_to_irq(tahvo_irq_gpio); 258 nokia770_i2c_board_info_2[1].irq = gpio_to_irq(tahvo_irq_gpio);
258 i2c_register_board_info(2, nokia770_i2c_board_info_2, 259 i2c_register_board_info(2, nokia770_i2c_board_info_2,
259 ARRAY_SIZE(nokia770_i2c_board_info_2)); 260 ARRAY_SIZE(nokia770_i2c_board_info_2));
261 gpiod_add_lookup_table(&nokia770_cbus_gpio_table);
260 platform_device_register(&nokia770_cbus_device); 262 platform_device_register(&nokia770_cbus_device);
261} 263}
262#else /* CONFIG_I2C_CBUS_GPIO */ 264#else /* CONFIG_I2C_CBUS_GPIO */
diff --git a/drivers/i2c/algos/i2c-algo-bit.c b/drivers/i2c/algos/i2c-algo-bit.c
index c33dcfb87993..5e5990a83da5 100644
--- a/drivers/i2c/algos/i2c-algo-bit.c
+++ b/drivers/i2c/algos/i2c-algo-bit.c
@@ -1,21 +1,12 @@
1/* ------------------------------------------------------------------------- 1// SPDX-License-Identifier: GPL-2.0+
2 * i2c-algo-bit.c i2c driver algorithms for bit-shift adapters 2/*
3 * ------------------------------------------------------------------------- 3 * i2c-algo-bit.c: i2c driver algorithms for bit-shift adapters
4 *
4 * Copyright (C) 1995-2000 Simon G. Vogl 5 * Copyright (C) 1995-2000 Simon G. Vogl
5 6 *
6 This program is free software; you can redistribute it and/or modify 7 * With some changes from Frodo Looijaard <frodol@dds.nl>, Kyösti Mälkki
7 it under the terms of the GNU General Public License as published by 8 * <kmalkki@cc.hut.fi> and Jean Delvare <jdelvare@suse.de>
8 the Free Software Foundation; either version 2 of the License, or 9 */
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15 * ------------------------------------------------------------------------- */
16
17/* With some changes from Frodo Looijaard <frodol@dds.nl>, Kyösti Mälkki
18 <kmalkki@cc.hut.fi> and Jean Delvare <jdelvare@suse.de> */
19 10
20#include <linux/kernel.h> 11#include <linux/kernel.h>
21#include <linux/module.h> 12#include <linux/module.h>
diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c
index 8dc9161ced38..6c8b38fd6e64 100644
--- a/drivers/i2c/busses/i2c-aspeed.c
+++ b/drivers/i2c/busses/i2c-aspeed.c
@@ -117,6 +117,7 @@
117 117
118enum aspeed_i2c_master_state { 118enum aspeed_i2c_master_state {
119 ASPEED_I2C_MASTER_INACTIVE, 119 ASPEED_I2C_MASTER_INACTIVE,
120 ASPEED_I2C_MASTER_PENDING,
120 ASPEED_I2C_MASTER_START, 121 ASPEED_I2C_MASTER_START,
121 ASPEED_I2C_MASTER_TX_FIRST, 122 ASPEED_I2C_MASTER_TX_FIRST,
122 ASPEED_I2C_MASTER_TX, 123 ASPEED_I2C_MASTER_TX,
@@ -126,12 +127,13 @@ enum aspeed_i2c_master_state {
126}; 127};
127 128
128enum aspeed_i2c_slave_state { 129enum aspeed_i2c_slave_state {
129 ASPEED_I2C_SLAVE_STOP, 130 ASPEED_I2C_SLAVE_INACTIVE,
130 ASPEED_I2C_SLAVE_START, 131 ASPEED_I2C_SLAVE_START,
131 ASPEED_I2C_SLAVE_READ_REQUESTED, 132 ASPEED_I2C_SLAVE_READ_REQUESTED,
132 ASPEED_I2C_SLAVE_READ_PROCESSED, 133 ASPEED_I2C_SLAVE_READ_PROCESSED,
133 ASPEED_I2C_SLAVE_WRITE_REQUESTED, 134 ASPEED_I2C_SLAVE_WRITE_REQUESTED,
134 ASPEED_I2C_SLAVE_WRITE_RECEIVED, 135 ASPEED_I2C_SLAVE_WRITE_RECEIVED,
136 ASPEED_I2C_SLAVE_STOP,
135}; 137};
136 138
137struct aspeed_i2c_bus { 139struct aspeed_i2c_bus {
@@ -156,6 +158,8 @@ struct aspeed_i2c_bus {
156 int cmd_err; 158 int cmd_err;
157 /* Protected only by i2c_lock_bus */ 159 /* Protected only by i2c_lock_bus */
158 int master_xfer_result; 160 int master_xfer_result;
161 /* Multi-master */
162 bool multi_master;
159#if IS_ENABLED(CONFIG_I2C_SLAVE) 163#if IS_ENABLED(CONFIG_I2C_SLAVE)
160 struct i2c_client *slave; 164 struct i2c_client *slave;
161 enum aspeed_i2c_slave_state slave_state; 165 enum aspeed_i2c_slave_state slave_state;
@@ -251,7 +255,7 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
251 } 255 }
252 256
253 /* Slave is not currently active, irq was for someone else. */ 257 /* Slave is not currently active, irq was for someone else. */
254 if (bus->slave_state == ASPEED_I2C_SLAVE_STOP) 258 if (bus->slave_state == ASPEED_I2C_SLAVE_INACTIVE)
255 return irq_handled; 259 return irq_handled;
256 260
257 dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n", 261 dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n",
@@ -277,16 +281,15 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
277 irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP; 281 irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;
278 bus->slave_state = ASPEED_I2C_SLAVE_STOP; 282 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
279 } 283 }
280 if (irq_status & ASPEED_I2CD_INTR_TX_NAK) { 284 if (irq_status & ASPEED_I2CD_INTR_TX_NAK &&
285 bus->slave_state == ASPEED_I2C_SLAVE_READ_PROCESSED) {
281 irq_handled |= ASPEED_I2CD_INTR_TX_NAK; 286 irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
282 bus->slave_state = ASPEED_I2C_SLAVE_STOP; 287 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
283 } 288 }
284 if (irq_status & ASPEED_I2CD_INTR_TX_ACK)
285 irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
286 289
287 switch (bus->slave_state) { 290 switch (bus->slave_state) {
288 case ASPEED_I2C_SLAVE_READ_REQUESTED: 291 case ASPEED_I2C_SLAVE_READ_REQUESTED:
289 if (irq_status & ASPEED_I2CD_INTR_TX_ACK) 292 if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_ACK))
290 dev_err(bus->dev, "Unexpected ACK on read request.\n"); 293 dev_err(bus->dev, "Unexpected ACK on read request.\n");
291 bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED; 294 bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED;
292 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 295 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
@@ -294,9 +297,12 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
294 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG); 297 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
295 break; 298 break;
296 case ASPEED_I2C_SLAVE_READ_PROCESSED: 299 case ASPEED_I2C_SLAVE_READ_PROCESSED:
297 if (!(irq_status & ASPEED_I2CD_INTR_TX_ACK)) 300 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
298 dev_err(bus->dev, 301 dev_err(bus->dev,
299 "Expected ACK after processed read.\n"); 302 "Expected ACK after processed read.\n");
303 break;
304 }
305 irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
300 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value); 306 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
301 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG); 307 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
302 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG); 308 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
@@ -310,10 +316,15 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
310 break; 316 break;
311 case ASPEED_I2C_SLAVE_STOP: 317 case ASPEED_I2C_SLAVE_STOP:
312 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 318 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
319 bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
320 break;
321 case ASPEED_I2C_SLAVE_START:
322 /* Slave was just started. Waiting for the next event. */;
313 break; 323 break;
314 default: 324 default:
315 dev_err(bus->dev, "unhandled slave_state: %d\n", 325 dev_err(bus->dev, "unknown slave_state: %d\n",
316 bus->slave_state); 326 bus->slave_state);
327 bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
317 break; 328 break;
318 } 329 }
319 330
@@ -329,6 +340,17 @@ static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus)
329 u8 slave_addr = i2c_8bit_addr_from_msg(msg); 340 u8 slave_addr = i2c_8bit_addr_from_msg(msg);
330 341
331 bus->master_state = ASPEED_I2C_MASTER_START; 342 bus->master_state = ASPEED_I2C_MASTER_START;
343
344#if IS_ENABLED(CONFIG_I2C_SLAVE)
345 /*
346 * If it's requested in the middle of a slave session, set the master
347 * state to 'pending' then H/W will continue handling this master
348 * command when the bus comes back to the idle state.
349 */
350 if (bus->slave_state != ASPEED_I2C_SLAVE_INACTIVE)
351 bus->master_state = ASPEED_I2C_MASTER_PENDING;
352#endif /* CONFIG_I2C_SLAVE */
353
332 bus->buf_index = 0; 354 bus->buf_index = 0;
333 355
334 if (msg->flags & I2C_M_RD) { 356 if (msg->flags & I2C_M_RD) {
@@ -384,10 +406,6 @@ static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
384 bus->master_state = ASPEED_I2C_MASTER_INACTIVE; 406 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
385 irq_handled |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE; 407 irq_handled |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE;
386 goto out_complete; 408 goto out_complete;
387 } else {
388 /* Master is not currently active, irq was for someone else. */
389 if (bus->master_state == ASPEED_I2C_MASTER_INACTIVE)
390 goto out_no_complete;
391 } 409 }
392 410
393 /* 411 /*
@@ -399,11 +417,32 @@ static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
399 if (ret) { 417 if (ret) {
400 dev_dbg(bus->dev, "received error interrupt: 0x%08x\n", 418 dev_dbg(bus->dev, "received error interrupt: 0x%08x\n",
401 irq_status); 419 irq_status);
402 bus->cmd_err = ret;
403 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
404 irq_handled |= (irq_status & ASPEED_I2CD_INTR_MASTER_ERRORS); 420 irq_handled |= (irq_status & ASPEED_I2CD_INTR_MASTER_ERRORS);
405 goto out_complete; 421 if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE) {
422 bus->cmd_err = ret;
423 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
424 goto out_complete;
425 }
426 }
427
428#if IS_ENABLED(CONFIG_I2C_SLAVE)
429 /*
430 * A pending master command will be started by H/W when the bus comes
431 * back to idle state after completing a slave operation so change the
432 * master state from 'pending' to 'start' at here if slave is inactive.
433 */
434 if (bus->master_state == ASPEED_I2C_MASTER_PENDING) {
435 if (bus->slave_state != ASPEED_I2C_SLAVE_INACTIVE)
436 goto out_no_complete;
437
438 bus->master_state = ASPEED_I2C_MASTER_START;
406 } 439 }
440#endif /* CONFIG_I2C_SLAVE */
441
442 /* Master is not currently active, irq was for someone else. */
443 if (bus->master_state == ASPEED_I2C_MASTER_INACTIVE ||
444 bus->master_state == ASPEED_I2C_MASTER_PENDING)
445 goto out_no_complete;
407 446
408 /* We are in an invalid state; reset bus to a known state. */ 447 /* We are in an invalid state; reset bus to a known state. */
409 if (!bus->msgs) { 448 if (!bus->msgs) {
@@ -423,6 +462,20 @@ static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
423 * then update the state and handle the new state below. 462 * then update the state and handle the new state below.
424 */ 463 */
425 if (bus->master_state == ASPEED_I2C_MASTER_START) { 464 if (bus->master_state == ASPEED_I2C_MASTER_START) {
465#if IS_ENABLED(CONFIG_I2C_SLAVE)
466 /*
467 * If a peer master starts a xfer immediately after it queues a
468 * master command, change its state to 'pending' then H/W will
469 * continue the queued master xfer just after completing the
470 * slave mode session.
471 */
472 if (unlikely(irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH)) {
473 bus->master_state = ASPEED_I2C_MASTER_PENDING;
474 dev_dbg(bus->dev,
475 "master goes pending due to a slave start\n");
476 goto out_no_complete;
477 }
478#endif /* CONFIG_I2C_SLAVE */
426 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) { 479 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
427 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_NAK))) { 480 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_NAK))) {
428 bus->cmd_err = -ENXIO; 481 bus->cmd_err = -ENXIO;
@@ -566,7 +619,8 @@ static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id)
566 * interrupt bits. Each case needs to be handled using corresponding 619 * interrupt bits. Each case needs to be handled using corresponding
567 * handlers depending on the current state. 620 * handlers depending on the current state.
568 */ 621 */
569 if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE) { 622 if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE &&
623 bus->master_state != ASPEED_I2C_MASTER_PENDING) {
570 irq_handled = aspeed_i2c_master_irq(bus, irq_remaining); 624 irq_handled = aspeed_i2c_master_irq(bus, irq_remaining);
571 irq_remaining &= ~irq_handled; 625 irq_remaining &= ~irq_handled;
572 if (irq_remaining) 626 if (irq_remaining)
@@ -601,15 +655,16 @@ static int aspeed_i2c_master_xfer(struct i2c_adapter *adap,
601{ 655{
602 struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap); 656 struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap);
603 unsigned long time_left, flags; 657 unsigned long time_left, flags;
604 int ret = 0;
605 658
606 spin_lock_irqsave(&bus->lock, flags); 659 spin_lock_irqsave(&bus->lock, flags);
607 bus->cmd_err = 0; 660 bus->cmd_err = 0;
608 661
609 /* If bus is busy, attempt recovery. We assume a single master 662 /* If bus is busy in a single master environment, attempt recovery. */
610 * environment. 663 if (!bus->multi_master &&
611 */ 664 (readl(bus->base + ASPEED_I2C_CMD_REG) &
612 if (readl(bus->base + ASPEED_I2C_CMD_REG) & ASPEED_I2CD_BUS_BUSY_STS) { 665 ASPEED_I2CD_BUS_BUSY_STS)) {
666 int ret;
667
613 spin_unlock_irqrestore(&bus->lock, flags); 668 spin_unlock_irqrestore(&bus->lock, flags);
614 ret = aspeed_i2c_recover_bus(bus); 669 ret = aspeed_i2c_recover_bus(bus);
615 if (ret) 670 if (ret)
@@ -629,10 +684,20 @@ static int aspeed_i2c_master_xfer(struct i2c_adapter *adap,
629 time_left = wait_for_completion_timeout(&bus->cmd_complete, 684 time_left = wait_for_completion_timeout(&bus->cmd_complete,
630 bus->adap.timeout); 685 bus->adap.timeout);
631 686
632 if (time_left == 0) 687 if (time_left == 0) {
688 /*
689 * If timed out and bus is still busy in a multi master
690 * environment, attempt recovery at here.
691 */
692 if (bus->multi_master &&
693 (readl(bus->base + ASPEED_I2C_CMD_REG) &
694 ASPEED_I2CD_BUS_BUSY_STS))
695 aspeed_i2c_recover_bus(bus);
696
633 return -ETIMEDOUT; 697 return -ETIMEDOUT;
634 else 698 }
635 return bus->master_xfer_result; 699
700 return bus->master_xfer_result;
636} 701}
637 702
638static u32 aspeed_i2c_functionality(struct i2c_adapter *adap) 703static u32 aspeed_i2c_functionality(struct i2c_adapter *adap)
@@ -672,7 +737,7 @@ static int aspeed_i2c_reg_slave(struct i2c_client *client)
672 __aspeed_i2c_reg_slave(bus, client->addr); 737 __aspeed_i2c_reg_slave(bus, client->addr);
673 738
674 bus->slave = client; 739 bus->slave = client;
675 bus->slave_state = ASPEED_I2C_SLAVE_STOP; 740 bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
676 spin_unlock_irqrestore(&bus->lock, flags); 741 spin_unlock_irqrestore(&bus->lock, flags);
677 742
678 return 0; 743 return 0;
@@ -827,7 +892,9 @@ static int aspeed_i2c_init(struct aspeed_i2c_bus *bus,
827 if (ret < 0) 892 if (ret < 0)
828 return ret; 893 return ret;
829 894
830 if (!of_property_read_bool(pdev->dev.of_node, "multi-master")) 895 if (of_property_read_bool(pdev->dev.of_node, "multi-master"))
896 bus->multi_master = true;
897 else
831 fun_ctrl_reg |= ASPEED_I2CD_MULTI_MASTER_DIS; 898 fun_ctrl_reg |= ASPEED_I2CD_MULTI_MASTER_DIS;
832 899
833 /* Enable Master Mode */ 900 /* Enable Master Mode */
@@ -930,7 +997,6 @@ static int aspeed_i2c_probe_bus(struct platform_device *pdev)
930 init_completion(&bus->cmd_complete); 997 init_completion(&bus->cmd_complete);
931 bus->adap.owner = THIS_MODULE; 998 bus->adap.owner = THIS_MODULE;
932 bus->adap.retries = 0; 999 bus->adap.retries = 0;
933 bus->adap.timeout = 5 * HZ;
934 bus->adap.algo = &aspeed_i2c_algo; 1000 bus->adap.algo = &aspeed_i2c_algo;
935 bus->adap.dev.parent = &pdev->dev; 1001 bus->adap.dev.parent = &pdev->dev;
936 bus->adap.dev.of_node = pdev->dev.of_node; 1002 bus->adap.dev.of_node = pdev->dev.of_node;
diff --git a/drivers/i2c/busses/i2c-brcmstb.c b/drivers/i2c/busses/i2c-brcmstb.c
index 826d32049996..f4d862234980 100644
--- a/drivers/i2c/busses/i2c-brcmstb.c
+++ b/drivers/i2c/busses/i2c-brcmstb.c
@@ -170,7 +170,6 @@ struct brcmstb_i2c_dev {
170 struct bsc_regs *bsc_regmap; 170 struct bsc_regs *bsc_regmap;
171 struct i2c_adapter adapter; 171 struct i2c_adapter adapter;
172 struct completion done; 172 struct completion done;
173 bool is_suspended;
174 u32 clk_freq_hz; 173 u32 clk_freq_hz;
175 int data_regsz; 174 int data_regsz;
176}; 175};
@@ -467,9 +466,6 @@ static int brcmstb_i2c_xfer(struct i2c_adapter *adapter,
467 int xfersz = brcmstb_i2c_get_xfersz(dev); 466 int xfersz = brcmstb_i2c_get_xfersz(dev);
468 u32 cond, cond_per_msg; 467 u32 cond, cond_per_msg;
469 468
470 if (dev->is_suspended)
471 return -EBUSY;
472
473 /* Loop through all messages */ 469 /* Loop through all messages */
474 for (i = 0; i < num; i++) { 470 for (i = 0; i < num; i++) {
475 pmsg = &msgs[i]; 471 pmsg = &msgs[i];
@@ -689,10 +685,7 @@ static int brcmstb_i2c_suspend(struct device *dev)
689{ 685{
690 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev); 686 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
691 687
692 i2c_lock_bus(&i2c_dev->adapter, I2C_LOCK_ROOT_ADAPTER); 688 i2c_mark_adapter_suspended(&i2c_dev->adapter);
693 i2c_dev->is_suspended = true;
694 i2c_unlock_bus(&i2c_dev->adapter, I2C_LOCK_ROOT_ADAPTER);
695
696 return 0; 689 return 0;
697} 690}
698 691
@@ -700,10 +693,8 @@ static int brcmstb_i2c_resume(struct device *dev)
700{ 693{
701 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev); 694 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
702 695
703 i2c_lock_bus(&i2c_dev->adapter, I2C_LOCK_ROOT_ADAPTER);
704 brcmstb_i2c_set_bsc_reg_defaults(i2c_dev); 696 brcmstb_i2c_set_bsc_reg_defaults(i2c_dev);
705 i2c_dev->is_suspended = false; 697 i2c_mark_adapter_resumed(&i2c_dev->adapter);
706 i2c_unlock_bus(&i2c_dev->adapter, I2C_LOCK_ROOT_ADAPTER);
707 698
708 return 0; 699 return 0;
709} 700}
diff --git a/drivers/i2c/busses/i2c-cbus-gpio.c b/drivers/i2c/busses/i2c-cbus-gpio.c
index b4f91e48948a..72df563477b1 100644
--- a/drivers/i2c/busses/i2c-cbus-gpio.c
+++ b/drivers/i2c/busses/i2c-cbus-gpio.c
@@ -18,16 +18,14 @@
18 18
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/i2c.h> 20#include <linux/i2c.h>
21#include <linux/gpio.h>
22#include <linux/slab.h> 21#include <linux/slab.h>
23#include <linux/delay.h> 22#include <linux/delay.h>
24#include <linux/errno.h> 23#include <linux/errno.h>
25#include <linux/kernel.h> 24#include <linux/kernel.h>
26#include <linux/module.h> 25#include <linux/module.h>
27#include <linux/of_gpio.h> 26#include <linux/gpio/consumer.h>
28#include <linux/interrupt.h> 27#include <linux/interrupt.h>
29#include <linux/platform_device.h> 28#include <linux/platform_device.h>
30#include <linux/platform_data/i2c-cbus-gpio.h>
31 29
32/* 30/*
33 * Bit counts are derived from Nokia implementation. These should be checked 31 * Bit counts are derived from Nokia implementation. These should be checked
@@ -39,9 +37,9 @@
39struct cbus_host { 37struct cbus_host {
40 spinlock_t lock; /* host lock */ 38 spinlock_t lock; /* host lock */
41 struct device *dev; 39 struct device *dev;
42 int clk_gpio; 40 struct gpio_desc *clk;
43 int dat_gpio; 41 struct gpio_desc *dat;
44 int sel_gpio; 42 struct gpio_desc *sel;
45}; 43};
46 44
47/** 45/**
@@ -51,9 +49,9 @@ struct cbus_host {
51 */ 49 */
52static void cbus_send_bit(struct cbus_host *host, unsigned bit) 50static void cbus_send_bit(struct cbus_host *host, unsigned bit)
53{ 51{
54 gpio_set_value(host->dat_gpio, bit ? 1 : 0); 52 gpiod_set_value(host->dat, bit ? 1 : 0);
55 gpio_set_value(host->clk_gpio, 1); 53 gpiod_set_value(host->clk, 1);
56 gpio_set_value(host->clk_gpio, 0); 54 gpiod_set_value(host->clk, 0);
57} 55}
58 56
59/** 57/**
@@ -78,9 +76,9 @@ static int cbus_receive_bit(struct cbus_host *host)
78{ 76{
79 int ret; 77 int ret;
80 78
81 gpio_set_value(host->clk_gpio, 1); 79 gpiod_set_value(host->clk, 1);
82 ret = gpio_get_value(host->dat_gpio); 80 ret = gpiod_get_value(host->dat);
83 gpio_set_value(host->clk_gpio, 0); 81 gpiod_set_value(host->clk, 0);
84 return ret; 82 return ret;
85} 83}
86 84
@@ -123,10 +121,10 @@ static int cbus_transfer(struct cbus_host *host, char rw, unsigned dev,
123 spin_lock_irqsave(&host->lock, flags); 121 spin_lock_irqsave(&host->lock, flags);
124 122
125 /* Reset state and start of transfer, SEL stays down during transfer */ 123 /* Reset state and start of transfer, SEL stays down during transfer */
126 gpio_set_value(host->sel_gpio, 0); 124 gpiod_set_value(host->sel, 0);
127 125
128 /* Set the DAT pin to output */ 126 /* Set the DAT pin to output */
129 gpio_direction_output(host->dat_gpio, 1); 127 gpiod_direction_output(host->dat, 1);
130 128
131 /* Send the device address */ 129 /* Send the device address */
132 cbus_send_data(host, dev, CBUS_ADDR_BITS); 130 cbus_send_data(host, dev, CBUS_ADDR_BITS);
@@ -141,12 +139,12 @@ static int cbus_transfer(struct cbus_host *host, char rw, unsigned dev,
141 cbus_send_data(host, data, 16); 139 cbus_send_data(host, data, 16);
142 ret = 0; 140 ret = 0;
143 } else { 141 } else {
144 ret = gpio_direction_input(host->dat_gpio); 142 ret = gpiod_direction_input(host->dat);
145 if (ret) { 143 if (ret) {
146 dev_dbg(host->dev, "failed setting direction\n"); 144 dev_dbg(host->dev, "failed setting direction\n");
147 goto out; 145 goto out;
148 } 146 }
149 gpio_set_value(host->clk_gpio, 1); 147 gpiod_set_value(host->clk, 1);
150 148
151 ret = cbus_receive_word(host); 149 ret = cbus_receive_word(host);
152 if (ret < 0) { 150 if (ret < 0) {
@@ -156,9 +154,9 @@ static int cbus_transfer(struct cbus_host *host, char rw, unsigned dev,
156 } 154 }
157 155
158 /* Indicate end of transfer, SEL goes up until next transfer */ 156 /* Indicate end of transfer, SEL goes up until next transfer */
159 gpio_set_value(host->sel_gpio, 1); 157 gpiod_set_value(host->sel, 1);
160 gpio_set_value(host->clk_gpio, 1); 158 gpiod_set_value(host->clk, 1);
161 gpio_set_value(host->clk_gpio, 0); 159 gpiod_set_value(host->clk, 0);
162 160
163out: 161out:
164 spin_unlock_irqrestore(&host->lock, flags); 162 spin_unlock_irqrestore(&host->lock, flags);
@@ -214,7 +212,6 @@ static int cbus_i2c_probe(struct platform_device *pdev)
214{ 212{
215 struct i2c_adapter *adapter; 213 struct i2c_adapter *adapter;
216 struct cbus_host *chost; 214 struct cbus_host *chost;
217 int ret;
218 215
219 adapter = devm_kzalloc(&pdev->dev, sizeof(struct i2c_adapter), 216 adapter = devm_kzalloc(&pdev->dev, sizeof(struct i2c_adapter),
220 GFP_KERNEL); 217 GFP_KERNEL);
@@ -225,22 +222,20 @@ static int cbus_i2c_probe(struct platform_device *pdev)
225 if (!chost) 222 if (!chost)
226 return -ENOMEM; 223 return -ENOMEM;
227 224
228 if (pdev->dev.of_node) { 225 if (gpiod_count(&pdev->dev, NULL) != 3)
229 struct device_node *dnode = pdev->dev.of_node;
230 if (of_gpio_count(dnode) != 3)
231 return -ENODEV;
232 chost->clk_gpio = of_get_gpio(dnode, 0);
233 chost->dat_gpio = of_get_gpio(dnode, 1);
234 chost->sel_gpio = of_get_gpio(dnode, 2);
235 } else if (dev_get_platdata(&pdev->dev)) {
236 struct i2c_cbus_platform_data *pdata =
237 dev_get_platdata(&pdev->dev);
238 chost->clk_gpio = pdata->clk_gpio;
239 chost->dat_gpio = pdata->dat_gpio;
240 chost->sel_gpio = pdata->sel_gpio;
241 } else {
242 return -ENODEV; 226 return -ENODEV;
243 } 227 chost->clk = devm_gpiod_get_index(&pdev->dev, NULL, 0, GPIOD_OUT_LOW);
228 if (IS_ERR(chost->clk))
229 return PTR_ERR(chost->clk);
230 chost->dat = devm_gpiod_get_index(&pdev->dev, NULL, 1, GPIOD_IN);
231 if (IS_ERR(chost->dat))
232 return PTR_ERR(chost->dat);
233 chost->sel = devm_gpiod_get_index(&pdev->dev, NULL, 2, GPIOD_OUT_HIGH);
234 if (IS_ERR(chost->sel))
235 return PTR_ERR(chost->sel);
236 gpiod_set_consumer_name(chost->clk, "CBUS clk");
237 gpiod_set_consumer_name(chost->dat, "CBUS dat");
238 gpiod_set_consumer_name(chost->sel, "CBUS sel");
244 239
245 adapter->owner = THIS_MODULE; 240 adapter->owner = THIS_MODULE;
246 adapter->class = I2C_CLASS_HWMON; 241 adapter->class = I2C_CLASS_HWMON;
@@ -254,21 +249,6 @@ static int cbus_i2c_probe(struct platform_device *pdev)
254 spin_lock_init(&chost->lock); 249 spin_lock_init(&chost->lock);
255 chost->dev = &pdev->dev; 250 chost->dev = &pdev->dev;
256 251
257 ret = devm_gpio_request_one(&pdev->dev, chost->clk_gpio,
258 GPIOF_OUT_INIT_LOW, "CBUS clk");
259 if (ret)
260 return ret;
261
262 ret = devm_gpio_request_one(&pdev->dev, chost->dat_gpio, GPIOF_IN,
263 "CBUS data");
264 if (ret)
265 return ret;
266
267 ret = devm_gpio_request_one(&pdev->dev, chost->sel_gpio,
268 GPIOF_OUT_INIT_HIGH, "CBUS sel");
269 if (ret)
270 return ret;
271
272 i2c_set_adapdata(adapter, chost); 252 i2c_set_adapdata(adapter, chost);
273 platform_set_drvdata(pdev, adapter); 253 platform_set_drvdata(pdev, adapter);
274 254
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index b4a0b2b99a78..6b4ef1d38fb2 100644
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -215,6 +215,7 @@
215 * @disable_int: function to disable all interrupts 215 * @disable_int: function to disable all interrupts
216 * @init: function to initialize the I2C hardware 216 * @init: function to initialize the I2C hardware
217 * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE 217 * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE
218 * @suspended: set to true if the controller is suspended
218 * 219 *
219 * HCNT and LCNT parameters can be used if the platform knows more accurate 220 * HCNT and LCNT parameters can be used if the platform knows more accurate
220 * values than the one computed based only on the input clock frequency. 221 * values than the one computed based only on the input clock frequency.
@@ -270,6 +271,7 @@ struct dw_i2c_dev {
270 int (*set_sda_hold_time)(struct dw_i2c_dev *dev); 271 int (*set_sda_hold_time)(struct dw_i2c_dev *dev);
271 int mode; 272 int mode;
272 struct i2c_bus_recovery_info rinfo; 273 struct i2c_bus_recovery_info rinfo;
274 bool suspended;
273}; 275};
274 276
275#define ACCESS_SWAP 0x00000001 277#define ACCESS_SWAP 0x00000001
diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c
index 8d1bc44d2530..bb8e3f149979 100644
--- a/drivers/i2c/busses/i2c-designware-master.c
+++ b/drivers/i2c/busses/i2c-designware-master.c
@@ -426,6 +426,12 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
426 426
427 pm_runtime_get_sync(dev->dev); 427 pm_runtime_get_sync(dev->dev);
428 428
429 if (dev->suspended) {
430 dev_err(dev->dev, "Error %s call while suspended\n", __func__);
431 ret = -ESHUTDOWN;
432 goto done_nolock;
433 }
434
429 reinit_completion(&dev->cmd_complete); 435 reinit_completion(&dev->cmd_complete);
430 dev->msgs = msgs; 436 dev->msgs = msgs;
431 dev->msgs_num = num; 437 dev->msgs_num = num;
diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index d50f80487214..76810deb2de6 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -176,6 +176,7 @@ static int i2c_dw_pci_suspend(struct device *dev)
176 struct pci_dev *pdev = to_pci_dev(dev); 176 struct pci_dev *pdev = to_pci_dev(dev);
177 struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev); 177 struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev);
178 178
179 i_dev->suspended = true;
179 i_dev->disable(i_dev); 180 i_dev->disable(i_dev);
180 181
181 return 0; 182 return 0;
@@ -185,8 +186,12 @@ static int i2c_dw_pci_resume(struct device *dev)
185{ 186{
186 struct pci_dev *pdev = to_pci_dev(dev); 187 struct pci_dev *pdev = to_pci_dev(dev);
187 struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev); 188 struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev);
189 int ret;
188 190
189 return i_dev->init(i_dev); 191 ret = i_dev->init(i_dev);
192 i_dev->suspended = false;
193
194 return ret;
190} 195}
191#endif 196#endif
192 197
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 9eaac3be1f63..ead5e7de3e4d 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -454,6 +454,8 @@ static int dw_i2c_plat_suspend(struct device *dev)
454{ 454{
455 struct dw_i2c_dev *i_dev = dev_get_drvdata(dev); 455 struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
456 456
457 i_dev->suspended = true;
458
457 if (i_dev->shared_with_punit) 459 if (i_dev->shared_with_punit)
458 return 0; 460 return 0;
459 461
@@ -471,6 +473,7 @@ static int dw_i2c_plat_resume(struct device *dev)
471 i2c_dw_prepare_clk(i_dev, true); 473 i2c_dw_prepare_clk(i_dev, true);
472 474
473 i_dev->init(i_dev); 475 i_dev->init(i_dev);
476 i_dev->suspended = false;
474 477
475 return 0; 478 return 0;
476} 479}
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index c1ce2299a76e..41de4ee409b6 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -183,7 +183,6 @@ enum i2c_type_exynos {
183 183
184struct exynos5_i2c { 184struct exynos5_i2c {
185 struct i2c_adapter adap; 185 struct i2c_adapter adap;
186 unsigned int suspended:1;
187 186
188 struct i2c_msg *msg; 187 struct i2c_msg *msg;
189 struct completion msg_complete; 188 struct completion msg_complete;
@@ -715,11 +714,6 @@ static int exynos5_i2c_xfer(struct i2c_adapter *adap,
715 struct exynos5_i2c *i2c = adap->algo_data; 714 struct exynos5_i2c *i2c = adap->algo_data;
716 int i, ret; 715 int i, ret;
717 716
718 if (i2c->suspended) {
719 dev_err(i2c->dev, "HS-I2C is not initialized.\n");
720 return -EIO;
721 }
722
723 ret = clk_enable(i2c->clk); 717 ret = clk_enable(i2c->clk);
724 if (ret) 718 if (ret)
725 return ret; 719 return ret;
@@ -847,8 +841,7 @@ static int exynos5_i2c_suspend_noirq(struct device *dev)
847{ 841{
848 struct exynos5_i2c *i2c = dev_get_drvdata(dev); 842 struct exynos5_i2c *i2c = dev_get_drvdata(dev);
849 843
850 i2c->suspended = 1; 844 i2c_mark_adapter_suspended(&i2c->adap);
851
852 clk_unprepare(i2c->clk); 845 clk_unprepare(i2c->clk);
853 846
854 return 0; 847 return 0;
@@ -871,7 +864,7 @@ static int exynos5_i2c_resume_noirq(struct device *dev)
871 864
872 exynos5_i2c_init(i2c); 865 exynos5_i2c_init(i2c);
873 clk_disable(i2c->clk); 866 clk_disable(i2c->clk);
874 i2c->suspended = 0; 867 i2c_mark_adapter_resumed(&i2c->adap);
875 868
876 return 0; 869 return 0;
877} 870}
diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
index c008d209f0b8..bba5c4627de3 100644
--- a/drivers/i2c/busses/i2c-gpio.c
+++ b/drivers/i2c/busses/i2c-gpio.c
@@ -7,17 +7,19 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10#include <linux/completion.h>
10#include <linux/debugfs.h> 11#include <linux/debugfs.h>
11#include <linux/delay.h> 12#include <linux/delay.h>
12#include <linux/i2c.h> 13#include <linux/gpio/consumer.h>
13#include <linux/i2c-algo-bit.h> 14#include <linux/i2c-algo-bit.h>
14#include <linux/platform_data/i2c-gpio.h> 15#include <linux/i2c.h>
15#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/interrupt.h>
16#include <linux/module.h> 18#include <linux/module.h>
17#include <linux/slab.h>
18#include <linux/platform_device.h>
19#include <linux/gpio/consumer.h>
20#include <linux/of.h> 19#include <linux/of.h>
20#include <linux/platform_data/i2c-gpio.h>
21#include <linux/platform_device.h>
22#include <linux/slab.h>
21 23
22struct i2c_gpio_private_data { 24struct i2c_gpio_private_data {
23 struct gpio_desc *sda; 25 struct gpio_desc *sda;
@@ -27,6 +29,9 @@ struct i2c_gpio_private_data {
27 struct i2c_gpio_platform_data pdata; 29 struct i2c_gpio_platform_data pdata;
28#ifdef CONFIG_I2C_GPIO_FAULT_INJECTOR 30#ifdef CONFIG_I2C_GPIO_FAULT_INJECTOR
29 struct dentry *debug_dir; 31 struct dentry *debug_dir;
32 /* these must be protected by bus lock */
33 struct completion scl_irq_completion;
34 u64 scl_irq_data;
30#endif 35#endif
31}; 36};
32 37
@@ -162,6 +167,96 @@ static int fops_incomplete_write_byte_set(void *data, u64 addr)
162} 167}
163DEFINE_DEBUGFS_ATTRIBUTE(fops_incomplete_write_byte, NULL, fops_incomplete_write_byte_set, "%llu\n"); 168DEFINE_DEBUGFS_ATTRIBUTE(fops_incomplete_write_byte, NULL, fops_incomplete_write_byte_set, "%llu\n");
164 169
170static int i2c_gpio_fi_act_on_scl_irq(struct i2c_gpio_private_data *priv,
171 irqreturn_t handler(int, void*))
172{
173 int ret, irq = gpiod_to_irq(priv->scl);
174
175 if (irq < 0)
176 return irq;
177
178 i2c_lock_bus(&priv->adap, I2C_LOCK_ROOT_ADAPTER);
179
180 ret = gpiod_direction_input(priv->scl);
181 if (ret)
182 goto unlock;
183
184 reinit_completion(&priv->scl_irq_completion);
185
186 ret = request_irq(irq, handler, IRQF_TRIGGER_FALLING,
187 "i2c_gpio_fault_injector_scl_irq", priv);
188 if (ret)
189 goto output;
190
191 wait_for_completion_interruptible(&priv->scl_irq_completion);
192
193 free_irq(irq, priv);
194 output:
195 ret = gpiod_direction_output(priv->scl, 1) ?: ret;
196 unlock:
197 i2c_unlock_bus(&priv->adap, I2C_LOCK_ROOT_ADAPTER);
198
199 return ret;
200}
201
202static irqreturn_t lose_arbitration_irq(int irq, void *dev_id)
203{
204 struct i2c_gpio_private_data *priv = dev_id;
205
206 setsda(&priv->bit_data, 0);
207 udelay(priv->scl_irq_data);
208 setsda(&priv->bit_data, 1);
209
210 complete(&priv->scl_irq_completion);
211
212 return IRQ_HANDLED;
213}
214
215static int fops_lose_arbitration_set(void *data, u64 duration)
216{
217 struct i2c_gpio_private_data *priv = data;
218
219 if (duration > 100 * 1000)
220 return -EINVAL;
221
222 priv->scl_irq_data = duration;
223 /*
224 * Interrupt on falling SCL. This ensures that the master under test has
225 * really started the transfer. Interrupt on falling SDA did only
226 * exercise 'bus busy' detection on some HW but not 'arbitration lost'.
227 * Note that the interrupt latency may cause the first bits to be
228 * transmitted correctly.
229 */
230 return i2c_gpio_fi_act_on_scl_irq(priv, lose_arbitration_irq);
231}
232DEFINE_DEBUGFS_ATTRIBUTE(fops_lose_arbitration, NULL, fops_lose_arbitration_set, "%llu\n");
233
234static irqreturn_t inject_panic_irq(int irq, void *dev_id)
235{
236 struct i2c_gpio_private_data *priv = dev_id;
237
238 udelay(priv->scl_irq_data);
239 panic("I2C fault injector induced panic");
240
241 return IRQ_HANDLED;
242}
243
244static int fops_inject_panic_set(void *data, u64 duration)
245{
246 struct i2c_gpio_private_data *priv = data;
247
248 if (duration > 100 * 1000)
249 return -EINVAL;
250
251 priv->scl_irq_data = duration;
252 /*
253 * Interrupt on falling SCL. This ensures that the master under test has
254 * really started the transfer.
255 */
256 return i2c_gpio_fi_act_on_scl_irq(priv, inject_panic_irq);
257}
258DEFINE_DEBUGFS_ATTRIBUTE(fops_inject_panic, NULL, fops_inject_panic_set, "%llu\n");
259
165static void i2c_gpio_fault_injector_init(struct platform_device *pdev) 260static void i2c_gpio_fault_injector_init(struct platform_device *pdev)
166{ 261{
167 struct i2c_gpio_private_data *priv = platform_get_drvdata(pdev); 262 struct i2c_gpio_private_data *priv = platform_get_drvdata(pdev);
@@ -181,12 +276,20 @@ static void i2c_gpio_fault_injector_init(struct platform_device *pdev)
181 if (!priv->debug_dir) 276 if (!priv->debug_dir)
182 return; 277 return;
183 278
184 debugfs_create_file_unsafe("scl", 0600, priv->debug_dir, priv, &fops_scl); 279 init_completion(&priv->scl_irq_completion);
185 debugfs_create_file_unsafe("sda", 0600, priv->debug_dir, priv, &fops_sda); 280
186 debugfs_create_file_unsafe("incomplete_address_phase", 0200, priv->debug_dir, 281 debugfs_create_file_unsafe("incomplete_address_phase", 0200, priv->debug_dir,
187 priv, &fops_incomplete_addr_phase); 282 priv, &fops_incomplete_addr_phase);
188 debugfs_create_file_unsafe("incomplete_write_byte", 0200, priv->debug_dir, 283 debugfs_create_file_unsafe("incomplete_write_byte", 0200, priv->debug_dir,
189 priv, &fops_incomplete_write_byte); 284 priv, &fops_incomplete_write_byte);
285 if (priv->bit_data.getscl) {
286 debugfs_create_file_unsafe("inject_panic", 0200, priv->debug_dir,
287 priv, &fops_inject_panic);
288 debugfs_create_file_unsafe("lose_arbitration", 0200, priv->debug_dir,
289 priv, &fops_lose_arbitration);
290 }
291 debugfs_create_file_unsafe("scl", 0600, priv->debug_dir, priv, &fops_scl);
292 debugfs_create_file_unsafe("sda", 0600, priv->debug_dir, priv, &fops_sda);
190} 293}
191 294
192static void i2c_gpio_fault_injector_exit(struct platform_device *pdev) 295static void i2c_gpio_fault_injector_exit(struct platform_device *pdev)
@@ -286,11 +389,11 @@ static int i2c_gpio_probe(struct platform_device *pdev)
286 389
287 /* 390 /*
288 * First get the GPIO pins; if it fails, we'll defer the probe. 391 * First get the GPIO pins; if it fails, we'll defer the probe.
289 * If the SDA line is marked from platform data or device tree as 392 * If the SCL/SDA lines are marked "open drain" by platform data or
290 * "open drain" it means something outside of our control is making 393 * device tree then this means that something outside of our control is
291 * this line being handled as open drain, and we should just handle 394 * marking these lines to be handled as open drain, and we should just
292 * it as any other output. Else we enforce open drain as this is 395 * handle them as we handle any other output. Else we enforce open
293 * required for an I2C bus. 396 * drain as this is required for an I2C bus.
294 */ 397 */
295 if (pdata->sda_is_open_drain) 398 if (pdata->sda_is_open_drain)
296 gflags = GPIOD_OUT_HIGH; 399 gflags = GPIOD_OUT_HIGH;
@@ -300,13 +403,6 @@ static int i2c_gpio_probe(struct platform_device *pdev)
300 if (IS_ERR(priv->sda)) 403 if (IS_ERR(priv->sda))
301 return PTR_ERR(priv->sda); 404 return PTR_ERR(priv->sda);
302 405
303 /*
304 * If the SCL line is marked from platform data or device tree as
305 * "open drain" it means something outside of our control is making
306 * this line being handled as open drain, and we should just handle
307 * it as any other output. Else we enforce open drain as this is
308 * required for an I2C bus.
309 */
310 if (pdata->scl_is_open_drain) 406 if (pdata->scl_is_open_drain)
311 gflags = GPIOD_OUT_HIGH; 407 gflags = GPIOD_OUT_HIGH;
312 else 408 else
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index fa9ad53845d9..42fed40198a0 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -273,8 +273,8 @@ static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
273} 273}
274 274
275/* Functions for DMA support */ 275/* Functions for DMA support */
276static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 276static int i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
277 dma_addr_t phy_addr) 277 dma_addr_t phy_addr)
278{ 278{
279 struct imx_i2c_dma *dma; 279 struct imx_i2c_dma *dma;
280 struct dma_slave_config dma_sconfig; 280 struct dma_slave_config dma_sconfig;
@@ -283,11 +283,13 @@ static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
283 283
284 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 284 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
285 if (!dma) 285 if (!dma)
286 return; 286 return -ENOMEM;
287 287
288 dma->chan_tx = dma_request_slave_channel(dev, "tx"); 288 dma->chan_tx = dma_request_chan(dev, "tx");
289 if (!dma->chan_tx) { 289 if (IS_ERR(dma->chan_tx)) {
290 dev_dbg(dev, "can't request DMA tx channel\n"); 290 ret = PTR_ERR(dma->chan_tx);
291 if (ret != -ENODEV && ret != -EPROBE_DEFER)
292 dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
291 goto fail_al; 293 goto fail_al;
292 } 294 }
293 295
@@ -298,13 +300,15 @@ static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
298 dma_sconfig.direction = DMA_MEM_TO_DEV; 300 dma_sconfig.direction = DMA_MEM_TO_DEV;
299 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); 301 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
300 if (ret < 0) { 302 if (ret < 0) {
301 dev_dbg(dev, "can't configure tx channel\n"); 303 dev_err(dev, "can't configure tx channel (%d)\n", ret);
302 goto fail_tx; 304 goto fail_tx;
303 } 305 }
304 306
305 dma->chan_rx = dma_request_slave_channel(dev, "rx"); 307 dma->chan_rx = dma_request_chan(dev, "rx");
306 if (!dma->chan_rx) { 308 if (IS_ERR(dma->chan_rx)) {
307 dev_dbg(dev, "can't request DMA rx channel\n"); 309 ret = PTR_ERR(dma->chan_rx);
310 if (ret != -ENODEV && ret != -EPROBE_DEFER)
311 dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
308 goto fail_tx; 312 goto fail_tx;
309 } 313 }
310 314
@@ -315,7 +319,7 @@ static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
315 dma_sconfig.direction = DMA_DEV_TO_MEM; 319 dma_sconfig.direction = DMA_DEV_TO_MEM;
316 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig); 320 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
317 if (ret < 0) { 321 if (ret < 0) {
318 dev_dbg(dev, "can't configure rx channel\n"); 322 dev_err(dev, "can't configure rx channel (%d)\n", ret);
319 goto fail_rx; 323 goto fail_rx;
320 } 324 }
321 325
@@ -324,7 +328,7 @@ static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
324 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 328 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
325 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 329 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
326 330
327 return; 331 return 0;
328 332
329fail_rx: 333fail_rx:
330 dma_release_channel(dma->chan_rx); 334 dma_release_channel(dma->chan_rx);
@@ -332,7 +336,8 @@ fail_tx:
332 dma_release_channel(dma->chan_tx); 336 dma_release_channel(dma->chan_tx);
333fail_al: 337fail_al:
334 devm_kfree(dev, dma); 338 devm_kfree(dev, dma);
335 dev_info(dev, "can't use DMA, using PIO instead.\n"); 339 /* return successfully if there is no dma support */
340 return ret == -ENODEV ? 0 : ret;
336} 341}
337 342
338static void i2c_imx_dma_callback(void *arg) 343static void i2c_imx_dma_callback(void *arg)
@@ -1160,11 +1165,13 @@ static int i2c_imx_probe(struct platform_device *pdev)
1160 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 1165 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1161 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1166 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1162 i2c_imx->adapter.name); 1167 i2c_imx->adapter.name);
1163 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1164 1168
1165 /* Init DMA config if supported */ 1169 /* Init DMA config if supported */
1166 i2c_imx_dma_request(i2c_imx, phy_addr); 1170 ret = i2c_imx_dma_request(i2c_imx, phy_addr);
1171 if (ret < 0)
1172 goto clk_notifier_unregister;
1167 1173
1174 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1168 return 0; /* Return OK */ 1175 return 0; /* Return OK */
1169 1176
1170clk_notifier_unregister: 1177clk_notifier_unregister:
diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c
index 85cbe4b55578..a34cb3848280 100644
--- a/drivers/i2c/busses/i2c-iop3xx.c
+++ b/drivers/i2c/busses/i2c-iop3xx.c
@@ -471,6 +471,7 @@ iop3xx_i2c_probe(struct platform_device *pdev)
471 new_adapter->owner = THIS_MODULE; 471 new_adapter->owner = THIS_MODULE;
472 new_adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 472 new_adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
473 new_adapter->dev.parent = &pdev->dev; 473 new_adapter->dev.parent = &pdev->dev;
474 new_adapter->dev.of_node = pdev->dev.of_node;
474 new_adapter->nr = pdev->id; 475 new_adapter->nr = pdev->id;
475 476
476 /* 477 /*
@@ -508,12 +509,19 @@ out:
508 return ret; 509 return ret;
509} 510}
510 511
512static const struct of_device_id i2c_iop3xx_match[] = {
513 { .compatible = "intel,iop3xx-i2c", },
514 { .compatible = "intel,ixp4xx-i2c", },
515 {},
516};
517MODULE_DEVICE_TABLE(of, i2c_iop3xx_match);
511 518
512static struct platform_driver iop3xx_i2c_driver = { 519static struct platform_driver iop3xx_i2c_driver = {
513 .probe = iop3xx_i2c_probe, 520 .probe = iop3xx_i2c_probe,
514 .remove = iop3xx_i2c_remove, 521 .remove = iop3xx_i2c_remove,
515 .driver = { 522 .driver = {
516 .name = "IOP3xx-I2C", 523 .name = "IOP3xx-I2C",
524 .of_match_table = i2c_iop3xx_match,
517 }, 525 },
518}; 526};
519 527
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index a74ef76705e0..660de1ee68ed 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -456,7 +456,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
456 456
457 control_reg = readw(i2c->base + OFFSET_CONTROL) & 457 control_reg = readw(i2c->base + OFFSET_CONTROL) &
458 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); 458 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
459 if ((i2c->speed_hz > 400000) || (left_num >= 1)) 459 if ((i2c->speed_hz > MAX_FS_MODE_SPEED) || (left_num >= 1))
460 control_reg |= I2C_CONTROL_RS; 460 control_reg |= I2C_CONTROL_RS;
461 461
462 if (i2c->op == I2C_MASTER_WRRD) 462 if (i2c->op == I2C_MASTER_WRRD)
@@ -465,7 +465,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
465 writew(control_reg, i2c->base + OFFSET_CONTROL); 465 writew(control_reg, i2c->base + OFFSET_CONTROL);
466 466
467 /* set start condition */ 467 /* set start condition */
468 if (i2c->speed_hz <= 100000) 468 if (i2c->speed_hz <= I2C_DEFAULT_SPEED)
469 writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF); 469 writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF);
470 else 470 else
471 writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF); 471 writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF);
@@ -642,8 +642,6 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
642 return -ETIMEDOUT; 642 return -ETIMEDOUT;
643 } 643 }
644 644
645 completion_done(&i2c->msg_complete);
646
647 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { 645 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
648 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); 646 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
649 mtk_i2c_init_hw(i2c); 647 mtk_i2c_init_hw(i2c);
diff --git a/drivers/i2c/busses/i2c-ocores.c b/drivers/i2c/busses/i2c-ocores.c
index 87f9caacba85..4e1a077fb688 100644
--- a/drivers/i2c/busses/i2c-ocores.c
+++ b/drivers/i2c/busses/i2c-ocores.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller 3 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
3 * (https://opencores.org/project/i2c/overview) 4 * (https://opencores.org/project/i2c/overview)
@@ -6,13 +7,10 @@
6 * 7 *
7 * Support for the GRLIB port of the controller by 8 * Support for the GRLIB port of the controller by
8 * Andreas Larsson <andreas@gaisler.com> 9 * Andreas Larsson <andreas@gaisler.com>
9 *
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
13 */ 10 */
14 11
15#include <linux/clk.h> 12#include <linux/clk.h>
13#include <linux/delay.h>
16#include <linux/err.h> 14#include <linux/err.h>
17#include <linux/kernel.h> 15#include <linux/kernel.h>
18#include <linux/module.h> 16#include <linux/module.h>
@@ -25,17 +23,28 @@
25#include <linux/slab.h> 23#include <linux/slab.h>
26#include <linux/io.h> 24#include <linux/io.h>
27#include <linux/log2.h> 25#include <linux/log2.h>
26#include <linux/spinlock.h>
27#include <linux/jiffies.h>
28
29#define OCORES_FLAG_POLL BIT(0)
28 30
31/*
32 * 'process_lock' exists because ocores_process() and ocores_process_timeout()
33 * can't run in parallel.
34 */
29struct ocores_i2c { 35struct ocores_i2c {
30 void __iomem *base; 36 void __iomem *base;
37 int iobase;
31 u32 reg_shift; 38 u32 reg_shift;
32 u32 reg_io_width; 39 u32 reg_io_width;
40 unsigned long flags;
33 wait_queue_head_t wait; 41 wait_queue_head_t wait;
34 struct i2c_adapter adap; 42 struct i2c_adapter adap;
35 struct i2c_msg *msg; 43 struct i2c_msg *msg;
36 int pos; 44 int pos;
37 int nmsgs; 45 int nmsgs;
38 int state; /* see STATE_ */ 46 int state; /* see STATE_ */
47 spinlock_t process_lock;
39 struct clk *clk; 48 struct clk *clk;
40 int ip_clock_khz; 49 int ip_clock_khz;
41 int bus_clock_khz; 50 int bus_clock_khz;
@@ -127,6 +136,16 @@ static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg)
127 return ioread32be(i2c->base + (reg << i2c->reg_shift)); 136 return ioread32be(i2c->base + (reg << i2c->reg_shift));
128} 137}
129 138
139static void oc_setreg_io_8(struct ocores_i2c *i2c, int reg, u8 value)
140{
141 outb(value, i2c->iobase + reg);
142}
143
144static inline u8 oc_getreg_io_8(struct ocores_i2c *i2c, int reg)
145{
146 return inb(i2c->iobase + reg);
147}
148
130static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value) 149static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
131{ 150{
132 i2c->setreg(i2c, reg, value); 151 i2c->setreg(i2c, reg, value);
@@ -137,23 +156,29 @@ static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
137 return i2c->getreg(i2c, reg); 156 return i2c->getreg(i2c, reg);
138} 157}
139 158
140static void ocores_process(struct ocores_i2c *i2c) 159static void ocores_process(struct ocores_i2c *i2c, u8 stat)
141{ 160{
142 struct i2c_msg *msg = i2c->msg; 161 struct i2c_msg *msg = i2c->msg;
143 u8 stat = oc_getreg(i2c, OCI2C_STATUS); 162 unsigned long flags;
163
164 /*
165 * If we spin here is because we are in timeout, so we are going
166 * to be in STATE_ERROR. See ocores_process_timeout()
167 */
168 spin_lock_irqsave(&i2c->process_lock, flags);
144 169
145 if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) { 170 if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
146 /* stop has been sent */ 171 /* stop has been sent */
147 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); 172 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
148 wake_up(&i2c->wait); 173 wake_up(&i2c->wait);
149 return; 174 goto out;
150 } 175 }
151 176
152 /* error? */ 177 /* error? */
153 if (stat & OCI2C_STAT_ARBLOST) { 178 if (stat & OCI2C_STAT_ARBLOST) {
154 i2c->state = STATE_ERROR; 179 i2c->state = STATE_ERROR;
155 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 180 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
156 return; 181 goto out;
157 } 182 }
158 183
159 if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) { 184 if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
@@ -163,10 +188,11 @@ static void ocores_process(struct ocores_i2c *i2c)
163 if (stat & OCI2C_STAT_NACK) { 188 if (stat & OCI2C_STAT_NACK) {
164 i2c->state = STATE_ERROR; 189 i2c->state = STATE_ERROR;
165 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 190 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
166 return; 191 goto out;
167 } 192 }
168 } else 193 } else {
169 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA); 194 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
195 }
170 196
171 /* end of msg? */ 197 /* end of msg? */
172 if (i2c->pos == msg->len) { 198 if (i2c->pos == msg->len) {
@@ -183,15 +209,15 @@ static void ocores_process(struct ocores_i2c *i2c)
183 i2c->state = STATE_START; 209 i2c->state = STATE_START;
184 210
185 oc_setreg(i2c, OCI2C_DATA, addr); 211 oc_setreg(i2c, OCI2C_DATA, addr);
186 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); 212 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
187 return; 213 goto out;
188 } else 214 }
189 i2c->state = (msg->flags & I2C_M_RD) 215 i2c->state = (msg->flags & I2C_M_RD)
190 ? STATE_READ : STATE_WRITE; 216 ? STATE_READ : STATE_WRITE;
191 } else { 217 } else {
192 i2c->state = STATE_DONE; 218 i2c->state = STATE_DONE;
193 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 219 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
194 return; 220 goto out;
195 } 221 }
196 } 222 }
197 223
@@ -202,20 +228,148 @@ static void ocores_process(struct ocores_i2c *i2c)
202 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]); 228 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
203 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE); 229 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
204 } 230 }
231
232out:
233 spin_unlock_irqrestore(&i2c->process_lock, flags);
205} 234}
206 235
207static irqreturn_t ocores_isr(int irq, void *dev_id) 236static irqreturn_t ocores_isr(int irq, void *dev_id)
208{ 237{
209 struct ocores_i2c *i2c = dev_id; 238 struct ocores_i2c *i2c = dev_id;
239 u8 stat = oc_getreg(i2c, OCI2C_STATUS);
240
241 if (!(stat & OCI2C_STAT_IF))
242 return IRQ_NONE;
210 243
211 ocores_process(i2c); 244 ocores_process(i2c, stat);
212 245
213 return IRQ_HANDLED; 246 return IRQ_HANDLED;
214} 247}
215 248
216static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 249/**
250 * Process timeout event
251 * @i2c: ocores I2C device instance
252 */
253static void ocores_process_timeout(struct ocores_i2c *i2c)
217{ 254{
218 struct ocores_i2c *i2c = i2c_get_adapdata(adap); 255 unsigned long flags;
256
257 spin_lock_irqsave(&i2c->process_lock, flags);
258 i2c->state = STATE_ERROR;
259 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
260 spin_unlock_irqrestore(&i2c->process_lock, flags);
261}
262
263/**
264 * Wait until something change in a given register
265 * @i2c: ocores I2C device instance
266 * @reg: register to query
267 * @mask: bitmask to apply on register value
268 * @val: expected result
269 * @timeout: timeout in jiffies
270 *
271 * Timeout is necessary to avoid to stay here forever when the chip
272 * does not answer correctly.
273 *
274 * Return: 0 on success, -ETIMEDOUT on timeout
275 */
276static int ocores_wait(struct ocores_i2c *i2c,
277 int reg, u8 mask, u8 val,
278 const unsigned long timeout)
279{
280 unsigned long j;
281
282 j = jiffies + timeout;
283 while (1) {
284 u8 status = oc_getreg(i2c, reg);
285
286 if ((status & mask) == val)
287 break;
288
289 if (time_after(jiffies, j))
290 return -ETIMEDOUT;
291 }
292 return 0;
293}
294
295/**
296 * Wait until is possible to process some data
297 * @i2c: ocores I2C device instance
298 *
299 * Used when the device is in polling mode (interrupts disabled).
300 *
301 * Return: 0 on success, -ETIMEDOUT on timeout
302 */
303static int ocores_poll_wait(struct ocores_i2c *i2c)
304{
305 u8 mask;
306 int err;
307
308 if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
309 /* transfer is over */
310 mask = OCI2C_STAT_BUSY;
311 } else {
312 /* on going transfer */
313 mask = OCI2C_STAT_TIP;
314 /*
315 * We wait for the data to be transferred (8bit),
316 * then we start polling on the ACK/NACK bit
317 */
318 udelay((8 * 1000) / i2c->bus_clock_khz);
319 }
320
321 /*
322 * once we are here we expect to get the expected result immediately
323 * so if after 1ms we timeout then something is broken.
324 */
325 err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1));
326 if (err)
327 dev_warn(i2c->adap.dev.parent,
328 "%s: STATUS timeout, bit 0x%x did not clear in 1ms\n",
329 __func__, mask);
330 return err;
331}
332
333/**
334 * It handles an IRQ-less transfer
335 * @i2c: ocores I2C device instance
336 *
337 * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same
338 * (only that IRQ are not produced). This means that we can re-use entirely
339 * ocores_isr(), we just add our polling code around it.
340 *
341 * It can run in atomic context
342 */
343static void ocores_process_polling(struct ocores_i2c *i2c)
344{
345 while (1) {
346 irqreturn_t ret;
347 int err;
348
349 err = ocores_poll_wait(i2c);
350 if (err) {
351 i2c->state = STATE_ERROR;
352 break; /* timeout */
353 }
354
355 ret = ocores_isr(-1, i2c);
356 if (ret == IRQ_NONE)
357 break; /* all messages have been transferred */
358 }
359}
360
361static int ocores_xfer_core(struct ocores_i2c *i2c,
362 struct i2c_msg *msgs, int num,
363 bool polling)
364{
365 int ret;
366 u8 ctrl;
367
368 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
369 if (polling)
370 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN);
371 else
372 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN);
219 373
220 i2c->msg = msgs; 374 i2c->msg = msgs;
221 i2c->pos = 0; 375 i2c->pos = 0;
@@ -225,11 +379,35 @@ static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
225 oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg)); 379 oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg));
226 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); 380 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
227 381
228 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || 382 if (polling) {
229 (i2c->state == STATE_DONE), HZ)) 383 ocores_process_polling(i2c);
230 return (i2c->state == STATE_DONE) ? num : -EIO; 384 } else {
231 else 385 ret = wait_event_timeout(i2c->wait,
232 return -ETIMEDOUT; 386 (i2c->state == STATE_ERROR) ||
387 (i2c->state == STATE_DONE), HZ);
388 if (ret == 0) {
389 ocores_process_timeout(i2c);
390 return -ETIMEDOUT;
391 }
392 }
393
394 return (i2c->state == STATE_DONE) ? num : -EIO;
395}
396
397static int ocores_xfer_polling(struct i2c_adapter *adap,
398 struct i2c_msg *msgs, int num)
399{
400 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, true);
401}
402
403static int ocores_xfer(struct i2c_adapter *adap,
404 struct i2c_msg *msgs, int num)
405{
406 struct ocores_i2c *i2c = i2c_get_adapdata(adap);
407
408 if (i2c->flags & OCORES_FLAG_POLL)
409 return ocores_xfer_polling(adap, msgs, num);
410 return ocores_xfer_core(i2c, msgs, num, false);
233} 411}
234 412
235static int ocores_init(struct device *dev, struct ocores_i2c *i2c) 413static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
@@ -239,7 +417,8 @@ static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
239 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 417 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
240 418
241 /* make sure the device is disabled */ 419 /* make sure the device is disabled */
242 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); 420 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
421 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
243 422
244 prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1; 423 prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1;
245 prescale = clamp(prescale, 0, 0xffff); 424 prescale = clamp(prescale, 0, 0xffff);
@@ -257,7 +436,7 @@ static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
257 436
258 /* Init the device */ 437 /* Init the device */
259 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); 438 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
260 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN); 439 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN);
261 440
262 return 0; 441 return 0;
263} 442}
@@ -294,13 +473,16 @@ static const struct of_device_id ocores_i2c_match[] = {
294MODULE_DEVICE_TABLE(of, ocores_i2c_match); 473MODULE_DEVICE_TABLE(of, ocores_i2c_match);
295 474
296#ifdef CONFIG_OF 475#ifdef CONFIG_OF
297/* Read and write functions for the GRLIB port of the controller. Registers are 476/*
477 * Read and write functions for the GRLIB port of the controller. Registers are
298 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one 478 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
299 * register. The subsequent registers has their offset decreased accordingly. */ 479 * register. The subsequent registers have their offsets decreased accordingly.
480 */
300static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg) 481static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
301{ 482{
302 u32 rd; 483 u32 rd;
303 int rreg = reg; 484 int rreg = reg;
485
304 if (reg != OCI2C_PRELOW) 486 if (reg != OCI2C_PRELOW)
305 rreg--; 487 rreg--;
306 rd = ioread32be(i2c->base + (rreg << i2c->reg_shift)); 488 rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
@@ -314,6 +496,7 @@ static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
314{ 496{
315 u32 curr, wr; 497 u32 curr, wr;
316 int rreg = reg; 498 int rreg = reg;
499
317 if (reg != OCI2C_PRELOW) 500 if (reg != OCI2C_PRELOW)
318 rreg--; 501 rreg--;
319 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) { 502 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
@@ -402,7 +585,7 @@ static int ocores_i2c_of_probe(struct platform_device *pdev,
402 return 0; 585 return 0;
403} 586}
404#else 587#else
405#define ocores_i2c_of_probe(pdev,i2c) -ENODEV 588#define ocores_i2c_of_probe(pdev, i2c) -ENODEV
406#endif 589#endif
407 590
408static int ocores_i2c_probe(struct platform_device *pdev) 591static int ocores_i2c_probe(struct platform_device *pdev)
@@ -414,25 +597,41 @@ static int ocores_i2c_probe(struct platform_device *pdev)
414 int ret; 597 int ret;
415 int i; 598 int i;
416 599
417 irq = platform_get_irq(pdev, 0);
418 if (irq < 0)
419 return irq;
420
421 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 600 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
422 if (!i2c) 601 if (!i2c)
423 return -ENOMEM; 602 return -ENOMEM;
424 603
604 spin_lock_init(&i2c->process_lock);
605
425 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 606 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
426 i2c->base = devm_ioremap_resource(&pdev->dev, res); 607 if (res) {
427 if (IS_ERR(i2c->base)) 608 i2c->base = devm_ioremap_resource(&pdev->dev, res);
428 return PTR_ERR(i2c->base); 609 if (IS_ERR(i2c->base))
610 return PTR_ERR(i2c->base);
611 } else {
612 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
613 if (!res)
614 return -EINVAL;
615 i2c->iobase = res->start;
616 if (!devm_request_region(&pdev->dev, res->start,
617 resource_size(res),
618 pdev->name)) {
619 dev_err(&pdev->dev, "Can't get I/O resource.\n");
620 return -EBUSY;
621 }
622 i2c->setreg = oc_setreg_io_8;
623 i2c->getreg = oc_getreg_io_8;
624 }
429 625
430 pdata = dev_get_platdata(&pdev->dev); 626 pdata = dev_get_platdata(&pdev->dev);
431 if (pdata) { 627 if (pdata) {
432 i2c->reg_shift = pdata->reg_shift; 628 i2c->reg_shift = pdata->reg_shift;
433 i2c->reg_io_width = pdata->reg_io_width; 629 i2c->reg_io_width = pdata->reg_io_width;
434 i2c->ip_clock_khz = pdata->clock_khz; 630 i2c->ip_clock_khz = pdata->clock_khz;
435 i2c->bus_clock_khz = 100; 631 if (pdata->bus_khz)
632 i2c->bus_clock_khz = pdata->bus_khz;
633 else
634 i2c->bus_clock_khz = 100;
436 } else { 635 } else {
437 ret = ocores_i2c_of_probe(pdev, i2c); 636 ret = ocores_i2c_of_probe(pdev, i2c);
438 if (ret) 637 if (ret)
@@ -470,18 +669,29 @@ static int ocores_i2c_probe(struct platform_device *pdev)
470 } 669 }
471 } 670 }
472 671
672 init_waitqueue_head(&i2c->wait);
673
674 irq = platform_get_irq(pdev, 0);
675 if (irq == -ENXIO) {
676 i2c->flags |= OCORES_FLAG_POLL;
677 } else {
678 if (irq < 0)
679 return irq;
680 }
681
682 if (!(i2c->flags & OCORES_FLAG_POLL)) {
683 ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
684 pdev->name, i2c);
685 if (ret) {
686 dev_err(&pdev->dev, "Cannot claim IRQ\n");
687 goto err_clk;
688 }
689 }
690
473 ret = ocores_init(&pdev->dev, i2c); 691 ret = ocores_init(&pdev->dev, i2c);
474 if (ret) 692 if (ret)
475 goto err_clk; 693 goto err_clk;
476 694
477 init_waitqueue_head(&i2c->wait);
478 ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
479 pdev->name, i2c);
480 if (ret) {
481 dev_err(&pdev->dev, "Cannot claim IRQ\n");
482 goto err_clk;
483 }
484
485 /* hook up driver to tree */ 695 /* hook up driver to tree */
486 platform_set_drvdata(pdev, i2c); 696 platform_set_drvdata(pdev, i2c);
487 i2c->adap = ocores_adapter; 697 i2c->adap = ocores_adapter;
@@ -510,10 +720,11 @@ err_clk:
510static int ocores_i2c_remove(struct platform_device *pdev) 720static int ocores_i2c_remove(struct platform_device *pdev)
511{ 721{
512 struct ocores_i2c *i2c = platform_get_drvdata(pdev); 722 struct ocores_i2c *i2c = platform_get_drvdata(pdev);
723 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
513 724
514 /* disable i2c logic */ 725 /* disable i2c logic */
515 oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL) 726 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
516 & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); 727 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
517 728
518 /* remove adapter & data */ 729 /* remove adapter & data */
519 i2c_del_adapter(&i2c->adap); 730 i2c_del_adapter(&i2c->adap);
@@ -531,7 +742,8 @@ static int ocores_i2c_suspend(struct device *dev)
531 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 742 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
532 743
533 /* make sure the device is disabled */ 744 /* make sure the device is disabled */
534 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); 745 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
746 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
535 747
536 if (!IS_ERR(i2c->clk)) 748 if (!IS_ERR(i2c->clk))
537 clk_disable_unprepare(i2c->clk); 749 clk_disable_unprepare(i2c->clk);
diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
index 254e6219e538..dd52a068b140 100644
--- a/drivers/i2c/busses/i2c-rcar.c
+++ b/drivers/i2c/busses/i2c-rcar.c
@@ -2,8 +2,8 @@
2/* 2/*
3 * Driver for the Renesas R-Car I2C unit 3 * Driver for the Renesas R-Car I2C unit
4 * 4 *
5 * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com> 5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
6 * Copyright (C) 2011-2015 Renesas Electronics Corporation 6 * Copyright (C) 2011-2019 Renesas Electronics Corporation
7 * 7 *
8 * Copyright (C) 2012-14 Renesas Solutions Corp. 8 * Copyright (C) 2012-14 Renesas Solutions Corp.
9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
@@ -39,8 +39,8 @@
39#define ICSAR 0x1C /* slave address */ 39#define ICSAR 0x1C /* slave address */
40#define ICMAR 0x20 /* master address */ 40#define ICMAR 0x20 /* master address */
41#define ICRXTX 0x24 /* data port */ 41#define ICRXTX 0x24 /* data port */
42#define ICDMAER 0x3c /* DMA enable */ 42#define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */
43#define ICFBSCR 0x38 /* first bit setup cycle */ 43#define ICDMAER 0x3c /* DMA enable (Gen3) */
44 44
45/* ICSCR */ 45/* ICSCR */
46#define SDBS (1 << 3) /* slave data buffer select */ 46#define SDBS (1 << 3) /* slave data buffer select */
@@ -83,7 +83,6 @@
83#define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */ 83#define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */
84 84
85/* ICFBSCR */ 85/* ICFBSCR */
86#define TCYC06 0x04 /* 6*Tcyc delay 1st bit between SDA and SCL */
87#define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 86#define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */
88 87
89 88
@@ -212,6 +211,10 @@ static void rcar_i2c_init(struct rcar_i2c_priv *priv)
212 rcar_i2c_write(priv, ICMSR, 0); 211 rcar_i2c_write(priv, ICMSR, 0);
213 /* start clock */ 212 /* start clock */
214 rcar_i2c_write(priv, ICCCR, priv->icccr); 213 rcar_i2c_write(priv, ICCCR, priv->icccr);
214
215 if (priv->devtype == I2C_RCAR_GEN3)
216 rcar_i2c_write(priv, ICFBSCR, TCYC17);
217
215} 218}
216 219
217static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 220static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
@@ -355,9 +358,6 @@ static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
355 rcar_i2c_prepare_msg(priv); 358 rcar_i2c_prepare_msg(priv);
356} 359}
357 360
358/*
359 * interrupt functions
360 */
361static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv) 361static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv)
362{ 362{
363 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE 363 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE
@@ -366,9 +366,6 @@ static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv)
366 /* Disable DMA Master Received/Transmitted */ 366 /* Disable DMA Master Received/Transmitted */
367 rcar_i2c_write(priv, ICDMAER, 0); 367 rcar_i2c_write(priv, ICDMAER, 0);
368 368
369 /* Reset default delay */
370 rcar_i2c_write(priv, ICFBSCR, TCYC06);
371
372 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), 369 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
373 sg_dma_len(&priv->sg), priv->dma_direction); 370 sg_dma_len(&priv->sg), priv->dma_direction);
374 371
@@ -464,9 +461,6 @@ static void rcar_i2c_dma(struct rcar_i2c_priv *priv)
464 return; 461 return;
465 } 462 }
466 463
467 /* Set delay for DMA operations */
468 rcar_i2c_write(priv, ICFBSCR, TCYC17);
469
470 /* Enable DMA Master Received/Transmitted */ 464 /* Enable DMA Master Received/Transmitted */
471 if (read) 465 if (read)
472 rcar_i2c_write(priv, ICDMAER, RMDMAE); 466 rcar_i2c_write(priv, ICDMAER, RMDMAE);
@@ -1017,10 +1011,37 @@ static int rcar_i2c_remove(struct platform_device *pdev)
1017 return 0; 1011 return 0;
1018} 1012}
1019 1013
1014#ifdef CONFIG_PM_SLEEP
1015static int rcar_i2c_suspend(struct device *dev)
1016{
1017 struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1018
1019 i2c_mark_adapter_suspended(&priv->adap);
1020 return 0;
1021}
1022
1023static int rcar_i2c_resume(struct device *dev)
1024{
1025 struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1026
1027 i2c_mark_adapter_resumed(&priv->adap);
1028 return 0;
1029}
1030
1031static const struct dev_pm_ops rcar_i2c_pm_ops = {
1032 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume)
1033};
1034
1035#define DEV_PM_OPS (&rcar_i2c_pm_ops)
1036#else
1037#define DEV_PM_OPS NULL
1038#endif /* CONFIG_PM_SLEEP */
1039
1020static struct platform_driver rcar_i2c_driver = { 1040static struct platform_driver rcar_i2c_driver = {
1021 .driver = { 1041 .driver = {
1022 .name = "i2c-rcar", 1042 .name = "i2c-rcar",
1023 .of_match_table = rcar_i2c_dt_ids, 1043 .of_match_table = rcar_i2c_dt_ids,
1044 .pm = DEV_PM_OPS,
1024 }, 1045 },
1025 .probe = rcar_i2c_probe, 1046 .probe = rcar_i2c_probe,
1026 .remove = rcar_i2c_remove, 1047 .remove = rcar_i2c_remove,
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index 2f2e28d60ef5..53bc021f4a5a 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -104,7 +104,6 @@ enum s3c24xx_i2c_state {
104struct s3c24xx_i2c { 104struct s3c24xx_i2c {
105 wait_queue_head_t wait; 105 wait_queue_head_t wait;
106 kernel_ulong_t quirks; 106 kernel_ulong_t quirks;
107 unsigned int suspended:1;
108 107
109 struct i2c_msg *msg; 108 struct i2c_msg *msg;
110 unsigned int msg_num; 109 unsigned int msg_num;
@@ -703,9 +702,6 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
703 unsigned long timeout; 702 unsigned long timeout;
704 int ret; 703 int ret;
705 704
706 if (i2c->suspended)
707 return -EIO;
708
709 ret = s3c24xx_i2c_set_master(i2c); 705 ret = s3c24xx_i2c_set_master(i2c);
710 if (ret != 0) { 706 if (ret != 0) {
711 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); 707 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
@@ -1246,7 +1242,7 @@ static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1246{ 1242{
1247 struct s3c24xx_i2c *i2c = dev_get_drvdata(dev); 1243 struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1248 1244
1249 i2c->suspended = 1; 1245 i2c_mark_adapter_suspended(&i2c->adap);
1250 1246
1251 if (!IS_ERR(i2c->sysreg)) 1247 if (!IS_ERR(i2c->sysreg))
1252 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg); 1248 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg);
@@ -1267,7 +1263,7 @@ static int s3c24xx_i2c_resume_noirq(struct device *dev)
1267 return ret; 1263 return ret;
1268 s3c24xx_i2c_init(i2c); 1264 s3c24xx_i2c_init(i2c);
1269 clk_disable(i2c->clk); 1265 clk_disable(i2c->clk);
1270 i2c->suspended = 0; 1266 i2c_mark_adapter_resumed(&i2c->adap);
1271 1267
1272 return 0; 1268 return 0;
1273} 1269}
diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
index a64f2ff3cb49..8777af4c695e 100644
--- a/drivers/i2c/busses/i2c-sh_mobile.c
+++ b/drivers/i2c/busses/i2c-sh_mobile.c
@@ -2,8 +2,7 @@
2/* 2/*
3 * SuperH Mobile I2C Controller 3 * SuperH Mobile I2C Controller
4 * 4 *
5 * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com> 5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
6 *
7 * Copyright (C) 2008 Magnus Damm 6 * Copyright (C) 2008 Magnus Damm
8 * 7 *
9 * Portions of the code based on out-of-tree driver i2c-sh7343.c 8 * Portions of the code based on out-of-tree driver i2c-sh7343.c
@@ -303,13 +302,12 @@ static int sh_mobile_i2c_v2_init(struct sh_mobile_i2c_data *pd)
303 return sh_mobile_i2c_check_timing(pd); 302 return sh_mobile_i2c_check_timing(pd);
304} 303}
305 304
306static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, 305static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, enum sh_mobile_i2c_op op)
307 enum sh_mobile_i2c_op op, unsigned char data)
308{ 306{
309 unsigned char ret = 0; 307 unsigned char ret = 0;
310 unsigned long flags; 308 unsigned long flags;
311 309
312 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data); 310 dev_dbg(pd->dev, "op %d\n", op);
313 311
314 spin_lock_irqsave(&pd->lock, flags); 312 spin_lock_irqsave(&pd->lock, flags);
315 313
@@ -317,12 +315,12 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
317 case OP_START: /* issue start and trigger DTE interrupt */ 315 case OP_START: /* issue start and trigger DTE interrupt */
318 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY); 316 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
319 break; 317 break;
320 case OP_TX_FIRST: /* disable DTE interrupt and write data */ 318 case OP_TX_FIRST: /* disable DTE interrupt and write client address */
321 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 319 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
322 iic_wr(pd, ICDR, data); 320 iic_wr(pd, ICDR, i2c_8bit_addr_from_msg(pd->msg));
323 break; 321 break;
324 case OP_TX: /* write data */ 322 case OP_TX: /* write data */
325 iic_wr(pd, ICDR, data); 323 iic_wr(pd, ICDR, pd->msg->buf[pd->pos]);
326 break; 324 break;
327 case OP_TX_STOP: /* issue a stop (or rep_start) */ 325 case OP_TX_STOP: /* issue a stop (or rep_start) */
328 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS 326 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
@@ -353,34 +351,17 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
353 return ret; 351 return ret;
354} 352}
355 353
356static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
357{
358 return pd->pos == -1;
359}
360
361static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
362 unsigned char *buf)
363{
364 switch (pd->pos) {
365 case -1:
366 *buf = i2c_8bit_addr_from_msg(pd->msg);
367 break;
368 default:
369 *buf = pd->msg->buf[pd->pos];
370 }
371}
372
373static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd) 354static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
374{ 355{
375 unsigned char data;
376
377 if (pd->pos == pd->msg->len) { 356 if (pd->pos == pd->msg->len) {
378 i2c_op(pd, OP_TX_STOP, 0); 357 i2c_op(pd, OP_TX_STOP);
379 return 1; 358 return 1;
380 } 359 }
381 360
382 sh_mobile_i2c_get_data(pd, &data); 361 if (pd->pos == -1)
383 i2c_op(pd, sh_mobile_i2c_is_first_byte(pd) ? OP_TX_FIRST : OP_TX, data); 362 i2c_op(pd, OP_TX_FIRST);
363 else
364 i2c_op(pd, OP_TX);
384 365
385 pd->pos++; 366 pd->pos++;
386 return 0; 367 return 0;
@@ -391,45 +372,32 @@ static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
391 unsigned char data; 372 unsigned char data;
392 int real_pos; 373 int real_pos;
393 374
394 do { 375 /* switch from TX (address) to RX (data) adds two interrupts */
395 if (pd->pos <= -1) { 376 real_pos = pd->pos - 2;
396 sh_mobile_i2c_get_data(pd, &data); 377
397 378 if (pd->pos == -1) {
398 if (sh_mobile_i2c_is_first_byte(pd)) 379 i2c_op(pd, OP_TX_FIRST);
399 i2c_op(pd, OP_TX_FIRST, data); 380 } else if (pd->pos == 0) {
400 else 381 i2c_op(pd, OP_TX_TO_RX);
401 i2c_op(pd, OP_TX, data); 382 } else if (pd->pos == pd->msg->len) {
402 break; 383 if (pd->stop_after_dma) {
403 } 384 /* Simulate PIO end condition after DMA transfer */
404 385 i2c_op(pd, OP_RX_STOP);
405 if (pd->pos == 0) { 386 pd->pos++;
406 i2c_op(pd, OP_TX_TO_RX, 0); 387 goto done;
407 break;
408 }
409
410 real_pos = pd->pos - 2;
411
412 if (pd->pos == pd->msg->len) {
413 if (pd->stop_after_dma) {
414 /* Simulate PIO end condition after DMA transfer */
415 i2c_op(pd, OP_RX_STOP, 0);
416 pd->pos++;
417 break;
418 }
419
420 if (real_pos < 0) {
421 i2c_op(pd, OP_RX_STOP, 0);
422 break;
423 }
424 data = i2c_op(pd, OP_RX_STOP_DATA, 0);
425 } else if (real_pos >= 0) {
426 data = i2c_op(pd, OP_RX, 0);
427 } 388 }
428 389
429 if (real_pos >= 0) 390 if (real_pos < 0)
430 pd->msg->buf[real_pos] = data; 391 i2c_op(pd, OP_RX_STOP);
431 } while (0); 392 else
393 data = i2c_op(pd, OP_RX_STOP_DATA);
394 } else if (real_pos >= 0) {
395 data = i2c_op(pd, OP_RX);
396 }
432 397
398 if (real_pos >= 0)
399 pd->msg->buf[real_pos] = data;
400 done:
433 pd->pos++; 401 pd->pos++;
434 return pd->pos == (pd->msg->len + 2); 402 return pd->pos == (pd->msg->len + 2);
435} 403}
@@ -698,7 +666,7 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
698 start_ch(pd, msg, do_start); 666 start_ch(pd, msg, do_start);
699 667
700 if (do_start) 668 if (do_start)
701 i2c_op(pd, OP_START, 0); 669 i2c_op(pd, OP_START);
702 670
703 /* The interrupt handler takes care of the rest... */ 671 /* The interrupt handler takes care of the rest... */
704 timeout = wait_event_timeout(pd->wait, 672 timeout = wait_event_timeout(pd->wait,
@@ -749,8 +717,7 @@ static const struct i2c_adapter_quirks sh_mobile_i2c_quirks = {
749}; 717};
750 718
751/* 719/*
752 * r8a7740 chip has lasting errata on I2C I/O pad reset. 720 * r8a7740 has an errata regarding I2C I/O pad reset needing this workaround.
753 * this is work-around for it.
754 */ 721 */
755static int sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd) 722static int sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd)
756{ 723{
@@ -802,15 +769,15 @@ static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
802 { .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config }, 769 { .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config },
803 { .compatible = "renesas,iic-r8a774c0", .data = &fast_clock_dt_config }, 770 { .compatible = "renesas,iic-r8a774c0", .data = &fast_clock_dt_config },
804 { .compatible = "renesas,iic-r8a7790", .data = &v2_freq_calc_dt_config }, 771 { .compatible = "renesas,iic-r8a7790", .data = &v2_freq_calc_dt_config },
805 { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config }, 772 { .compatible = "renesas,iic-r8a7791", .data = &v2_freq_calc_dt_config },
806 { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config }, 773 { .compatible = "renesas,iic-r8a7792", .data = &v2_freq_calc_dt_config },
807 { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config }, 774 { .compatible = "renesas,iic-r8a7793", .data = &v2_freq_calc_dt_config },
808 { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config }, 775 { .compatible = "renesas,iic-r8a7794", .data = &v2_freq_calc_dt_config },
809 { .compatible = "renesas,rcar-gen2-iic", .data = &fast_clock_dt_config }, 776 { .compatible = "renesas,iic-r8a7795", .data = &v2_freq_calc_dt_config },
810 { .compatible = "renesas,iic-r8a7795", .data = &fast_clock_dt_config }, 777 { .compatible = "renesas,iic-r8a77990", .data = &v2_freq_calc_dt_config },
811 { .compatible = "renesas,rcar-gen3-iic", .data = &fast_clock_dt_config },
812 { .compatible = "renesas,iic-r8a77990", .data = &fast_clock_dt_config },
813 { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config }, 778 { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
779 { .compatible = "renesas,rcar-gen2-iic", .data = &v2_freq_calc_dt_config },
780 { .compatible = "renesas,rcar-gen3-iic", .data = &v2_freq_calc_dt_config },
814 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config }, 781 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
815 {}, 782 {},
816}; 783};
diff --git a/drivers/i2c/busses/i2c-sprd.c b/drivers/i2c/busses/i2c-sprd.c
index a94e724f51dc..961123529678 100644
--- a/drivers/i2c/busses/i2c-sprd.c
+++ b/drivers/i2c/busses/i2c-sprd.c
@@ -86,7 +86,6 @@ struct sprd_i2c {
86 u32 count; 86 u32 count;
87 int irq; 87 int irq;
88 int err; 88 int err;
89 bool is_suspended;
90}; 89};
91 90
92static void sprd_i2c_set_count(struct sprd_i2c *i2c_dev, u32 count) 91static void sprd_i2c_set_count(struct sprd_i2c *i2c_dev, u32 count)
@@ -284,9 +283,6 @@ static int sprd_i2c_master_xfer(struct i2c_adapter *i2c_adap,
284 struct sprd_i2c *i2c_dev = i2c_adap->algo_data; 283 struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
285 int im, ret; 284 int im, ret;
286 285
287 if (i2c_dev->is_suspended)
288 return -EBUSY;
289
290 ret = pm_runtime_get_sync(i2c_dev->dev); 286 ret = pm_runtime_get_sync(i2c_dev->dev);
291 if (ret < 0) 287 if (ret < 0)
292 return ret; 288 return ret;
@@ -586,40 +582,34 @@ static int sprd_i2c_remove(struct platform_device *pdev)
586 return 0; 582 return 0;
587} 583}
588 584
589static int __maybe_unused sprd_i2c_suspend_noirq(struct device *pdev) 585static int __maybe_unused sprd_i2c_suspend_noirq(struct device *dev)
590{ 586{
591 struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev); 587 struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
592
593 i2c_lock_bus(&i2c_dev->adap, I2C_LOCK_ROOT_ADAPTER);
594 i2c_dev->is_suspended = true;
595 i2c_unlock_bus(&i2c_dev->adap, I2C_LOCK_ROOT_ADAPTER);
596 588
597 return pm_runtime_force_suspend(pdev); 589 i2c_mark_adapter_suspended(&i2c_dev->adap);
590 return pm_runtime_force_suspend(dev);
598} 591}
599 592
600static int __maybe_unused sprd_i2c_resume_noirq(struct device *pdev) 593static int __maybe_unused sprd_i2c_resume_noirq(struct device *dev)
601{ 594{
602 struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev); 595 struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
603
604 i2c_lock_bus(&i2c_dev->adap, I2C_LOCK_ROOT_ADAPTER);
605 i2c_dev->is_suspended = false;
606 i2c_unlock_bus(&i2c_dev->adap, I2C_LOCK_ROOT_ADAPTER);
607 596
608 return pm_runtime_force_resume(pdev); 597 i2c_mark_adapter_resumed(&i2c_dev->adap);
598 return pm_runtime_force_resume(dev);
609} 599}
610 600
611static int __maybe_unused sprd_i2c_runtime_suspend(struct device *pdev) 601static int __maybe_unused sprd_i2c_runtime_suspend(struct device *dev)
612{ 602{
613 struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev); 603 struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
614 604
615 clk_disable_unprepare(i2c_dev->clk); 605 clk_disable_unprepare(i2c_dev->clk);
616 606
617 return 0; 607 return 0;
618} 608}
619 609
620static int __maybe_unused sprd_i2c_runtime_resume(struct device *pdev) 610static int __maybe_unused sprd_i2c_runtime_resume(struct device *dev)
621{ 611{
622 struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev); 612 struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
623 int ret; 613 int ret;
624 614
625 ret = clk_prepare_enable(i2c_dev->clk); 615 ret = clk_prepare_enable(i2c_dev->clk);
diff --git a/drivers/i2c/busses/i2c-synquacer.c b/drivers/i2c/busses/i2c-synquacer.c
index 2184b7c3580e..d18b0941b71a 100644
--- a/drivers/i2c/busses/i2c-synquacer.c
+++ b/drivers/i2c/busses/i2c-synquacer.c
@@ -144,8 +144,6 @@ struct synquacer_i2c {
144 u32 timeout_ms; 144 u32 timeout_ms;
145 enum i2c_state state; 145 enum i2c_state state;
146 struct i2c_adapter adapter; 146 struct i2c_adapter adapter;
147
148 bool is_suspended;
149}; 147};
150 148
151static inline int is_lastmsg(struct synquacer_i2c *i2c) 149static inline int is_lastmsg(struct synquacer_i2c *i2c)
@@ -316,9 +314,6 @@ static int synquacer_i2c_doxfer(struct synquacer_i2c *i2c,
316 unsigned long timeout; 314 unsigned long timeout;
317 int ret; 315 int ret;
318 316
319 if (i2c->is_suspended)
320 return -EBUSY;
321
322 synquacer_i2c_hw_init(i2c); 317 synquacer_i2c_hw_init(i2c);
323 bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR); 318 bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
324 if (bsr & SYNQUACER_I2C_BSR_BB) { 319 if (bsr & SYNQUACER_I2C_BSR_BB) {
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index c77adbbea0c7..ebaa78d17d6e 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -6,26 +6,24 @@
6 * Author: Colin Cross <ccross@android.com> 6 * Author: Colin Cross <ccross@android.com>
7 */ 7 */
8 8
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/clk.h> 9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/dmaengine.h>
12#include <linux/dma-mapping.h>
13#include <linux/err.h> 13#include <linux/err.h>
14#include <linux/i2c.h> 14#include <linux/i2c.h>
15#include <linux/io.h> 15#include <linux/init.h>
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/delay.h> 17#include <linux/io.h>
18#include <linux/slab.h> 18#include <linux/iopoll.h>
19#include <linux/of_device.h> 19#include <linux/kernel.h>
20#include <linux/module.h> 20#include <linux/module.h>
21#include <linux/reset.h> 21#include <linux/of_device.h>
22#include <linux/pinctrl/consumer.h> 22#include <linux/pinctrl/consumer.h>
23#include <linux/platform_device.h>
23#include <linux/pm_runtime.h> 24#include <linux/pm_runtime.h>
24#include <linux/iopoll.h> 25#include <linux/reset.h>
25
26#include <asm/unaligned.h>
27 26
28#define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
29#define BYTES_PER_FIFO_WORD 4 27#define BYTES_PER_FIFO_WORD 4
30 28
31#define I2C_CNFG 0x000 29#define I2C_CNFG 0x000
@@ -45,8 +43,8 @@
45#define I2C_FIFO_CONTROL 0x05c 43#define I2C_FIFO_CONTROL 0x05c
46#define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) 44#define I2C_FIFO_CONTROL_TX_FLUSH BIT(1)
47#define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) 45#define I2C_FIFO_CONTROL_RX_FLUSH BIT(0)
48#define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5 46#define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
49#define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2 47#define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
50#define I2C_FIFO_STATUS 0x060 48#define I2C_FIFO_STATUS 0x060
51#define I2C_FIFO_STATUS_TX_MASK 0xF0 49#define I2C_FIFO_STATUS_TX_MASK 0xF0
52#define I2C_FIFO_STATUS_TX_SHIFT 4 50#define I2C_FIFO_STATUS_TX_SHIFT 4
@@ -54,6 +52,7 @@
54#define I2C_FIFO_STATUS_RX_SHIFT 0 52#define I2C_FIFO_STATUS_RX_SHIFT 0
55#define I2C_INT_MASK 0x064 53#define I2C_INT_MASK 0x064
56#define I2C_INT_STATUS 0x068 54#define I2C_INT_STATUS 0x068
55#define I2C_INT_BUS_CLR_DONE BIT(11)
57#define I2C_INT_PACKET_XFER_COMPLETE BIT(7) 56#define I2C_INT_PACKET_XFER_COMPLETE BIT(7)
58#define I2C_INT_ALL_PACKETS_XFER_COMPLETE BIT(6) 57#define I2C_INT_ALL_PACKETS_XFER_COMPLETE BIT(6)
59#define I2C_INT_TX_FIFO_OVERFLOW BIT(5) 58#define I2C_INT_TX_FIFO_OVERFLOW BIT(5)
@@ -96,6 +95,15 @@
96#define I2C_HEADER_MASTER_ADDR_SHIFT 12 95#define I2C_HEADER_MASTER_ADDR_SHIFT 12
97#define I2C_HEADER_SLAVE_ADDR_SHIFT 1 96#define I2C_HEADER_SLAVE_ADDR_SHIFT 1
98 97
98#define I2C_BUS_CLEAR_CNFG 0x084
99#define I2C_BC_SCLK_THRESHOLD 9
100#define I2C_BC_SCLK_THRESHOLD_SHIFT 16
101#define I2C_BC_STOP_COND BIT(2)
102#define I2C_BC_TERMINATE BIT(1)
103#define I2C_BC_ENABLE BIT(0)
104#define I2C_BUS_CLEAR_STATUS 0x088
105#define I2C_BC_STATUS BIT(0)
106
99#define I2C_CONFIG_LOAD 0x08C 107#define I2C_CONFIG_LOAD 0x08C
100#define I2C_MSTR_CONFIG_LOAD BIT(0) 108#define I2C_MSTR_CONFIG_LOAD BIT(0)
101#define I2C_SLV_CONFIG_LOAD BIT(1) 109#define I2C_SLV_CONFIG_LOAD BIT(1)
@@ -118,6 +126,25 @@
118#define I2C_MST_FIFO_STATUS_TX_MASK 0xff0000 126#define I2C_MST_FIFO_STATUS_TX_MASK 0xff0000
119#define I2C_MST_FIFO_STATUS_TX_SHIFT 16 127#define I2C_MST_FIFO_STATUS_TX_SHIFT 16
120 128
129#define I2C_INTERFACE_TIMING_0 0x94
130#define I2C_THIGH_SHIFT 8
131#define I2C_INTERFACE_TIMING_1 0x98
132
133#define I2C_STANDARD_MODE 100000
134#define I2C_FAST_MODE 400000
135#define I2C_FAST_PLUS_MODE 1000000
136#define I2C_HS_MODE 3500000
137
138/* Packet header size in bytes */
139#define I2C_PACKET_HEADER_SIZE 12
140
141/*
142 * Upto I2C_PIO_MODE_MAX_LEN bytes, controller will use PIO mode,
143 * above this, controller will use DMA to fill FIFO.
144 * MAX PIO len is 20 bytes excluding packet header.
145 */
146#define I2C_PIO_MODE_MAX_LEN 32
147
121/* 148/*
122 * msg_end_type: The bus control which need to be send at end of transfer. 149 * msg_end_type: The bus control which need to be send at end of transfer.
123 * @MSG_END_STOP: Send stop pulse at end of transfer. 150 * @MSG_END_STOP: Send stop pulse at end of transfer.
@@ -142,7 +169,10 @@ enum msg_end_type {
142 * @has_config_load_reg: Has the config load register to load the new 169 * @has_config_load_reg: Has the config load register to load the new
143 * configuration. 170 * configuration.
144 * @clk_divisor_hs_mode: Clock divisor in HS mode. 171 * @clk_divisor_hs_mode: Clock divisor in HS mode.
145 * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is 172 * @clk_divisor_std_mode: Clock divisor in standard mode. It is
173 * applicable if there is no fast clock source i.e. single clock
174 * source.
175 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
146 * applicable if there is no fast clock source i.e. single clock 176 * applicable if there is no fast clock source i.e. single clock
147 * source. 177 * source.
148 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is 178 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
@@ -157,6 +187,21 @@ enum msg_end_type {
157 * be transferred in one go. 187 * be transferred in one go.
158 * @quirks: i2c adapter quirks for limiting write/read transfer size and not 188 * @quirks: i2c adapter quirks for limiting write/read transfer size and not
159 * allowing 0 length transfers. 189 * allowing 0 length transfers.
190 * @supports_bus_clear: Bus Clear support to recover from bus hang during
191 * SDA stuck low from device for some unknown reasons.
192 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip.
193 * @tlow_std_mode: Low period of the clock in standard mode.
194 * @thigh_std_mode: High period of the clock in standard mode.
195 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
196 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
197 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
198 * in standard mode.
199 * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop
200 * conditions in fast/fast-plus modes.
201 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions
202 * in HS mode.
203 * @has_interface_timing_reg: Has interface timing register to program the tuned
204 * timing settings.
160 */ 205 */
161struct tegra_i2c_hw_feature { 206struct tegra_i2c_hw_feature {
162 bool has_continue_xfer_support; 207 bool has_continue_xfer_support;
@@ -164,12 +209,23 @@ struct tegra_i2c_hw_feature {
164 bool has_single_clk_source; 209 bool has_single_clk_source;
165 bool has_config_load_reg; 210 bool has_config_load_reg;
166 int clk_divisor_hs_mode; 211 int clk_divisor_hs_mode;
167 int clk_divisor_std_fast_mode; 212 int clk_divisor_std_mode;
213 int clk_divisor_fast_mode;
168 u16 clk_divisor_fast_plus_mode; 214 u16 clk_divisor_fast_plus_mode;
169 bool has_multi_master_mode; 215 bool has_multi_master_mode;
170 bool has_slcg_override_reg; 216 bool has_slcg_override_reg;
171 bool has_mst_fifo; 217 bool has_mst_fifo;
172 const struct i2c_adapter_quirks *quirks; 218 const struct i2c_adapter_quirks *quirks;
219 bool supports_bus_clear;
220 bool has_apb_dma;
221 u8 tlow_std_mode;
222 u8 thigh_std_mode;
223 u8 tlow_fast_fastplus_mode;
224 u8 thigh_fast_fastplus_mode;
225 u32 setup_hold_time_std_mode;
226 u32 setup_hold_time_fast_fast_plus_mode;
227 u32 setup_hold_time_hs_mode;
228 bool has_interface_timing_reg;
173}; 229};
174 230
175/** 231/**
@@ -181,6 +237,7 @@ struct tegra_i2c_hw_feature {
181 * @fast_clk: clock reference for fast clock of I2C controller 237 * @fast_clk: clock reference for fast clock of I2C controller
182 * @rst: reset control for the I2C controller 238 * @rst: reset control for the I2C controller
183 * @base: ioremapped registers cookie 239 * @base: ioremapped registers cookie
240 * @base_phys: physical base address of the I2C controller
184 * @cont_id: I2C controller ID, used for packet header 241 * @cont_id: I2C controller ID, used for packet header
185 * @irq: IRQ number of transfer complete interrupt 242 * @irq: IRQ number of transfer complete interrupt
186 * @irq_disabled: used to track whether or not the interrupt is enabled 243 * @irq_disabled: used to track whether or not the interrupt is enabled
@@ -194,6 +251,13 @@ struct tegra_i2c_hw_feature {
194 * @clk_divisor_non_hs_mode: clock divider for non-high-speed modes 251 * @clk_divisor_non_hs_mode: clock divider for non-high-speed modes
195 * @is_multimaster_mode: track if I2C controller is in multi-master mode 252 * @is_multimaster_mode: track if I2C controller is in multi-master mode
196 * @xfer_lock: lock to serialize transfer submission and processing 253 * @xfer_lock: lock to serialize transfer submission and processing
254 * @tx_dma_chan: DMA transmit channel
255 * @rx_dma_chan: DMA receive channel
256 * @dma_phys: handle to DMA resources
257 * @dma_buf: pointer to allocated DMA buffer
258 * @dma_buf_size: DMA buffer size
259 * @is_curr_dma_xfer: indicates active DMA transfer
260 * @dma_complete: DMA completion notifier
197 */ 261 */
198struct tegra_i2c_dev { 262struct tegra_i2c_dev {
199 struct device *dev; 263 struct device *dev;
@@ -203,6 +267,7 @@ struct tegra_i2c_dev {
203 struct clk *fast_clk; 267 struct clk *fast_clk;
204 struct reset_control *rst; 268 struct reset_control *rst;
205 void __iomem *base; 269 void __iomem *base;
270 phys_addr_t base_phys;
206 int cont_id; 271 int cont_id;
207 int irq; 272 int irq;
208 bool irq_disabled; 273 bool irq_disabled;
@@ -216,6 +281,13 @@ struct tegra_i2c_dev {
216 u16 clk_divisor_non_hs_mode; 281 u16 clk_divisor_non_hs_mode;
217 bool is_multimaster_mode; 282 bool is_multimaster_mode;
218 spinlock_t xfer_lock; 283 spinlock_t xfer_lock;
284 struct dma_chan *tx_dma_chan;
285 struct dma_chan *rx_dma_chan;
286 dma_addr_t dma_phys;
287 u32 *dma_buf;
288 unsigned int dma_buf_size;
289 bool is_curr_dma_xfer;
290 struct completion dma_complete;
219}; 291};
220 292
221static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 293static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
@@ -284,6 +356,111 @@ static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
284 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 356 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
285} 357}
286 358
359static void tegra_i2c_dma_complete(void *args)
360{
361 struct tegra_i2c_dev *i2c_dev = args;
362
363 complete(&i2c_dev->dma_complete);
364}
365
366static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
367{
368 struct dma_async_tx_descriptor *dma_desc;
369 enum dma_transfer_direction dir;
370 struct dma_chan *chan;
371
372 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len);
373 reinit_completion(&i2c_dev->dma_complete);
374 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
375 chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan;
376 dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys,
377 len, dir, DMA_PREP_INTERRUPT |
378 DMA_CTRL_ACK);
379 if (!dma_desc) {
380 dev_err(i2c_dev->dev, "failed to get DMA descriptor\n");
381 return -EINVAL;
382 }
383
384 dma_desc->callback = tegra_i2c_dma_complete;
385 dma_desc->callback_param = i2c_dev;
386 dmaengine_submit(dma_desc);
387 dma_async_issue_pending(chan);
388 return 0;
389}
390
391static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
392{
393 if (i2c_dev->dma_buf) {
394 dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
395 i2c_dev->dma_buf, i2c_dev->dma_phys);
396 i2c_dev->dma_buf = NULL;
397 }
398
399 if (i2c_dev->tx_dma_chan) {
400 dma_release_channel(i2c_dev->tx_dma_chan);
401 i2c_dev->tx_dma_chan = NULL;
402 }
403
404 if (i2c_dev->rx_dma_chan) {
405 dma_release_channel(i2c_dev->rx_dma_chan);
406 i2c_dev->rx_dma_chan = NULL;
407 }
408}
409
410static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
411{
412 struct dma_chan *chan;
413 u32 *dma_buf;
414 dma_addr_t dma_phys;
415 int err;
416
417 if (!i2c_dev->hw->has_apb_dma)
418 return 0;
419
420 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) {
421 dev_dbg(i2c_dev->dev, "Support for APB DMA not enabled!\n");
422 return 0;
423 }
424
425 chan = dma_request_slave_channel_reason(i2c_dev->dev, "rx");
426 if (IS_ERR(chan)) {
427 err = PTR_ERR(chan);
428 goto err_out;
429 }
430
431 i2c_dev->rx_dma_chan = chan;
432
433 chan = dma_request_slave_channel_reason(i2c_dev->dev, "tx");
434 if (IS_ERR(chan)) {
435 err = PTR_ERR(chan);
436 goto err_out;
437 }
438
439 i2c_dev->tx_dma_chan = chan;
440
441 dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
442 &dma_phys, GFP_KERNEL | __GFP_NOWARN);
443 if (!dma_buf) {
444 dev_err(i2c_dev->dev, "failed to allocate the DMA buffer\n");
445 err = -ENOMEM;
446 goto err_out;
447 }
448
449 i2c_dev->dma_buf = dma_buf;
450 i2c_dev->dma_phys = dma_phys;
451 return 0;
452
453err_out:
454 tegra_i2c_release_dma(i2c_dev);
455 if (err != -EPROBE_DEFER) {
456 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err);
457 dev_err(i2c_dev->dev, "falling back to PIO\n");
458 return 0;
459 }
460
461 return err;
462}
463
287static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 464static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
288{ 465{
289 unsigned long timeout = jiffies + HZ; 466 unsigned long timeout = jiffies + HZ;
@@ -518,11 +695,13 @@ static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
518 return 0; 695 return 0;
519} 696}
520 697
521static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 698static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit)
522{ 699{
523 u32 val; 700 u32 val;
524 int err; 701 int err;
525 u32 clk_divisor; 702 u32 clk_divisor, clk_multiplier;
703 u32 tsu_thd = 0;
704 u8 tlow, thigh;
526 705
527 err = pm_runtime_get_sync(i2c_dev->dev); 706 err = pm_runtime_get_sync(i2c_dev->dev);
528 if (err < 0) { 707 if (err < 0) {
@@ -552,6 +731,41 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
552 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT; 731 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
553 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); 732 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
554 733
734 if (i2c_dev->bus_clk_rate > I2C_STANDARD_MODE &&
735 i2c_dev->bus_clk_rate <= I2C_FAST_PLUS_MODE) {
736 tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
737 thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
738 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
739 } else {
740 tlow = i2c_dev->hw->tlow_std_mode;
741 thigh = i2c_dev->hw->thigh_std_mode;
742 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
743 }
744
745 if (i2c_dev->hw->has_interface_timing_reg) {
746 val = (thigh << I2C_THIGH_SHIFT) | tlow;
747 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
748 }
749
750 /*
751 * configure setup and hold times only when tsu_thd is non-zero.
752 * otherwise, preserve the chip default values
753 */
754 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
755 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
756
757 if (!clk_reinit) {
758 clk_multiplier = (tlow + thigh + 2);
759 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
760 err = clk_set_rate(i2c_dev->div_clk,
761 i2c_dev->bus_clk_rate * clk_multiplier);
762 if (err) {
763 dev_err(i2c_dev->dev,
764 "failed changing clock rate: %d\n", err);
765 goto err;
766 }
767 }
768
555 if (!i2c_dev->is_dvc) { 769 if (!i2c_dev->is_dvc) {
556 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 770 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
557 771
@@ -561,16 +775,6 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
561 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 775 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
562 } 776 }
563 777
564 if (i2c_dev->hw->has_mst_fifo) {
565 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
566 I2C_MST_FIFO_CONTROL_RX_TRIG(1);
567 i2c_writel(i2c_dev, val, I2C_MST_FIFO_CONTROL);
568 } else {
569 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
570 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
571 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
572 }
573
574 err = tegra_i2c_flush_fifos(i2c_dev); 778 err = tegra_i2c_flush_fifos(i2c_dev);
575 if (err) 779 if (err)
576 goto err; 780 goto err;
@@ -643,25 +847,44 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
643 goto err; 847 goto err;
644 } 848 }
645 849
646 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 850 /*
647 if (i2c_dev->msg_buf_remaining) 851 * I2C transfer is terminated during the bus clear so skip
648 tegra_i2c_empty_rx_fifo(i2c_dev); 852 * processing the other interrupts.
649 else 853 */
650 BUG(); 854 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
651 } 855 goto err;
652 856
653 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 857 if (!i2c_dev->is_curr_dma_xfer) {
654 if (i2c_dev->msg_buf_remaining) 858 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
655 tegra_i2c_fill_tx_fifo(i2c_dev); 859 if (i2c_dev->msg_buf_remaining)
656 else 860 tegra_i2c_empty_rx_fifo(i2c_dev);
657 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ); 861 else
862 BUG();
863 }
864
865 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
866 if (i2c_dev->msg_buf_remaining)
867 tegra_i2c_fill_tx_fifo(i2c_dev);
868 else
869 tegra_i2c_mask_irq(i2c_dev,
870 I2C_INT_TX_FIFO_DATA_REQ);
871 }
658 } 872 }
659 873
660 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 874 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
661 if (i2c_dev->is_dvc) 875 if (i2c_dev->is_dvc)
662 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 876 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
663 877
878 /*
879 * During message read XFER_COMPLETE interrupt is triggered prior to
880 * DMA completion and during message write XFER_COMPLETE interrupt is
881 * triggered after DMA completion.
882 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer.
883 * so forcing msg_buf_remaining to 0 in DMA mode.
884 */
664 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 885 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
886 if (i2c_dev->is_curr_dma_xfer)
887 i2c_dev->msg_buf_remaining = 0;
665 BUG_ON(i2c_dev->msg_buf_remaining); 888 BUG_ON(i2c_dev->msg_buf_remaining);
666 complete(&i2c_dev->msg_complete); 889 complete(&i2c_dev->msg_complete);
667 } 890 }
@@ -671,16 +894,135 @@ err:
671 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | 894 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
672 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ | 895 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
673 I2C_INT_RX_FIFO_DATA_REQ); 896 I2C_INT_RX_FIFO_DATA_REQ);
897 if (i2c_dev->hw->supports_bus_clear)
898 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
674 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 899 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
675 if (i2c_dev->is_dvc) 900 if (i2c_dev->is_dvc)
676 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 901 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
677 902
903 if (i2c_dev->is_curr_dma_xfer) {
904 if (i2c_dev->msg_read)
905 dmaengine_terminate_async(i2c_dev->rx_dma_chan);
906 else
907 dmaengine_terminate_async(i2c_dev->tx_dma_chan);
908
909 complete(&i2c_dev->dma_complete);
910 }
911
678 complete(&i2c_dev->msg_complete); 912 complete(&i2c_dev->msg_complete);
679done: 913done:
680 spin_unlock(&i2c_dev->xfer_lock); 914 spin_unlock(&i2c_dev->xfer_lock);
681 return IRQ_HANDLED; 915 return IRQ_HANDLED;
682} 916}
683 917
918static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
919 size_t len)
920{
921 u32 val, reg;
922 u8 dma_burst;
923 struct dma_slave_config slv_config = {0};
924 struct dma_chan *chan;
925 int ret;
926 unsigned long reg_offset;
927
928 if (i2c_dev->hw->has_mst_fifo)
929 reg = I2C_MST_FIFO_CONTROL;
930 else
931 reg = I2C_FIFO_CONTROL;
932
933 if (i2c_dev->is_curr_dma_xfer) {
934 if (len & 0xF)
935 dma_burst = 1;
936 else if (len & 0x10)
937 dma_burst = 4;
938 else
939 dma_burst = 8;
940
941 if (i2c_dev->msg_read) {
942 chan = i2c_dev->rx_dma_chan;
943 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);
944 slv_config.src_addr = i2c_dev->base_phys + reg_offset;
945 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
946 slv_config.src_maxburst = dma_burst;
947
948 if (i2c_dev->hw->has_mst_fifo)
949 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst);
950 else
951 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst);
952 } else {
953 chan = i2c_dev->tx_dma_chan;
954 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
955 slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
956 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
957 slv_config.dst_maxburst = dma_burst;
958
959 if (i2c_dev->hw->has_mst_fifo)
960 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst);
961 else
962 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst);
963 }
964
965 slv_config.device_fc = true;
966 ret = dmaengine_slave_config(chan, &slv_config);
967 if (ret < 0) {
968 dev_err(i2c_dev->dev, "DMA slave config failed: %d\n",
969 ret);
970 dev_err(i2c_dev->dev, "falling back to PIO\n");
971 tegra_i2c_release_dma(i2c_dev);
972 i2c_dev->is_curr_dma_xfer = false;
973 } else {
974 goto out;
975 }
976 }
977
978 if (i2c_dev->hw->has_mst_fifo)
979 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
980 I2C_MST_FIFO_CONTROL_RX_TRIG(1);
981 else
982 val = I2C_FIFO_CONTROL_TX_TRIG(8) |
983 I2C_FIFO_CONTROL_RX_TRIG(1);
984out:
985 i2c_writel(i2c_dev, val, reg);
986}
987
988static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap)
989{
990 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
991 int err;
992 unsigned long time_left;
993 u32 reg;
994
995 reinit_completion(&i2c_dev->msg_complete);
996 reg = (I2C_BC_SCLK_THRESHOLD << I2C_BC_SCLK_THRESHOLD_SHIFT) |
997 I2C_BC_STOP_COND | I2C_BC_TERMINATE;
998 i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG);
999 if (i2c_dev->hw->has_config_load_reg) {
1000 err = tegra_i2c_wait_for_config_load(i2c_dev);
1001 if (err)
1002 return err;
1003 }
1004
1005 reg |= I2C_BC_ENABLE;
1006 i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG);
1007 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1008
1009 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
1010 msecs_to_jiffies(50));
1011 if (time_left == 0) {
1012 dev_err(i2c_dev->dev, "timed out for bus clear\n");
1013 return -ETIMEDOUT;
1014 }
1015
1016 reg = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS);
1017 if (!(reg & I2C_BC_STATUS)) {
1018 dev_err(i2c_dev->dev,
1019 "un-recovered arbitration lost\n");
1020 return -EIO;
1021 }
1022
1023 return -EAGAIN;
1024}
1025
684static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 1026static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
685 struct i2c_msg *msg, enum msg_end_type end_state) 1027 struct i2c_msg *msg, enum msg_end_type end_state)
686{ 1028{
@@ -688,6 +1030,11 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
688 u32 int_mask; 1030 u32 int_mask;
689 unsigned long time_left; 1031 unsigned long time_left;
690 unsigned long flags; 1032 unsigned long flags;
1033 size_t xfer_size;
1034 u32 *buffer = NULL;
1035 int err = 0;
1036 bool dma;
1037 u16 xfer_time = 100;
691 1038
692 tegra_i2c_flush_fifos(i2c_dev); 1039 tegra_i2c_flush_fifos(i2c_dev);
693 1040
@@ -697,19 +1044,63 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
697 i2c_dev->msg_read = (msg->flags & I2C_M_RD); 1044 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
698 reinit_completion(&i2c_dev->msg_complete); 1045 reinit_completion(&i2c_dev->msg_complete);
699 1046
1047 if (i2c_dev->msg_read)
1048 xfer_size = msg->len;
1049 else
1050 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE;
1051
1052 xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD);
1053 i2c_dev->is_curr_dma_xfer = (xfer_size > I2C_PIO_MODE_MAX_LEN) &&
1054 i2c_dev->dma_buf;
1055 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size);
1056 dma = i2c_dev->is_curr_dma_xfer;
1057 /*
1058 * Transfer time in mSec = Total bits / transfer rate
1059 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits
1060 */
1061 xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC,
1062 i2c_dev->bus_clk_rate);
700 spin_lock_irqsave(&i2c_dev->xfer_lock, flags); 1063 spin_lock_irqsave(&i2c_dev->xfer_lock, flags);
701 1064
702 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 1065 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
703 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1066 tegra_i2c_unmask_irq(i2c_dev, int_mask);
1067 if (dma) {
1068 if (i2c_dev->msg_read) {
1069 dma_sync_single_for_device(i2c_dev->dev,
1070 i2c_dev->dma_phys,
1071 xfer_size,
1072 DMA_FROM_DEVICE);
1073 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1074 if (err < 0) {
1075 dev_err(i2c_dev->dev,
1076 "starting RX DMA failed, err %d\n",
1077 err);
1078 goto unlock;
1079 }
1080
1081 } else {
1082 dma_sync_single_for_cpu(i2c_dev->dev,
1083 i2c_dev->dma_phys,
1084 xfer_size,
1085 DMA_TO_DEVICE);
1086 buffer = i2c_dev->dma_buf;
1087 }
1088 }
704 1089
705 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | 1090 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
706 PACKET_HEADER0_PROTOCOL_I2C | 1091 PACKET_HEADER0_PROTOCOL_I2C |
707 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) | 1092 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
708 (1 << PACKET_HEADER0_PACKET_ID_SHIFT); 1093 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
709 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1094 if (dma && !i2c_dev->msg_read)
1095 *buffer++ = packet_header;
1096 else
1097 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
710 1098
711 packet_header = msg->len - 1; 1099 packet_header = msg->len - 1;
712 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1100 if (dma && !i2c_dev->msg_read)
1101 *buffer++ = packet_header;
1102 else
1103 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
713 1104
714 packet_header = I2C_HEADER_IE_ENABLE; 1105 packet_header = I2C_HEADER_IE_ENABLE;
715 if (end_state == MSG_END_CONTINUE) 1106 if (end_state == MSG_END_CONTINUE)
@@ -726,31 +1117,85 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
726 packet_header |= I2C_HEADER_CONT_ON_NAK; 1117 packet_header |= I2C_HEADER_CONT_ON_NAK;
727 if (msg->flags & I2C_M_RD) 1118 if (msg->flags & I2C_M_RD)
728 packet_header |= I2C_HEADER_READ; 1119 packet_header |= I2C_HEADER_READ;
729 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1120 if (dma && !i2c_dev->msg_read)
730 1121 *buffer++ = packet_header;
731 if (!(msg->flags & I2C_M_RD)) 1122 else
732 tegra_i2c_fill_tx_fifo(i2c_dev); 1123 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1124
1125 if (!i2c_dev->msg_read) {
1126 if (dma) {
1127 memcpy(buffer, msg->buf, msg->len);
1128 dma_sync_single_for_device(i2c_dev->dev,
1129 i2c_dev->dma_phys,
1130 xfer_size,
1131 DMA_TO_DEVICE);
1132 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1133 if (err < 0) {
1134 dev_err(i2c_dev->dev,
1135 "starting TX DMA failed, err %d\n",
1136 err);
1137 goto unlock;
1138 }
1139 } else {
1140 tegra_i2c_fill_tx_fifo(i2c_dev);
1141 }
1142 }
733 1143
734 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) 1144 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
735 int_mask |= I2C_INT_PACKET_XFER_COMPLETE; 1145 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
736 if (msg->flags & I2C_M_RD) 1146 if (!dma) {
737 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 1147 if (msg->flags & I2C_M_RD)
738 else if (i2c_dev->msg_buf_remaining) 1148 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
739 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 1149 else if (i2c_dev->msg_buf_remaining)
1150 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
1151 }
740 1152
741 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1153 tegra_i2c_unmask_irq(i2c_dev, int_mask);
742 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags);
743 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n", 1154 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
744 i2c_readl(i2c_dev, I2C_INT_MASK)); 1155 i2c_readl(i2c_dev, I2C_INT_MASK));
745 1156
1157unlock:
1158 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags);
1159
1160 if (dma) {
1161 if (err)
1162 return err;
1163
1164 time_left = wait_for_completion_timeout(
1165 &i2c_dev->dma_complete,
1166 msecs_to_jiffies(xfer_time));
1167 if (time_left == 0) {
1168 dev_err(i2c_dev->dev, "DMA transfer timeout\n");
1169 dmaengine_terminate_sync(i2c_dev->msg_read ?
1170 i2c_dev->rx_dma_chan :
1171 i2c_dev->tx_dma_chan);
1172 tegra_i2c_init(i2c_dev, true);
1173 return -ETIMEDOUT;
1174 }
1175
1176 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) {
1177 dma_sync_single_for_cpu(i2c_dev->dev,
1178 i2c_dev->dma_phys,
1179 xfer_size,
1180 DMA_FROM_DEVICE);
1181 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf,
1182 msg->len);
1183 }
1184
1185 if (i2c_dev->msg_err != I2C_ERR_NONE)
1186 dmaengine_synchronize(i2c_dev->msg_read ?
1187 i2c_dev->rx_dma_chan :
1188 i2c_dev->tx_dma_chan);
1189 }
1190
746 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, 1191 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
747 TEGRA_I2C_TIMEOUT); 1192 msecs_to_jiffies(xfer_time));
748 tegra_i2c_mask_irq(i2c_dev, int_mask); 1193 tegra_i2c_mask_irq(i2c_dev, int_mask);
749 1194
750 if (time_left == 0) { 1195 if (time_left == 0) {
751 dev_err(i2c_dev->dev, "i2c transfer timed out\n"); 1196 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
752 1197
753 tegra_i2c_init(i2c_dev); 1198 tegra_i2c_init(i2c_dev, true);
754 return -ETIMEDOUT; 1199 return -ETIMEDOUT;
755 } 1200 }
756 1201
@@ -758,10 +1203,18 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
758 time_left, completion_done(&i2c_dev->msg_complete), 1203 time_left, completion_done(&i2c_dev->msg_complete),
759 i2c_dev->msg_err); 1204 i2c_dev->msg_err);
760 1205
1206 i2c_dev->is_curr_dma_xfer = false;
761 if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) 1207 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
762 return 0; 1208 return 0;
763 1209
764 tegra_i2c_init(i2c_dev); 1210 tegra_i2c_init(i2c_dev, true);
1211 /* start recovery upon arbitration loss in single master mode */
1212 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1213 if (!i2c_dev->is_multimaster_mode)
1214 return i2c_recover_bus(&i2c_dev->adapter);
1215 return -EAGAIN;
1216 }
1217
765 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 1218 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
766 if (msg->flags & I2C_M_IGNORE_NAK) 1219 if (msg->flags & I2C_M_IGNORE_NAK)
767 return 0; 1220 return 0;
@@ -836,12 +1289,17 @@ static const struct i2c_algorithm tegra_i2c_algo = {
836/* payload size is only 12 bit */ 1289/* payload size is only 12 bit */
837static const struct i2c_adapter_quirks tegra_i2c_quirks = { 1290static const struct i2c_adapter_quirks tegra_i2c_quirks = {
838 .flags = I2C_AQ_NO_ZERO_LEN, 1291 .flags = I2C_AQ_NO_ZERO_LEN,
839 .max_read_len = 4096, 1292 .max_read_len = SZ_4K,
840 .max_write_len = 4096, 1293 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
841}; 1294};
842 1295
843static const struct i2c_adapter_quirks tegra194_i2c_quirks = { 1296static const struct i2c_adapter_quirks tegra194_i2c_quirks = {
844 .flags = I2C_AQ_NO_ZERO_LEN, 1297 .flags = I2C_AQ_NO_ZERO_LEN,
1298 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1299};
1300
1301static struct i2c_bus_recovery_info tegra_i2c_recovery_info = {
1302 .recover_bus = tegra_i2c_issue_bus_clear,
845}; 1303};
846 1304
847static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { 1305static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
@@ -849,13 +1307,24 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
849 .has_per_pkt_xfer_complete_irq = false, 1307 .has_per_pkt_xfer_complete_irq = false,
850 .has_single_clk_source = false, 1308 .has_single_clk_source = false,
851 .clk_divisor_hs_mode = 3, 1309 .clk_divisor_hs_mode = 3,
852 .clk_divisor_std_fast_mode = 0, 1310 .clk_divisor_std_mode = 0,
1311 .clk_divisor_fast_mode = 0,
853 .clk_divisor_fast_plus_mode = 0, 1312 .clk_divisor_fast_plus_mode = 0,
854 .has_config_load_reg = false, 1313 .has_config_load_reg = false,
855 .has_multi_master_mode = false, 1314 .has_multi_master_mode = false,
856 .has_slcg_override_reg = false, 1315 .has_slcg_override_reg = false,
857 .has_mst_fifo = false, 1316 .has_mst_fifo = false,
858 .quirks = &tegra_i2c_quirks, 1317 .quirks = &tegra_i2c_quirks,
1318 .supports_bus_clear = false,
1319 .has_apb_dma = true,
1320 .tlow_std_mode = 0x4,
1321 .thigh_std_mode = 0x2,
1322 .tlow_fast_fastplus_mode = 0x4,
1323 .thigh_fast_fastplus_mode = 0x2,
1324 .setup_hold_time_std_mode = 0x0,
1325 .setup_hold_time_fast_fast_plus_mode = 0x0,
1326 .setup_hold_time_hs_mode = 0x0,
1327 .has_interface_timing_reg = false,
859}; 1328};
860 1329
861static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { 1330static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
@@ -863,13 +1332,24 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
863 .has_per_pkt_xfer_complete_irq = false, 1332 .has_per_pkt_xfer_complete_irq = false,
864 .has_single_clk_source = false, 1333 .has_single_clk_source = false,
865 .clk_divisor_hs_mode = 3, 1334 .clk_divisor_hs_mode = 3,
866 .clk_divisor_std_fast_mode = 0, 1335 .clk_divisor_std_mode = 0,
1336 .clk_divisor_fast_mode = 0,
867 .clk_divisor_fast_plus_mode = 0, 1337 .clk_divisor_fast_plus_mode = 0,
868 .has_config_load_reg = false, 1338 .has_config_load_reg = false,
869 .has_multi_master_mode = false, 1339 .has_multi_master_mode = false,
870 .has_slcg_override_reg = false, 1340 .has_slcg_override_reg = false,
871 .has_mst_fifo = false, 1341 .has_mst_fifo = false,
872 .quirks = &tegra_i2c_quirks, 1342 .quirks = &tegra_i2c_quirks,
1343 .supports_bus_clear = false,
1344 .has_apb_dma = true,
1345 .tlow_std_mode = 0x4,
1346 .thigh_std_mode = 0x2,
1347 .tlow_fast_fastplus_mode = 0x4,
1348 .thigh_fast_fastplus_mode = 0x2,
1349 .setup_hold_time_std_mode = 0x0,
1350 .setup_hold_time_fast_fast_plus_mode = 0x0,
1351 .setup_hold_time_hs_mode = 0x0,
1352 .has_interface_timing_reg = false,
873}; 1353};
874 1354
875static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { 1355static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
@@ -877,13 +1357,24 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
877 .has_per_pkt_xfer_complete_irq = true, 1357 .has_per_pkt_xfer_complete_irq = true,
878 .has_single_clk_source = true, 1358 .has_single_clk_source = true,
879 .clk_divisor_hs_mode = 1, 1359 .clk_divisor_hs_mode = 1,
880 .clk_divisor_std_fast_mode = 0x19, 1360 .clk_divisor_std_mode = 0x19,
1361 .clk_divisor_fast_mode = 0x19,
881 .clk_divisor_fast_plus_mode = 0x10, 1362 .clk_divisor_fast_plus_mode = 0x10,
882 .has_config_load_reg = false, 1363 .has_config_load_reg = false,
883 .has_multi_master_mode = false, 1364 .has_multi_master_mode = false,
884 .has_slcg_override_reg = false, 1365 .has_slcg_override_reg = false,
885 .has_mst_fifo = false, 1366 .has_mst_fifo = false,
886 .quirks = &tegra_i2c_quirks, 1367 .quirks = &tegra_i2c_quirks,
1368 .supports_bus_clear = true,
1369 .has_apb_dma = true,
1370 .tlow_std_mode = 0x4,
1371 .thigh_std_mode = 0x2,
1372 .tlow_fast_fastplus_mode = 0x4,
1373 .thigh_fast_fastplus_mode = 0x2,
1374 .setup_hold_time_std_mode = 0x0,
1375 .setup_hold_time_fast_fast_plus_mode = 0x0,
1376 .setup_hold_time_hs_mode = 0x0,
1377 .has_interface_timing_reg = false,
887}; 1378};
888 1379
889static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { 1380static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
@@ -891,13 +1382,24 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
891 .has_per_pkt_xfer_complete_irq = true, 1382 .has_per_pkt_xfer_complete_irq = true,
892 .has_single_clk_source = true, 1383 .has_single_clk_source = true,
893 .clk_divisor_hs_mode = 1, 1384 .clk_divisor_hs_mode = 1,
894 .clk_divisor_std_fast_mode = 0x19, 1385 .clk_divisor_std_mode = 0x19,
1386 .clk_divisor_fast_mode = 0x19,
895 .clk_divisor_fast_plus_mode = 0x10, 1387 .clk_divisor_fast_plus_mode = 0x10,
896 .has_config_load_reg = true, 1388 .has_config_load_reg = true,
897 .has_multi_master_mode = false, 1389 .has_multi_master_mode = false,
898 .has_slcg_override_reg = true, 1390 .has_slcg_override_reg = true,
899 .has_mst_fifo = false, 1391 .has_mst_fifo = false,
900 .quirks = &tegra_i2c_quirks, 1392 .quirks = &tegra_i2c_quirks,
1393 .supports_bus_clear = true,
1394 .has_apb_dma = true,
1395 .tlow_std_mode = 0x4,
1396 .thigh_std_mode = 0x2,
1397 .tlow_fast_fastplus_mode = 0x4,
1398 .thigh_fast_fastplus_mode = 0x2,
1399 .setup_hold_time_std_mode = 0x0,
1400 .setup_hold_time_fast_fast_plus_mode = 0x0,
1401 .setup_hold_time_hs_mode = 0x0,
1402 .has_interface_timing_reg = true,
901}; 1403};
902 1404
903static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { 1405static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
@@ -905,32 +1407,80 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
905 .has_per_pkt_xfer_complete_irq = true, 1407 .has_per_pkt_xfer_complete_irq = true,
906 .has_single_clk_source = true, 1408 .has_single_clk_source = true,
907 .clk_divisor_hs_mode = 1, 1409 .clk_divisor_hs_mode = 1,
908 .clk_divisor_std_fast_mode = 0x19, 1410 .clk_divisor_std_mode = 0x19,
1411 .clk_divisor_fast_mode = 0x19,
909 .clk_divisor_fast_plus_mode = 0x10, 1412 .clk_divisor_fast_plus_mode = 0x10,
910 .has_config_load_reg = true, 1413 .has_config_load_reg = true,
911 .has_multi_master_mode = true, 1414 .has_multi_master_mode = false,
912 .has_slcg_override_reg = true, 1415 .has_slcg_override_reg = true,
913 .has_mst_fifo = false, 1416 .has_mst_fifo = false,
914 .quirks = &tegra_i2c_quirks, 1417 .quirks = &tegra_i2c_quirks,
1418 .supports_bus_clear = true,
1419 .has_apb_dma = true,
1420 .tlow_std_mode = 0x4,
1421 .thigh_std_mode = 0x2,
1422 .tlow_fast_fastplus_mode = 0x4,
1423 .thigh_fast_fastplus_mode = 0x2,
1424 .setup_hold_time_std_mode = 0,
1425 .setup_hold_time_fast_fast_plus_mode = 0,
1426 .setup_hold_time_hs_mode = 0,
1427 .has_interface_timing_reg = true,
915}; 1428};
916 1429
917static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { 1430static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
918 .has_continue_xfer_support = true, 1431 .has_continue_xfer_support = true,
919 .has_per_pkt_xfer_complete_irq = true, 1432 .has_per_pkt_xfer_complete_irq = true,
920 .has_single_clk_source = true, 1433 .has_single_clk_source = true,
921 .clk_divisor_hs_mode = 1, 1434 .clk_divisor_hs_mode = 1,
922 .clk_divisor_std_fast_mode = 0x19, 1435 .clk_divisor_std_mode = 0x16,
1436 .clk_divisor_fast_mode = 0x19,
923 .clk_divisor_fast_plus_mode = 0x10, 1437 .clk_divisor_fast_plus_mode = 0x10,
924 .has_config_load_reg = true, 1438 .has_config_load_reg = true,
1439 .has_multi_master_mode = false,
1440 .has_slcg_override_reg = true,
1441 .has_mst_fifo = false,
1442 .quirks = &tegra_i2c_quirks,
1443 .supports_bus_clear = true,
1444 .has_apb_dma = false,
1445 .tlow_std_mode = 0x4,
1446 .thigh_std_mode = 0x3,
1447 .tlow_fast_fastplus_mode = 0x4,
1448 .thigh_fast_fastplus_mode = 0x2,
1449 .setup_hold_time_std_mode = 0,
1450 .setup_hold_time_fast_fast_plus_mode = 0,
1451 .setup_hold_time_hs_mode = 0,
1452 .has_interface_timing_reg = true,
1453};
1454
1455static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
1456 .has_continue_xfer_support = true,
1457 .has_per_pkt_xfer_complete_irq = true,
1458 .has_single_clk_source = true,
1459 .clk_divisor_hs_mode = 1,
1460 .clk_divisor_std_mode = 0x4f,
1461 .clk_divisor_fast_mode = 0x3c,
1462 .clk_divisor_fast_plus_mode = 0x16,
1463 .has_config_load_reg = true,
925 .has_multi_master_mode = true, 1464 .has_multi_master_mode = true,
926 .has_slcg_override_reg = true, 1465 .has_slcg_override_reg = true,
927 .has_mst_fifo = true, 1466 .has_mst_fifo = true,
928 .quirks = &tegra194_i2c_quirks, 1467 .quirks = &tegra194_i2c_quirks,
1468 .supports_bus_clear = true,
1469 .has_apb_dma = false,
1470 .tlow_std_mode = 0x8,
1471 .thigh_std_mode = 0x7,
1472 .tlow_fast_fastplus_mode = 0x2,
1473 .thigh_fast_fastplus_mode = 0x2,
1474 .setup_hold_time_std_mode = 0x08080808,
1475 .setup_hold_time_fast_fast_plus_mode = 0x02020202,
1476 .setup_hold_time_hs_mode = 0x090909,
1477 .has_interface_timing_reg = true,
929}; 1478};
930 1479
931/* Match table for of_platform binding */ 1480/* Match table for of_platform binding */
932static const struct of_device_id tegra_i2c_of_match[] = { 1481static const struct of_device_id tegra_i2c_of_match[] = {
933 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, }, 1482 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1483 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
934 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, }, 1484 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
935 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, }, 1485 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
936 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, 1486 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
@@ -948,11 +1498,12 @@ static int tegra_i2c_probe(struct platform_device *pdev)
948 struct clk *div_clk; 1498 struct clk *div_clk;
949 struct clk *fast_clk; 1499 struct clk *fast_clk;
950 void __iomem *base; 1500 void __iomem *base;
1501 phys_addr_t base_phys;
951 int irq; 1502 int irq;
952 int ret = 0; 1503 int ret = 0;
953 int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
954 1504
955 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1505 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1506 base_phys = res->start;
956 base = devm_ioremap_resource(&pdev->dev, res); 1507 base = devm_ioremap_resource(&pdev->dev, res);
957 if (IS_ERR(base)) 1508 if (IS_ERR(base))
958 return PTR_ERR(base); 1509 return PTR_ERR(base);
@@ -975,8 +1526,11 @@ static int tegra_i2c_probe(struct platform_device *pdev)
975 return -ENOMEM; 1526 return -ENOMEM;
976 1527
977 i2c_dev->base = base; 1528 i2c_dev->base = base;
1529 i2c_dev->base_phys = base_phys;
978 i2c_dev->div_clk = div_clk; 1530 i2c_dev->div_clk = div_clk;
979 i2c_dev->adapter.algo = &tegra_i2c_algo; 1531 i2c_dev->adapter.algo = &tegra_i2c_algo;
1532 i2c_dev->adapter.retries = 1;
1533 i2c_dev->adapter.timeout = 6 * HZ;
980 i2c_dev->irq = irq; 1534 i2c_dev->irq = irq;
981 i2c_dev->cont_id = pdev->id; 1535 i2c_dev->cont_id = pdev->id;
982 i2c_dev->dev = &pdev->dev; 1536 i2c_dev->dev = &pdev->dev;
@@ -993,7 +1547,10 @@ static int tegra_i2c_probe(struct platform_device *pdev)
993 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, 1547 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
994 "nvidia,tegra20-i2c-dvc"); 1548 "nvidia,tegra20-i2c-dvc");
995 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; 1549 i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
1550 i2c_dev->dma_buf_size = i2c_dev->adapter.quirks->max_write_len +
1551 I2C_PACKET_HEADER_SIZE;
996 init_completion(&i2c_dev->msg_complete); 1552 init_completion(&i2c_dev->msg_complete);
1553 init_completion(&i2c_dev->dma_complete);
997 spin_lock_init(&i2c_dev->xfer_lock); 1554 spin_lock_init(&i2c_dev->xfer_lock);
998 1555
999 if (!i2c_dev->hw->has_single_clk_source) { 1556 if (!i2c_dev->hw->has_single_clk_source) {
@@ -1015,20 +1572,17 @@ static int tegra_i2c_probe(struct platform_device *pdev)
1015 } 1572 }
1016 } 1573 }
1017 1574
1018 i2c_dev->clk_divisor_non_hs_mode = 1575 if (i2c_dev->bus_clk_rate > I2C_FAST_MODE &&
1019 i2c_dev->hw->clk_divisor_std_fast_mode; 1576 i2c_dev->bus_clk_rate <= I2C_FAST_PLUS_MODE)
1020 if (i2c_dev->hw->clk_divisor_fast_plus_mode &&
1021 (i2c_dev->bus_clk_rate == 1000000))
1022 i2c_dev->clk_divisor_non_hs_mode = 1577 i2c_dev->clk_divisor_non_hs_mode =
1023 i2c_dev->hw->clk_divisor_fast_plus_mode; 1578 i2c_dev->hw->clk_divisor_fast_plus_mode;
1024 1579 else if (i2c_dev->bus_clk_rate > I2C_STANDARD_MODE &&
1025 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1); 1580 i2c_dev->bus_clk_rate <= I2C_FAST_MODE)
1026 ret = clk_set_rate(i2c_dev->div_clk, 1581 i2c_dev->clk_divisor_non_hs_mode =
1027 i2c_dev->bus_clk_rate * clk_multiplier); 1582 i2c_dev->hw->clk_divisor_fast_mode;
1028 if (ret) { 1583 else
1029 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret); 1584 i2c_dev->clk_divisor_non_hs_mode =
1030 goto unprepare_fast_clk; 1585 i2c_dev->hw->clk_divisor_std_mode;
1031 }
1032 1586
1033 ret = clk_prepare(i2c_dev->div_clk); 1587 ret = clk_prepare(i2c_dev->div_clk);
1034 if (ret < 0) { 1588 if (ret < 0) {
@@ -1054,17 +1608,24 @@ static int tegra_i2c_probe(struct platform_device *pdev)
1054 } 1608 }
1055 } 1609 }
1056 1610
1057 ret = tegra_i2c_init(i2c_dev); 1611 if (i2c_dev->hw->supports_bus_clear)
1612 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
1613
1614 ret = tegra_i2c_init_dma(i2c_dev);
1615 if (ret < 0)
1616 goto disable_div_clk;
1617
1618 ret = tegra_i2c_init(i2c_dev, false);
1058 if (ret) { 1619 if (ret) {
1059 dev_err(&pdev->dev, "Failed to initialize i2c controller\n"); 1620 dev_err(&pdev->dev, "Failed to initialize i2c controller\n");
1060 goto disable_div_clk; 1621 goto release_dma;
1061 } 1622 }
1062 1623
1063 ret = devm_request_irq(&pdev->dev, i2c_dev->irq, 1624 ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
1064 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev); 1625 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
1065 if (ret) { 1626 if (ret) {
1066 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); 1627 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
1067 goto disable_div_clk; 1628 goto release_dma;
1068 } 1629 }
1069 1630
1070 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 1631 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
@@ -1078,10 +1639,13 @@ static int tegra_i2c_probe(struct platform_device *pdev)
1078 1639
1079 ret = i2c_add_numbered_adapter(&i2c_dev->adapter); 1640 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
1080 if (ret) 1641 if (ret)
1081 goto disable_div_clk; 1642 goto release_dma;
1082 1643
1083 return 0; 1644 return 0;
1084 1645
1646release_dma:
1647 tegra_i2c_release_dma(i2c_dev);
1648
1085disable_div_clk: 1649disable_div_clk:
1086 if (i2c_dev->is_multimaster_mode) 1650 if (i2c_dev->is_multimaster_mode)
1087 clk_disable(i2c_dev->div_clk); 1651 clk_disable(i2c_dev->div_clk);
@@ -1118,6 +1682,7 @@ static int tegra_i2c_remove(struct platform_device *pdev)
1118 if (!i2c_dev->hw->has_single_clk_source) 1682 if (!i2c_dev->hw->has_single_clk_source)
1119 clk_unprepare(i2c_dev->fast_clk); 1683 clk_unprepare(i2c_dev->fast_clk);
1120 1684
1685 tegra_i2c_release_dma(i2c_dev);
1121 return 0; 1686 return 0;
1122} 1687}
1123 1688
@@ -1141,18 +1706,7 @@ static struct platform_driver tegra_i2c_driver = {
1141 }, 1706 },
1142}; 1707};
1143 1708
1144static int __init tegra_i2c_init_driver(void) 1709module_platform_driver(tegra_i2c_driver);
1145{
1146 return platform_driver_register(&tegra_i2c_driver);
1147}
1148
1149static void __exit tegra_i2c_exit_driver(void)
1150{
1151 platform_driver_unregister(&tegra_i2c_driver);
1152}
1153
1154subsys_initcall(tegra_i2c_init_driver);
1155module_exit(tegra_i2c_exit_driver);
1156 1710
1157MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver"); 1711MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1158MODULE_AUTHOR("Colin Cross"); 1712MODULE_AUTHOR("Colin Cross");
diff --git a/drivers/i2c/busses/i2c-zx2967.c b/drivers/i2c/busses/i2c-zx2967.c
index b8f9e020d80e..7b98d97da3c6 100644
--- a/drivers/i2c/busses/i2c-zx2967.c
+++ b/drivers/i2c/busses/i2c-zx2967.c
@@ -66,7 +66,6 @@ struct zx2967_i2c {
66 int msg_rd; 66 int msg_rd;
67 u8 *cur_trans; 67 u8 *cur_trans;
68 u8 access_cnt; 68 u8 access_cnt;
69 bool is_suspended;
70 int error; 69 int error;
71}; 70};
72 71
@@ -313,9 +312,6 @@ static int zx2967_i2c_xfer(struct i2c_adapter *adap,
313 int ret; 312 int ret;
314 int i; 313 int i;
315 314
316 if (i2c->is_suspended)
317 return -EBUSY;
318
319 zx2967_set_addr(i2c, msgs->addr); 315 zx2967_set_addr(i2c, msgs->addr);
320 316
321 for (i = 0; i < num; i++) { 317 for (i = 0; i < num; i++) {
@@ -470,7 +466,7 @@ static int __maybe_unused zx2967_i2c_suspend(struct device *dev)
470{ 466{
471 struct zx2967_i2c *i2c = dev_get_drvdata(dev); 467 struct zx2967_i2c *i2c = dev_get_drvdata(dev);
472 468
473 i2c->is_suspended = true; 469 i2c_mark_adapter_suspended(&i2c->adap);
474 clk_disable_unprepare(i2c->clk); 470 clk_disable_unprepare(i2c->clk);
475 471
476 return 0; 472 return 0;
@@ -480,8 +476,8 @@ static int __maybe_unused zx2967_i2c_resume(struct device *dev)
480{ 476{
481 struct zx2967_i2c *i2c = dev_get_drvdata(dev); 477 struct zx2967_i2c *i2c = dev_get_drvdata(dev);
482 478
483 i2c->is_suspended = false;
484 clk_prepare_enable(i2c->clk); 479 clk_prepare_enable(i2c->clk);
480 i2c_mark_adapter_resumed(&i2c->adap);
485 481
486 return 0; 482 return 0;
487} 483}
diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
index 28460f6a60cc..cb6c5cb0df0b 100644
--- a/drivers/i2c/i2c-core-base.c
+++ b/drivers/i2c/i2c-core-base.c
@@ -430,7 +430,7 @@ static int i2c_device_remove(struct device *dev)
430 dev_pm_clear_wake_irq(&client->dev); 430 dev_pm_clear_wake_irq(&client->dev);
431 device_init_wakeup(&client->dev, false); 431 device_init_wakeup(&client->dev, false);
432 432
433 client->irq = 0; 433 client->irq = client->init_irq;
434 434
435 return status; 435 return status;
436} 436}
@@ -741,10 +741,11 @@ i2c_new_device(struct i2c_adapter *adap, struct i2c_board_info const *info)
741 client->flags = info->flags; 741 client->flags = info->flags;
742 client->addr = info->addr; 742 client->addr = info->addr;
743 743
744 client->irq = info->irq; 744 client->init_irq = info->irq;
745 if (!client->irq) 745 if (!client->init_irq)
746 client->irq = i2c_dev_irq_from_resources(info->resources, 746 client->init_irq = i2c_dev_irq_from_resources(info->resources,
747 info->num_resources); 747 info->num_resources);
748 client->irq = client->init_irq;
748 749
749 strlcpy(client->name, info->type, sizeof(client->name)); 750 strlcpy(client->name, info->type, sizeof(client->name));
750 751
@@ -1232,6 +1233,7 @@ static int i2c_register_adapter(struct i2c_adapter *adap)
1232 if (!adap->lock_ops) 1233 if (!adap->lock_ops)
1233 adap->lock_ops = &i2c_adapter_lock_ops; 1234 adap->lock_ops = &i2c_adapter_lock_ops;
1234 1235
1236 adap->locked_flags = 0;
1235 rt_mutex_init(&adap->bus_lock); 1237 rt_mutex_init(&adap->bus_lock);
1236 rt_mutex_init(&adap->mux_lock); 1238 rt_mutex_init(&adap->mux_lock);
1237 mutex_init(&adap->userspace_clients_lock); 1239 mutex_init(&adap->userspace_clients_lock);
@@ -1865,6 +1867,8 @@ int __i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
1865 1867
1866 if (WARN_ON(!msgs || num < 1)) 1868 if (WARN_ON(!msgs || num < 1))
1867 return -EINVAL; 1869 return -EINVAL;
1870 if (WARN_ON(test_bit(I2C_ALF_IS_SUSPENDED, &adap->locked_flags)))
1871 return -ESHUTDOWN;
1868 1872
1869 if (adap->quirks && i2c_check_for_quirks(adap, msgs, num)) 1873 if (adap->quirks && i2c_check_for_quirks(adap, msgs, num))
1870 return -EOPNOTSUPP; 1874 return -EOPNOTSUPP;
diff --git a/drivers/i2c/i2c-core-of.c b/drivers/i2c/i2c-core-of.c
index 6cb7ad608bcd..0f01cdba9d2c 100644
--- a/drivers/i2c/i2c-core-of.c
+++ b/drivers/i2c/i2c-core-of.c
@@ -121,6 +121,17 @@ static int of_dev_node_match(struct device *dev, void *data)
121 return dev->of_node == data; 121 return dev->of_node == data;
122} 122}
123 123
124static int of_dev_or_parent_node_match(struct device *dev, void *data)
125{
126 if (dev->of_node == data)
127 return 1;
128
129 if (dev->parent)
130 return dev->parent->of_node == data;
131
132 return 0;
133}
134
124/* must call put_device() when done with returned i2c_client device */ 135/* must call put_device() when done with returned i2c_client device */
125struct i2c_client *of_find_i2c_device_by_node(struct device_node *node) 136struct i2c_client *of_find_i2c_device_by_node(struct device_node *node)
126{ 137{
@@ -145,7 +156,8 @@ struct i2c_adapter *of_find_i2c_adapter_by_node(struct device_node *node)
145 struct device *dev; 156 struct device *dev;
146 struct i2c_adapter *adapter; 157 struct i2c_adapter *adapter;
147 158
148 dev = bus_find_device(&i2c_bus_type, NULL, node, of_dev_node_match); 159 dev = bus_find_device(&i2c_bus_type, NULL, node,
160 of_dev_or_parent_node_match);
149 if (!dev) 161 if (!dev)
150 return NULL; 162 return NULL;
151 163
diff --git a/drivers/i2c/i2c-core-smbus.c b/drivers/i2c/i2c-core-smbus.c
index 9cd66cabb84f..132119112596 100644
--- a/drivers/i2c/i2c-core-smbus.c
+++ b/drivers/i2c/i2c-core-smbus.c
@@ -585,7 +585,7 @@ s32 __i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
585trace: 585trace:
586 /* If enabled, the reply tracepoint is conditional on read_write. */ 586 /* If enabled, the reply tracepoint is conditional on read_write. */
587 trace_smbus_reply(adapter, addr, flags, read_write, 587 trace_smbus_reply(adapter, addr, flags, read_write,
588 command, protocol, data); 588 command, protocol, data, res);
589 trace_smbus_result(adapter, addr, flags, read_write, 589 trace_smbus_result(adapter, addr, flags, read_write,
590 command, protocol, res); 590 command, protocol, res);
591 591
diff --git a/drivers/i2c/i2c-dev.c b/drivers/i2c/i2c-dev.c
index ccd76c71af09..3f7b9af11137 100644
--- a/drivers/i2c/i2c-dev.c
+++ b/drivers/i2c/i2c-dev.c
@@ -52,7 +52,7 @@ struct i2c_dev {
52 struct cdev cdev; 52 struct cdev cdev;
53}; 53};
54 54
55#define I2C_MINORS MINORMASK 55#define I2C_MINORS (MINORMASK + 1)
56static LIST_HEAD(i2c_dev_list); 56static LIST_HEAD(i2c_dev_list);
57static DEFINE_SPINLOCK(i2c_dev_list_lock); 57static DEFINE_SPINLOCK(i2c_dev_list_lock);
58 58
diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c
index ddfcf4ade7bf..63aa541c9608 100644
--- a/drivers/misc/eeprom/at24.c
+++ b/drivers/misc/eeprom/at24.c
@@ -22,10 +22,24 @@
22#include <linux/i2c.h> 22#include <linux/i2c.h>
23#include <linux/nvmem-provider.h> 23#include <linux/nvmem-provider.h>
24#include <linux/regmap.h> 24#include <linux/regmap.h>
25#include <linux/platform_data/at24.h>
26#include <linux/pm_runtime.h> 25#include <linux/pm_runtime.h>
27#include <linux/gpio/consumer.h> 26#include <linux/gpio/consumer.h>
28 27
28/* Address pointer is 16 bit. */
29#define AT24_FLAG_ADDR16 BIT(7)
30/* sysfs-entry will be read-only. */
31#define AT24_FLAG_READONLY BIT(6)
32/* sysfs-entry will be world-readable. */
33#define AT24_FLAG_IRUGO BIT(5)
34/* Take always 8 addresses (24c00). */
35#define AT24_FLAG_TAKE8ADDR BIT(4)
36/* Factory-programmed serial number. */
37#define AT24_FLAG_SERIAL BIT(3)
38/* Factory-programmed mac address. */
39#define AT24_FLAG_MAC BIT(2)
40/* Does not auto-rollover reads to the next slave address. */
41#define AT24_FLAG_NO_RDROL BIT(1)
42
29/* 43/*
30 * I2C EEPROMs from most vendors are inexpensive and mostly interchangeable. 44 * I2C EEPROMs from most vendors are inexpensive and mostly interchangeable.
31 * Differences between different vendor product lines (like Atmel AT24C or 45 * Differences between different vendor product lines (like Atmel AT24C or
@@ -107,10 +121,6 @@ module_param_named(write_timeout, at24_write_timeout, uint, 0);
107MODULE_PARM_DESC(at24_write_timeout, "Time (in ms) to try writes (default 25)"); 121MODULE_PARM_DESC(at24_write_timeout, "Time (in ms) to try writes (default 25)");
108 122
109struct at24_chip_data { 123struct at24_chip_data {
110 /*
111 * these fields mirror their equivalents in
112 * struct at24_platform_data
113 */
114 u32 byte_len; 124 u32 byte_len;
115 u8 flags; 125 u8 flags;
116}; 126};
@@ -471,63 +481,11 @@ static int at24_write(void *priv, unsigned int off, void *val, size_t count)
471 return 0; 481 return 0;
472} 482}
473 483
474static void at24_properties_to_pdata(struct device *dev, 484static const struct at24_chip_data *at24_get_chip_data(struct device *dev)
475 struct at24_platform_data *chip)
476{
477 int err;
478 u32 val;
479
480 if (device_property_present(dev, "read-only"))
481 chip->flags |= AT24_FLAG_READONLY;
482 if (device_property_present(dev, "no-read-rollover"))
483 chip->flags |= AT24_FLAG_NO_RDROL;
484
485 err = device_property_read_u32(dev, "address-width", &val);
486 if (!err) {
487 switch (val) {
488 case 8:
489 if (chip->flags & AT24_FLAG_ADDR16)
490 dev_warn(dev, "Override address width to be 8, while default is 16\n");
491 chip->flags &= ~AT24_FLAG_ADDR16;
492 break;
493 case 16:
494 chip->flags |= AT24_FLAG_ADDR16;
495 break;
496 default:
497 dev_warn(dev, "Bad \"address-width\" property: %u\n",
498 val);
499 }
500 }
501
502 err = device_property_read_u32(dev, "size", &val);
503 if (!err)
504 chip->byte_len = val;
505
506 err = device_property_read_u32(dev, "pagesize", &val);
507 if (!err) {
508 chip->page_size = val;
509 } else {
510 /*
511 * This is slow, but we can't know all eeproms, so we better
512 * play safe. Specifying custom eeprom-types via platform_data
513 * is recommended anyhow.
514 */
515 chip->page_size = 1;
516 }
517}
518
519static int at24_get_pdata(struct device *dev, struct at24_platform_data *pdata)
520{ 485{
521 struct device_node *of_node = dev->of_node; 486 struct device_node *of_node = dev->of_node;
522 const struct at24_chip_data *cdata; 487 const struct at24_chip_data *cdata;
523 const struct i2c_device_id *id; 488 const struct i2c_device_id *id;
524 struct at24_platform_data *pd;
525
526 pd = dev_get_platdata(dev);
527 if (pd) {
528 memcpy(pdata, pd, sizeof(*pdata));
529 return 0;
530 }
531 489
532 id = i2c_match_id(at24_ids, to_i2c_client(dev)); 490 id = i2c_match_id(at24_ids, to_i2c_client(dev));
533 491
@@ -544,13 +502,9 @@ static int at24_get_pdata(struct device *dev, struct at24_platform_data *pdata)
544 cdata = acpi_device_get_match_data(dev); 502 cdata = acpi_device_get_match_data(dev);
545 503
546 if (!cdata) 504 if (!cdata)
547 return -ENODEV; 505 return ERR_PTR(-ENODEV);
548 506
549 pdata->byte_len = cdata->byte_len; 507 return cdata;
550 pdata->flags = cdata->flags;
551 at24_properties_to_pdata(dev, pdata);
552
553 return 0;
554} 508}
555 509
556static void at24_remove_dummy_clients(struct at24_data *at24) 510static void at24_remove_dummy_clients(struct at24_data *at24)
@@ -619,7 +573,8 @@ static int at24_probe(struct i2c_client *client)
619{ 573{
620 struct regmap_config regmap_config = { }; 574 struct regmap_config regmap_config = { };
621 struct nvmem_config nvmem_config = { }; 575 struct nvmem_config nvmem_config = { };
622 struct at24_platform_data pdata = { }; 576 u32 byte_len, page_size, flags, addrw;
577 const struct at24_chip_data *cdata;
623 struct device *dev = &client->dev; 578 struct device *dev = &client->dev;
624 bool i2c_fn_i2c, i2c_fn_block; 579 bool i2c_fn_i2c, i2c_fn_block;
625 unsigned int i, num_addresses; 580 unsigned int i, num_addresses;
@@ -634,35 +589,75 @@ static int at24_probe(struct i2c_client *client)
634 i2c_fn_block = i2c_check_functionality(client->adapter, 589 i2c_fn_block = i2c_check_functionality(client->adapter,
635 I2C_FUNC_SMBUS_WRITE_I2C_BLOCK); 590 I2C_FUNC_SMBUS_WRITE_I2C_BLOCK);
636 591
637 err = at24_get_pdata(dev, &pdata); 592 cdata = at24_get_chip_data(dev);
593 if (IS_ERR(cdata))
594 return PTR_ERR(cdata);
595
596 err = device_property_read_u32(dev, "pagesize", &page_size);
597 if (err)
598 /*
599 * This is slow, but we can't know all eeproms, so we better
600 * play safe. Specifying custom eeprom-types via platform_data
601 * is recommended anyhow.
602 */
603 page_size = 1;
604
605 flags = cdata->flags;
606 if (device_property_present(dev, "read-only"))
607 flags |= AT24_FLAG_READONLY;
608 if (device_property_present(dev, "no-read-rollover"))
609 flags |= AT24_FLAG_NO_RDROL;
610
611 err = device_property_read_u32(dev, "address-width", &addrw);
612 if (!err) {
613 switch (addrw) {
614 case 8:
615 if (flags & AT24_FLAG_ADDR16)
616 dev_warn(dev,
617 "Override address width to be 8, while default is 16\n");
618 flags &= ~AT24_FLAG_ADDR16;
619 break;
620 case 16:
621 flags |= AT24_FLAG_ADDR16;
622 break;
623 default:
624 dev_warn(dev, "Bad \"address-width\" property: %u\n",
625 addrw);
626 }
627 }
628
629 err = device_property_read_u32(dev, "size", &byte_len);
638 if (err) 630 if (err)
639 return err; 631 byte_len = cdata->byte_len;
640 632
641 if (!i2c_fn_i2c && !i2c_fn_block) 633 if (!i2c_fn_i2c && !i2c_fn_block)
642 pdata.page_size = 1; 634 page_size = 1;
643 635
644 if (!pdata.page_size) { 636 if (!page_size) {
645 dev_err(dev, "page_size must not be 0!\n"); 637 dev_err(dev, "page_size must not be 0!\n");
646 return -EINVAL; 638 return -EINVAL;
647 } 639 }
648 640
649 if (!is_power_of_2(pdata.page_size)) 641 if (!is_power_of_2(page_size))
650 dev_warn(dev, "page_size looks suspicious (no power of 2)!\n"); 642 dev_warn(dev, "page_size looks suspicious (no power of 2)!\n");
651 643
652 if (pdata.flags & AT24_FLAG_TAKE8ADDR) 644 err = device_property_read_u32(dev, "num-addresses", &num_addresses);
653 num_addresses = 8; 645 if (err) {
654 else 646 if (flags & AT24_FLAG_TAKE8ADDR)
655 num_addresses = DIV_ROUND_UP(pdata.byte_len, 647 num_addresses = 8;
656 (pdata.flags & AT24_FLAG_ADDR16) ? 65536 : 256); 648 else
649 num_addresses = DIV_ROUND_UP(byte_len,
650 (flags & AT24_FLAG_ADDR16) ? 65536 : 256);
651 }
657 652
658 if ((pdata.flags & AT24_FLAG_SERIAL) && (pdata.flags & AT24_FLAG_MAC)) { 653 if ((flags & AT24_FLAG_SERIAL) && (flags & AT24_FLAG_MAC)) {
659 dev_err(dev, 654 dev_err(dev,
660 "invalid device data - cannot have both AT24_FLAG_SERIAL & AT24_FLAG_MAC."); 655 "invalid device data - cannot have both AT24_FLAG_SERIAL & AT24_FLAG_MAC.");
661 return -EINVAL; 656 return -EINVAL;
662 } 657 }
663 658
664 regmap_config.val_bits = 8; 659 regmap_config.val_bits = 8;
665 regmap_config.reg_bits = (pdata.flags & AT24_FLAG_ADDR16) ? 16 : 8; 660 regmap_config.reg_bits = (flags & AT24_FLAG_ADDR16) ? 16 : 8;
666 regmap_config.disable_locking = true; 661 regmap_config.disable_locking = true;
667 662
668 regmap = devm_regmap_init_i2c(client, &regmap_config); 663 regmap = devm_regmap_init_i2c(client, &regmap_config);
@@ -675,11 +670,11 @@ static int at24_probe(struct i2c_client *client)
675 return -ENOMEM; 670 return -ENOMEM;
676 671
677 mutex_init(&at24->lock); 672 mutex_init(&at24->lock);
678 at24->byte_len = pdata.byte_len; 673 at24->byte_len = byte_len;
679 at24->page_size = pdata.page_size; 674 at24->page_size = page_size;
680 at24->flags = pdata.flags; 675 at24->flags = flags;
681 at24->num_addresses = num_addresses; 676 at24->num_addresses = num_addresses;
682 at24->offset_adj = at24_get_offset_adj(pdata.flags, pdata.byte_len); 677 at24->offset_adj = at24_get_offset_adj(flags, byte_len);
683 at24->client[0].client = client; 678 at24->client[0].client = client;
684 at24->client[0].regmap = regmap; 679 at24->client[0].regmap = regmap;
685 680
@@ -687,10 +682,10 @@ static int at24_probe(struct i2c_client *client)
687 if (IS_ERR(at24->wp_gpio)) 682 if (IS_ERR(at24->wp_gpio))
688 return PTR_ERR(at24->wp_gpio); 683 return PTR_ERR(at24->wp_gpio);
689 684
690 writable = !(pdata.flags & AT24_FLAG_READONLY); 685 writable = !(flags & AT24_FLAG_READONLY);
691 if (writable) { 686 if (writable) {
692 at24->write_max = min_t(unsigned int, 687 at24->write_max = min_t(unsigned int,
693 pdata.page_size, at24_io_limit); 688 page_size, at24_io_limit);
694 if (!i2c_fn_i2c && at24->write_max > I2C_SMBUS_BLOCK_MAX) 689 if (!i2c_fn_i2c && at24->write_max > I2C_SMBUS_BLOCK_MAX)
695 at24->write_max = I2C_SMBUS_BLOCK_MAX; 690 at24->write_max = I2C_SMBUS_BLOCK_MAX;
696 } 691 }
@@ -733,7 +728,7 @@ static int at24_probe(struct i2c_client *client)
733 nvmem_config.priv = at24; 728 nvmem_config.priv = at24;
734 nvmem_config.stride = 1; 729 nvmem_config.stride = 1;
735 nvmem_config.word_size = 1; 730 nvmem_config.word_size = 1;
736 nvmem_config.size = pdata.byte_len; 731 nvmem_config.size = byte_len;
737 732
738 at24->nvmem = devm_nvmem_register(dev, &nvmem_config); 733 at24->nvmem = devm_nvmem_register(dev, &nvmem_config);
739 if (IS_ERR(at24->nvmem)) { 734 if (IS_ERR(at24->nvmem)) {
@@ -742,13 +737,9 @@ static int at24_probe(struct i2c_client *client)
742 } 737 }
743 738
744 dev_info(dev, "%u byte %s EEPROM, %s, %u bytes/write\n", 739 dev_info(dev, "%u byte %s EEPROM, %s, %u bytes/write\n",
745 pdata.byte_len, client->name, 740 byte_len, client->name,
746 writable ? "writable" : "read-only", at24->write_max); 741 writable ? "writable" : "read-only", at24->write_max);
747 742
748 /* export data to kernel code */
749 if (pdata.setup)
750 pdata.setup(at24->nvmem, pdata.context);
751
752 return 0; 743 return 0;
753 744
754err_clients: 745err_clients:
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index dca5f244d63d..6ac47f5ea514 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -1061,17 +1061,6 @@ static inline int acpi_dev_gpio_irq_get(struct acpi_device *adev, int index)
1061} 1061}
1062#endif 1062#endif
1063 1063
1064#if defined(CONFIG_ACPI) && IS_ENABLED(CONFIG_I2C)
1065bool i2c_acpi_get_i2c_resource(struct acpi_resource *ares,
1066 struct acpi_resource_i2c_serialbus **i2c);
1067#else
1068static inline bool i2c_acpi_get_i2c_resource(struct acpi_resource *ares,
1069 struct acpi_resource_i2c_serialbus **i2c)
1070{
1071 return false;
1072}
1073#endif
1074
1075/* Device properties */ 1064/* Device properties */
1076 1065
1077#ifdef CONFIG_ACPI 1066#ifdef CONFIG_ACPI
diff --git a/include/linux/i2c-algo-bit.h b/include/linux/i2c-algo-bit.h
index 63904ba6887e..69045df78e2d 100644
--- a/include/linux/i2c-algo-bit.h
+++ b/include/linux/i2c-algo-bit.h
@@ -1,30 +1,17 @@
1/* ------------------------------------------------------------------------- */ 1/* SPDX-License-Identifier: GPL-2.0+ */
2/* i2c-algo-bit.h i2c driver algorithms for bit-shift adapters */ 2/*
3/* ------------------------------------------------------------------------- */ 3 * i2c-algo-bit.h: i2c driver algorithms for bit-shift adapters
4/* Copyright (C) 1995-99 Simon G. Vogl 4 *
5 5 * Copyright (C) 1995-99 Simon G. Vogl
6 This program is free software; you can redistribute it and/or modify 6 * With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even
7 it under the terms of the GNU General Public License as published by 7 * Frodo Looijaard <frodol@dds.nl>
8 the Free Software Foundation; either version 2 of the License, or 8 */
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 MA 02110-1301 USA. */
20/* ------------------------------------------------------------------------- */
21
22/* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even
23 Frodo Looijaard <frodol@dds.nl> */
24 9
25#ifndef _LINUX_I2C_ALGO_BIT_H 10#ifndef _LINUX_I2C_ALGO_BIT_H
26#define _LINUX_I2C_ALGO_BIT_H 11#define _LINUX_I2C_ALGO_BIT_H
27 12
13#include <linux/i2c.h>
14
28/* --- Defines for bit-adapters --------------------------------------- */ 15/* --- Defines for bit-adapters --------------------------------------- */
29/* 16/*
30 * This struct contains the hw-dependent functions of bit-style adapters to 17 * This struct contains the hw-dependent functions of bit-style adapters to
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 65b4eaed1d96..383510b4f083 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -333,6 +333,7 @@ struct i2c_client {
333 char name[I2C_NAME_SIZE]; 333 char name[I2C_NAME_SIZE];
334 struct i2c_adapter *adapter; /* the adapter we sit on */ 334 struct i2c_adapter *adapter; /* the adapter we sit on */
335 struct device dev; /* the device structure */ 335 struct device dev; /* the device structure */
336 int init_irq; /* irq set at initialization */
336 int irq; /* irq issued by device */ 337 int irq; /* irq issued by device */
337 struct list_head detected; 338 struct list_head detected;
338#if IS_ENABLED(CONFIG_I2C_SLAVE) 339#if IS_ENABLED(CONFIG_I2C_SLAVE)
@@ -680,6 +681,8 @@ struct i2c_adapter {
680 int timeout; /* in jiffies */ 681 int timeout; /* in jiffies */
681 int retries; 682 int retries;
682 struct device dev; /* the adapter device */ 683 struct device dev; /* the adapter device */
684 unsigned long locked_flags; /* owned by the I2C core */
685#define I2C_ALF_IS_SUSPENDED 0
683 686
684 int nr; 687 int nr;
685 char name[48]; 688 char name[48];
@@ -762,6 +765,38 @@ i2c_unlock_bus(struct i2c_adapter *adapter, unsigned int flags)
762 adapter->lock_ops->unlock_bus(adapter, flags); 765 adapter->lock_ops->unlock_bus(adapter, flags);
763} 766}
764 767
768/**
769 * i2c_mark_adapter_suspended - Report suspended state of the adapter to the core
770 * @adap: Adapter to mark as suspended
771 *
772 * When using this helper to mark an adapter as suspended, the core will reject
773 * further transfers to this adapter. The usage of this helper is optional but
774 * recommended for devices having distinct handlers for system suspend and
775 * runtime suspend. More complex devices are free to implement custom solutions
776 * to reject transfers when suspended.
777 */
778static inline void i2c_mark_adapter_suspended(struct i2c_adapter *adap)
779{
780 i2c_lock_bus(adap, I2C_LOCK_ROOT_ADAPTER);
781 set_bit(I2C_ALF_IS_SUSPENDED, &adap->locked_flags);
782 i2c_unlock_bus(adap, I2C_LOCK_ROOT_ADAPTER);
783}
784
785/**
786 * i2c_mark_adapter_resumed - Report resumed state of the adapter to the core
787 * @adap: Adapter to mark as resumed
788 *
789 * When using this helper to mark an adapter as resumed, the core will allow
790 * further transfers to this adapter. See also further notes to
791 * @i2c_mark_adapter_suspended().
792 */
793static inline void i2c_mark_adapter_resumed(struct i2c_adapter *adap)
794{
795 i2c_lock_bus(adap, I2C_LOCK_ROOT_ADAPTER);
796 clear_bit(I2C_ALF_IS_SUSPENDED, &adap->locked_flags);
797 i2c_unlock_bus(adap, I2C_LOCK_ROOT_ADAPTER);
798}
799
765/*flags for the client struct: */ 800/*flags for the client struct: */
766#define I2C_CLIENT_PEC 0x04 /* Use Packet Error Checking */ 801#define I2C_CLIENT_PEC 0x04 /* Use Packet Error Checking */
767#define I2C_CLIENT_TEN 0x10 /* we have a ten bit chip address */ 802#define I2C_CLIENT_TEN 0x10 /* we have a ten bit chip address */
@@ -933,11 +968,21 @@ static inline int of_i2c_get_board_info(struct device *dev,
933 968
934#endif /* CONFIG_OF */ 969#endif /* CONFIG_OF */
935 970
971struct acpi_resource;
972struct acpi_resource_i2c_serialbus;
973
936#if IS_ENABLED(CONFIG_ACPI) 974#if IS_ENABLED(CONFIG_ACPI)
975bool i2c_acpi_get_i2c_resource(struct acpi_resource *ares,
976 struct acpi_resource_i2c_serialbus **i2c);
937u32 i2c_acpi_find_bus_speed(struct device *dev); 977u32 i2c_acpi_find_bus_speed(struct device *dev);
938struct i2c_client *i2c_acpi_new_device(struct device *dev, int index, 978struct i2c_client *i2c_acpi_new_device(struct device *dev, int index,
939 struct i2c_board_info *info); 979 struct i2c_board_info *info);
940#else 980#else
981static inline bool i2c_acpi_get_i2c_resource(struct acpi_resource *ares,
982 struct acpi_resource_i2c_serialbus **i2c)
983{
984 return false;
985}
941static inline u32 i2c_acpi_find_bus_speed(struct device *dev) 986static inline u32 i2c_acpi_find_bus_speed(struct device *dev)
942{ 987{
943 return 0; 988 return 0;
diff --git a/include/linux/platform_data/at24.h b/include/linux/platform_data/at24.h
deleted file mode 100644
index 63507ff464ee..000000000000
--- a/include/linux/platform_data/at24.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * at24.h - platform_data for the at24 (generic eeprom) driver
3 * (C) Copyright 2008 by Pengutronix
4 * (C) Copyright 2012 by Wolfram Sang
5 * same license as the driver
6 */
7
8#ifndef _LINUX_AT24_H
9#define _LINUX_AT24_H
10
11#include <linux/types.h>
12#include <linux/nvmem-consumer.h>
13#include <linux/bitops.h>
14
15/**
16 * struct at24_platform_data - data to set up at24 (generic eeprom) driver
17 * @byte_len: size of eeprom in byte
18 * @page_size: number of byte which can be written in one go
19 * @flags: tunable options, check AT24_FLAG_* defines
20 * @setup: an optional callback invoked after eeprom is probed; enables kernel
21 code to access eeprom via nvmem, see example
22 * @context: optional parameter passed to setup()
23 *
24 * If you set up a custom eeprom type, please double-check the parameters.
25 * Especially page_size needs extra care, as you risk data loss if your value
26 * is bigger than what the chip actually supports!
27 *
28 * An example in pseudo code for a setup() callback:
29 *
30 * void get_mac_addr(struct nvmem_device *nvmem, void *context)
31 * {
32 * u8 *mac_addr = ethernet_pdata->mac_addr;
33 * off_t offset = context;
34 *
35 * // Read MAC addr from EEPROM
36 * if (nvmem_device_read(nvmem, offset, ETH_ALEN, mac_addr) == ETH_ALEN)
37 * pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr);
38 * }
39 *
40 * This function pointer and context can now be set up in at24_platform_data.
41 */
42
43struct at24_platform_data {
44 u32 byte_len; /* size (sum of all addr) */
45 u16 page_size; /* for writes */
46 u8 flags;
47#define AT24_FLAG_ADDR16 BIT(7) /* address pointer is 16 bit */
48#define AT24_FLAG_READONLY BIT(6) /* sysfs-entry will be read-only */
49#define AT24_FLAG_IRUGO BIT(5) /* sysfs-entry will be world-readable */
50#define AT24_FLAG_TAKE8ADDR BIT(4) /* take always 8 addresses (24c00) */
51#define AT24_FLAG_SERIAL BIT(3) /* factory-programmed serial number */
52#define AT24_FLAG_MAC BIT(2) /* factory-programmed mac address */
53#define AT24_FLAG_NO_RDROL BIT(1) /* does not auto-rollover reads to */
54 /* the next slave address */
55
56 void (*setup)(struct nvmem_device *nvmem, void *context);
57 void *context;
58};
59
60#endif /* _LINUX_AT24_H */
diff --git a/include/linux/platform_data/i2c-cbus-gpio.h b/include/linux/platform_data/i2c-cbus-gpio.h
deleted file mode 100644
index 6faa992a9502..000000000000
--- a/include/linux/platform_data/i2c-cbus-gpio.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * i2c-cbus-gpio.h - CBUS I2C platform_data definition
3 *
4 * Copyright (C) 2004-2009 Nokia Corporation
5 *
6 * Written by Felipe Balbi and Aaro Koskinen.
7 *
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file "COPYING" in the main directory of this
10 * archive for more details.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#ifndef __INCLUDE_LINUX_I2C_CBUS_GPIO_H
19#define __INCLUDE_LINUX_I2C_CBUS_GPIO_H
20
21struct i2c_cbus_platform_data {
22 int dat_gpio;
23 int clk_gpio;
24 int sel_gpio;
25};
26
27#endif /* __INCLUDE_LINUX_I2C_CBUS_GPIO_H */
diff --git a/include/linux/platform_data/i2c-ocores.h b/include/linux/platform_data/i2c-ocores.h
index 113d6b12f650..e6326cbafe59 100644
--- a/include/linux/platform_data/i2c-ocores.h
+++ b/include/linux/platform_data/i2c-ocores.h
@@ -1,11 +1,8 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * i2c-ocores.h - definitions for the i2c-ocores interface 3 * i2c-ocores.h - definitions for the i2c-ocores interface
3 * 4 *
4 * Peter Korsgaard <peter@korsgaard.com> 5 * Peter Korsgaard <peter@korsgaard.com>
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */ 6 */
10 7
11#ifndef _LINUX_I2C_OCORES_H 8#ifndef _LINUX_I2C_OCORES_H
@@ -15,6 +12,7 @@ struct ocores_i2c_platform_data {
15 u32 reg_shift; /* register offset shift value */ 12 u32 reg_shift; /* register offset shift value */
16 u32 reg_io_width; /* register io read/write width */ 13 u32 reg_io_width; /* register io read/write width */
17 u32 clock_khz; /* input clock in kHz */ 14 u32 clock_khz; /* input clock in kHz */
15 u32 bus_khz; /* bus clock in kHz */
18 bool big_endian; /* registers are big endian */ 16 bool big_endian; /* registers are big endian */
19 u8 num_devices; /* number of devices in the devices list */ 17 u8 num_devices; /* number of devices in the devices list */
20 struct i2c_board_info const *devices; /* devices connected to the bus */ 18 struct i2c_board_info const *devices; /* devices connected to the bus */
diff --git a/include/trace/events/smbus.h b/include/trace/events/smbus.h
index d2fb6e1d3e10..a4892a187842 100644
--- a/include/trace/events/smbus.h
+++ b/include/trace/events/smbus.h
@@ -138,9 +138,9 @@ TRACE_EVENT_CONDITION(smbus_reply,
138 TP_PROTO(const struct i2c_adapter *adap, 138 TP_PROTO(const struct i2c_adapter *adap,
139 u16 addr, unsigned short flags, 139 u16 addr, unsigned short flags,
140 char read_write, u8 command, int protocol, 140 char read_write, u8 command, int protocol,
141 const union i2c_smbus_data *data), 141 const union i2c_smbus_data *data, int res),
142 TP_ARGS(adap, addr, flags, read_write, command, protocol, data), 142 TP_ARGS(adap, addr, flags, read_write, command, protocol, data, res),
143 TP_CONDITION(read_write == I2C_SMBUS_READ), 143 TP_CONDITION(res >= 0 && read_write == I2C_SMBUS_READ),
144 TP_STRUCT__entry( 144 TP_STRUCT__entry(
145 __field(int, adapter_nr ) 145 __field(int, adapter_nr )
146 __field(__u16, addr ) 146 __field(__u16, addr )