14 files changed, 137 insertions, 35 deletions

diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 59dae37f6b8d..b1990dd75f27 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -157,6 +157,7 @@ Ip_u2u1s3(_slti);
 Ip_u2u1s3(_sltiu);
 Ip_u3u1u2(_sltu);
 Ip_u2u1u3(_sra);
+Ip_u3u2u1(_srav);
 Ip_u2u1u3(_srl);
 Ip_u3u2u1(_srlv);
 Ip_u3u1u2(_subu);
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 273ef58f4d43..40fbb5dd66df 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -371,6 +371,7 @@ enum mm_32a_minor_op {
         mm_srl32_op = 0x040,
         mm_srlv32_op = 0x050,
         mm_sra_op = 0x080,
+        mm_srav_op = 0x090,
         mm_rotr_op = 0x0c0,
         mm_lwxs_op = 0x118,
         mm_addu32_op = 0x150,
diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c
index 24e5b0d06899..75ef90486fe6 100644
--- a/arch/mips/mm/uasm-micromips.c
+++ b/arch/mips/mm/uasm-micromips.c
@@ -104,6 +104,7 @@ static const struct insn insn_table_MM[insn_invalid] = {
         [insn_sltiu]    = {M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
         [insn_sltu]     = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD},
         [insn_sra]      = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD},
+        [insn_srav]     = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srav_op), RT | RS | RD},
         [insn_srl]      = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD},
         [insn_srlv]     = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD},
         [insn_rotr]     = {M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD},
diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c
index 60ceb93c71a0..6abe40fc413d 100644
--- a/arch/mips/mm/uasm-mips.c
+++ b/arch/mips/mm/uasm-mips.c
@@ -171,6 +171,7 @@ static const struct insn insn_table[insn_invalid] = {
         [insn_sltiu]    = {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
         [insn_sltu]     = {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD},
         [insn_sra]      = {M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE},
+        [insn_srav]     = {M(spec_op, 0, 0, 0, 0, srav_op), RS | RT | RD},
         [insn_srl]      = {M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE},
         [insn_srlv]     = {M(spec_op, 0, 0, 0, 0, srlv_op),  RS | RT | RD},
         [insn_subu]     = {M(spec_op, 0, 0, 0, 0, subu_op),     RS | RT | RD},
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 57570c0649b4..45b6264ff308 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -61,10 +61,10 @@ enum opcode {
         insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_nor,
         insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb,
         insn_sc, insn_scd, insn_sd, insn_sh, insn_sll, insn_sllv,
-        insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srl,
-        insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp,
-        insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor,
-        insn_xori, insn_yield,
+        insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srav,
+        insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall,
+        insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh,
+        insn_xor, insn_xori, insn_yield,
         insn_invalid /* insn_invalid must be last */
 };
 
@@ -353,6 +353,7 @@ I_u2u1s3(_slti)
 I_u2u1s3(_sltiu)
 I_u3u1u2(_sltu)
 I_u2u1u3(_sra)
+I_u3u2u1(_srav)
 I_u2u1u3(_srl)
 I_u3u2u1(_srlv)
 I_u2u1u3(_rotr)
diff --git a/arch/mips/net/ebpf_jit.c b/arch/mips/net/ebpf_jit.c
index aeb7b1b0f202..b16710a8a9e7 100644
--- a/arch/mips/net/ebpf_jit.c
+++ b/arch/mips/net/ebpf_jit.c
@@ -854,6 +854,7 @@ static int build_one_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
         case BPF_ALU | BPF_MOD | BPF_X: /* ALU_REG */
         case BPF_ALU | BPF_LSH | BPF_X: /* ALU_REG */
         case BPF_ALU | BPF_RSH | BPF_X: /* ALU_REG */
+        case BPF_ALU | BPF_ARSH | BPF_X: /* ALU_REG */
                 src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp);
                 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
                 if (src < 0 || dst < 0)
@@ -913,6 +914,9 @@ static int build_one_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
                 case BPF_RSH:
                         emit_instr(ctx, srlv, dst, dst, src);
                         break;
+                case BPF_ARSH:
+                        emit_instr(ctx, srav, dst, dst, src);
+                        break;
                 default:
                         pr_err("ALU_REG NOT HANDLED\n");
                         return -EINVAL;
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index a6e9e314c707..901459226eca 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -342,6 +342,8 @@
 #define PPC_INST_SLW                    0x7c000030
 #define PPC_INST_SLD                    0x7c000036
 #define PPC_INST_SRW                    0x7c000430
+#define PPC_INST_SRAW                   0x7c000630
+#define PPC_INST_SRAWI                  0x7c000670
 #define PPC_INST_SRD                    0x7c000436
 #define PPC_INST_SRAD                   0x7c000634
 #define PPC_INST_SRADI                  0x7c000674
diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h
index 47fc6660845d..c2d5192ed64f 100644
--- a/arch/powerpc/net/bpf_jit.h
+++ b/arch/powerpc/net/bpf_jit.h
@@ -152,6 +152,10 @@
                                      ___PPC_RS(a) | ___PPC_RB(s))
 #define PPC_SRW(d, a, s)        EMIT(PPC_INST_SRW | ___PPC_RA(d) |            \
                                      ___PPC_RS(a) | ___PPC_RB(s))
+#define PPC_SRAW(d, a, s)       EMIT(PPC_INST_SRAW | ___PPC_RA(d) |           \
+                                     ___PPC_RS(a) | ___PPC_RB(s))
+#define PPC_SRAWI(d, a, i)      EMIT(PPC_INST_SRAWI | ___PPC_RA(d) |          \
+                                     ___PPC_RS(a) | __PPC_SH(i))
 #define PPC_SRD(d, a, s)        EMIT(PPC_INST_SRD | ___PPC_RA(d) |            \
                                      ___PPC_RS(a) | ___PPC_RB(s))
 #define PPC_SRAD(d, a, s)       EMIT(PPC_INST_SRAD | ___PPC_RA(d) |           \
diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_comp64.c
index 17482f5de3e2..7dc81877057d 100644
--- a/arch/powerpc/net/bpf_jit_comp64.c
+++ b/arch/powerpc/net/bpf_jit_comp64.c
@@ -529,9 +529,15 @@ static int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,
                         if (imm != 0)
                                 PPC_SRDI(dst_reg, dst_reg, imm);
                         break;
+                case BPF_ALU | BPF_ARSH | BPF_X: /* (s32) dst >>= src */
+                        PPC_SRAW(dst_reg, dst_reg, src_reg);
+                        goto bpf_alu32_trunc;
                 case BPF_ALU64 | BPF_ARSH | BPF_X: /* (s64) dst >>= src */
                         PPC_SRAD(dst_reg, dst_reg, src_reg);
                         break;
+                case BPF_ALU | BPF_ARSH | BPF_K: /* (s32) dst >>= imm */
+                        PPC_SRAWI(dst_reg, dst_reg, imm);
+                        goto bpf_alu32_trunc;
                 case BPF_ALU64 | BPF_ARSH | BPF_K: /* (s64) dst >>= imm */
                         if (imm != 0)
                                 PPC_SRADI(dst_reg, dst_reg, imm);
diff --git a/arch/s390/net/bpf_jit_comp.c b/arch/s390/net/bpf_jit_comp.c
index d7052cbe984f..3ff758eeb71d 100644
--- a/arch/s390/net/bpf_jit_comp.c
+++ b/arch/s390/net/bpf_jit_comp.c
@@ -821,10 +821,22 @@ static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i
         /*
          * BPF_ARSH
          */
+        case BPF_ALU | BPF_ARSH | BPF_X: /* ((s32) dst) >>= src */
+                /* sra %dst,%dst,0(%src) */
+                EMIT4_DISP(0x8a000000, dst_reg, src_reg, 0);
+                EMIT_ZERO(dst_reg);
+                break;
         case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
                 /* srag %dst,%dst,0(%src) */
                 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
                 break;
+        case BPF_ALU | BPF_ARSH | BPF_K: /* ((s32) dst >> imm */
+                if (imm == 0)
+                        break;
+                /* sra %dst,imm(%r0) */
+                EMIT4_DISP(0x8a000000, dst_reg, REG_0, imm);
+                EMIT_ZERO(dst_reg);
+                break;
         case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
                 if (imm == 0)
                         break;
diff --git a/drivers/net/ethernet/netronome/nfp/bpf/jit.c b/drivers/net/ethernet/netronome/nfp/bpf/jit.c
index 97d33bb4d84d..662cbc21d909 100644
--- a/drivers/net/ethernet/netronome/nfp/bpf/jit.c
+++ b/drivers/net/ethernet/netronome/nfp/bpf/jit.c
@@ -2382,6 +2382,49 @@ static int neg_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
         return 0;
 }
 
+static int __ashr_imm(struct nfp_prog *nfp_prog, u8 dst, u8 shift_amt)
+{
+        /* Set signedness bit (MSB of result). */
+        emit_alu(nfp_prog, reg_none(), reg_a(dst), ALU_OP_OR, reg_imm(0));
+        emit_shf(nfp_prog, reg_both(dst), reg_none(), SHF_OP_ASHR, reg_b(dst),
+                 SHF_SC_R_SHF, shift_amt);
+        wrp_immed(nfp_prog, reg_both(dst + 1), 0);
+
+        return 0;
+}
+
+static int ashr_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
+{
+        const struct bpf_insn *insn = &meta->insn;
+        u64 umin, umax;
+        u8 dst, src;
+
+        dst = insn->dst_reg * 2;
+        umin = meta->umin_src;
+        umax = meta->umax_src;
+        if (umin == umax)
+                return __ashr_imm(nfp_prog, dst, umin);
+
+        src = insn->src_reg * 2;
+        /* NOTE: the first insn will set both indirect shift amount (source A)
+         * and signedness bit (MSB of result).
+         */
+        emit_alu(nfp_prog, reg_none(), reg_a(src), ALU_OP_OR, reg_b(dst));
+        emit_shf_indir(nfp_prog, reg_both(dst), reg_none(), SHF_OP_ASHR,
+                       reg_b(dst), SHF_SC_R_SHF);
+        wrp_immed(nfp_prog, reg_both(dst + 1), 0);
+
+        return 0;
+}
+
+static int ashr_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
+{
+        const struct bpf_insn *insn = &meta->insn;
+        u8 dst = insn->dst_reg * 2;
+
+        return __ashr_imm(nfp_prog, dst, insn->imm);
+}
+
 static int shl_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
 {
         const struct bpf_insn *insn = &meta->insn;
@@ -3286,6 +3329,8 @@ static const instr_cb_t instr_cb[256] = {
         [BPF_ALU | BPF_DIV | BPF_K] =   div_imm,
         [BPF_ALU | BPF_NEG] =           neg_reg,
         [BPF_ALU | BPF_LSH | BPF_K] =   shl_imm,
+        [BPF_ALU | BPF_ARSH | BPF_X] =  ashr_reg,
+        [BPF_ALU | BPF_ARSH | BPF_K] =  ashr_imm,
         [BPF_ALU | BPF_END | BPF_X] =   end_reg32,
         [BPF_LD | BPF_IMM | BPF_DW] =   imm_ld8,
         [BPF_LD | BPF_ABS | BPF_B] =    data_ld1,
diff --git a/kernel/bpf/core.c b/kernel/bpf/core.c
index 628b3970a49b..a5b223ef7131 100644
--- a/kernel/bpf/core.c
+++ b/kernel/bpf/core.c
@@ -933,32 +933,34 @@ EXPORT_SYMBOL_GPL(__bpf_call_base);
 #define BPF_INSN_MAP(INSN_2, INSN_3)            \
         /* 32 bit ALU operations. */            \
         /*   Register based. */                 \
-        INSN_3(ALU, ADD, X),                    \
-        INSN_3(ALU, SUB, X),                    \
-        INSN_3(ALU, AND, X),                    \
-        INSN_3(ALU, OR,  X),                    \
-        INSN_3(ALU, LSH, X),                    \
-        INSN_3(ALU, RSH, X),                    \
-        INSN_3(ALU, XOR, X),                    \
-        INSN_3(ALU, MUL, X),                    \
-        INSN_3(ALU, MOV, X),                    \
-        INSN_3(ALU, DIV, X),                    \
-        INSN_3(ALU, MOD, X),                    \
+        INSN_3(ALU, ADD,  X),                   \
+        INSN_3(ALU, SUB,  X),                   \
+        INSN_3(ALU, AND,  X),                   \
+        INSN_3(ALU, OR,   X),                   \
+        INSN_3(ALU, LSH,  X),                   \
+        INSN_3(ALU, RSH,  X),                   \
+        INSN_3(ALU, XOR,  X),                   \
+        INSN_3(ALU, MUL,  X),                   \
+        INSN_3(ALU, MOV,  X),                   \
+        INSN_3(ALU, ARSH, X),                   \
+        INSN_3(ALU, DIV,  X),                   \
+        INSN_3(ALU, MOD,  X),                   \
         INSN_2(ALU, NEG),                       \
         INSN_3(ALU, END, TO_BE),                \
         INSN_3(ALU, END, TO_LE),                \
         /*   Immediate based. */                \
-        INSN_3(ALU, ADD, K),                    \
-        INSN_3(ALU, SUB, K),                    \
-        INSN_3(ALU, AND, K),                    \
-        INSN_3(ALU, OR,  K),                    \
-        INSN_3(ALU, LSH, K),                    \
-        INSN_3(ALU, RSH, K),                    \
-        INSN_3(ALU, XOR, K),                    \
-        INSN_3(ALU, MUL, K),                    \
-        INSN_3(ALU, MOV, K),                    \
-        INSN_3(ALU, DIV, K),                    \
-        INSN_3(ALU, MOD, K),                    \
+        INSN_3(ALU, ADD,  K),                   \
+        INSN_3(ALU, SUB,  K),                   \
+        INSN_3(ALU, AND,  K),                   \
+        INSN_3(ALU, OR,   K),                   \
+        INSN_3(ALU, LSH,  K),                   \
+        INSN_3(ALU, RSH,  K),                   \
+        INSN_3(ALU, XOR,  K),                   \
+        INSN_3(ALU, MUL,  K),                   \
+        INSN_3(ALU, MOV,  K),                   \
+        INSN_3(ALU, ARSH, K),                   \
+        INSN_3(ALU, DIV,  K),                   \
+        INSN_3(ALU, MOD,  K),                   \
         /* 64 bit ALU operations. */            \
         /*   Register based. */                 \
         INSN_3(ALU64, ADD,  X),                 \
@@ -1137,6 +1139,12 @@ select_insn:
                 DST = (u64) (u32) insn[0].imm | ((u64) (u32) insn[1].imm) << 32;
                 insn++;
                 CONT;
+        ALU_ARSH_X:
+                DST = (u64) (u32) ((*(s32 *) &DST) >> SRC);
+                CONT;
+        ALU_ARSH_K:
+                DST = (u64) (u32) ((*(s32 *) &DST) >> IMM);
+                CONT;
         ALU64_ARSH_X:
                 (*(s64 *) &DST) >>= SRC;
                 CONT;
diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
index 7658c61c1a88..2752d35ad073 100644
--- a/kernel/bpf/verifier.c
+++ b/kernel/bpf/verifier.c
@@ -3649,11 +3649,6 @@ static int check_alu_op(struct bpf_verifier_env *env, struct bpf_insn *insn)
                         return -EINVAL;
                 }
 
-                if (opcode == BPF_ARSH && BPF_CLASS(insn->code) != BPF_ALU64) {
-                        verbose(env, "BPF_ARSH not supported for 32 bit ALU\n");
-                        return -EINVAL;
-                }
-
                 if ((opcode == BPF_LSH || opcode == BPF_RSH ||
                      opcode == BPF_ARSH) && BPF_SRC(insn->code) == BPF_K) {
                         int size = BPF_CLASS(insn->code) == BPF_ALU64 ? 64 : 32;
diff --git a/tools/testing/selftests/bpf/test_verifier.c b/tools/testing/selftests/bpf/test_verifier.c
index b4b4a3f93639..36ce58b4933e 100644
--- a/tools/testing/selftests/bpf/test_verifier.c
+++ b/tools/testing/selftests/bpf/test_verifier.c
@@ -721,8 +721,18 @@ static struct bpf_test tests[] = {
                         BPF_ALU32_IMM(BPF_ARSH, BPF_REG_0, 5),
                         BPF_EXIT_INSN(),
                 },
-                .result = REJECT,
-                .errstr = "unknown opcode c4",
+                .result = ACCEPT,
+                .retval = 0,
+        },
+        {
+                "arsh32 on imm 2",
+                .insns = {
+                        BPF_LD_IMM64(BPF_REG_0, 0x1122334485667788),
+                        BPF_ALU32_IMM(BPF_ARSH, BPF_REG_0, 7),
+                        BPF_EXIT_INSN(),
+                },
+                .result = ACCEPT,
+                .retval = -16069393,
         },
         {
                 "arsh32 on reg",
@@ -732,8 +742,19 @@ static struct bpf_test tests[] = {
                         BPF_ALU32_REG(BPF_ARSH, BPF_REG_0, BPF_REG_1),
                         BPF_EXIT_INSN(),
                 },
-                .result = REJECT,
-                .errstr = "unknown opcode cc",
+                .result = ACCEPT,
+                .retval = 0,
+        },
+        {
+                "arsh32 on reg 2",
+                .insns = {
+                        BPF_LD_IMM64(BPF_REG_0, 0xffff55667788),
+                        BPF_MOV64_IMM(BPF_REG_1, 15),
+                        BPF_ALU32_REG(BPF_ARSH, BPF_REG_0, BPF_REG_1),
+                        BPF_EXIT_INSN(),
+                },
+                .result = ACCEPT,
+                .retval = 43724,
         },
         {
                 "arsh64 on imm",