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-rw-r--r--Documentation/devicetree/bindings/arm/exynos/power_domain.txt2
-rw-r--r--Documentation/devicetree/bindings/arm/sti.txt4
-rw-r--r--Documentation/devicetree/bindings/power/power_domain.txt29
-rw-r--r--Documentation/devicetree/bindings/watchdog/atmel-wdt.txt5
-rw-r--r--MAINTAINERS12
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/dts/am335x-bone-common.dtsi8
-rw-r--r--arch/arm/boot/dts/am335x-bone.dts8
-rw-r--r--arch/arm/boot/dts/am335x-lxm.dts4
-rw-r--r--arch/arm/boot/dts/am33xx-clocks.dtsi6
-rw-r--r--arch/arm/boot/dts/am43xx-clocks.dtsi12
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi7
-rw-r--r--arch/arm/boot/dts/at91sam9261.dtsi9
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi5
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi3
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi1
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi5
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts10
-rw-r--r--arch/arm/boot/dts/dra72-evm.dts10
-rw-r--r--arch/arm/boot/dts/dra7xx-clocks.dtsi90
-rw-r--r--arch/arm/boot/dts/exynos3250.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos4-cpu-thermal.dtsi52
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi45
-rw-r--r--arch/arm/boot/dts/exynos4210-trats.dts19
-rw-r--r--arch/arm/boot/dts/exynos4210-universal_c210.dts57
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi38
-rw-r--r--arch/arm/boot/dts/exynos4212.dtsi5
-rw-r--r--arch/arm/boot/dts/exynos4412-odroid-common.dtsi64
-rw-r--r--arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi24
-rw-r--r--arch/arm/boot/dts/exynos4412-trats2.dts15
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi5
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi12
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi44
-rw-r--r--arch/arm/boot/dts/exynos5420-trip-points.dtsi35
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi33
-rw-r--r--arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi24
-rw-r--r--arch/arm/boot/dts/exynos5440-trip-points.dtsi25
-rw-r--r--arch/arm/boot/dts/exynos5440.dtsi18
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6sl-evk.dts2
-rw-r--r--arch/arm/boot/dts/omap5-core-thermal.dtsi2
-rw-r--r--arch/arm/boot/dts/omap5-gpu-thermal.dtsi2
-rw-r--r--arch/arm/boot/dts/omap5.dtsi4
-rw-r--r--arch/arm/boot/dts/omap54xx-clocks.dtsi41
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi3
-rw-r--r--arch/arm/boot/dts/sama5d4.dtsi9
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi6
-rw-r--r--arch/arm/configs/at91_dt_defconfig1
-rw-r--r--arch/arm/configs/multi_v7_defconfig2
-rw-r--r--arch/arm/configs/omap2plus_defconfig1
-rw-r--r--arch/arm/configs/sama5_defconfig2
-rw-r--r--arch/arm/configs/sunxi_defconfig1
-rw-r--r--arch/arm/configs/vexpress_defconfig2
-rw-r--r--arch/arm/include/debug/at91.S5
-rw-r--r--arch/arm/mach-at91/pm.c22
-rw-r--r--arch/arm/mach-at91/pm.h2
-rw-r--r--arch/arm/mach-at91/pm_slowclock.S80
-rw-r--r--arch/arm/mach-exynos/platsmp.c3
-rw-r--r--arch/arm/mach-exynos/pm_domains.c28
-rw-r--r--arch/arm/mach-exynos/suspend.c4
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c10
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c103
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c1
-rw-r--r--arch/arm/mach-omap2/prm44xx.c4
-rw-r--r--arch/arm/mach-socfpga/core.h2
-rw-r--r--arch/arm/mach-socfpga/socfpga.c5
-rw-r--r--arch/arm/mach-sti/board-dt.c1
-rw-r--r--include/dt-bindings/pinctrl/am33xx.h3
-rw-r--r--include/dt-bindings/pinctrl/am43xx.h3
-rw-r--r--include/soc/at91/at91sam9_ddrsdr.h2
71 files changed, 882 insertions, 225 deletions
diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index f4445e5a2bbb..1e097037349c 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -22,6 +22,8 @@ Optional Properties:
22 - pclkN, clkN: Pairs of parent of input clock and input clock to the 22 - pclkN, clkN: Pairs of parent of input clock and input clock to the
23 devices in this power domain. Maximum of 4 pairs (N = 0 to 3) 23 devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
24 are supported currently. 24 are supported currently.
25- power-domains: phandle pointing to the parent power domain, for more details
26 see Documentation/devicetree/bindings/power/power_domain.txt
25 27
26Node of a device using power domains must have a power-domains property 28Node of a device using power domains must have a power-domains property
27defined with a phandle to respective power domain. 29defined with a phandle to respective power domain.
diff --git a/Documentation/devicetree/bindings/arm/sti.txt b/Documentation/devicetree/bindings/arm/sti.txt
index d70ec358736c..8d27f6b084c7 100644
--- a/Documentation/devicetree/bindings/arm/sti.txt
+++ b/Documentation/devicetree/bindings/arm/sti.txt
@@ -13,6 +13,10 @@ Boards with the ST STiH407 SoC shall have the following properties:
13Required root node property: 13Required root node property:
14compatible = "st,stih407"; 14compatible = "st,stih407";
15 15
16Boards with the ST STiH410 SoC shall have the following properties:
17Required root node property:
18compatible = "st,stih410";
19
16Boards with the ST STiH418 SoC shall have the following properties: 20Boards with the ST STiH418 SoC shall have the following properties:
17Required root node property: 21Required root node property:
18compatible = "st,stih418"; 22compatible = "st,stih418";
diff --git a/Documentation/devicetree/bindings/power/power_domain.txt b/Documentation/devicetree/bindings/power/power_domain.txt
index 98c16672ab5f..0f8ed3710c66 100644
--- a/Documentation/devicetree/bindings/power/power_domain.txt
+++ b/Documentation/devicetree/bindings/power/power_domain.txt
@@ -19,6 +19,16 @@ Required properties:
19 providing multiple PM domains (e.g. power controllers), but can be any value 19 providing multiple PM domains (e.g. power controllers), but can be any value
20 as specified by device tree binding documentation of particular provider. 20 as specified by device tree binding documentation of particular provider.
21 21
22Optional properties:
23 - power-domains : A phandle and PM domain specifier as defined by bindings of
24 the power controller specified by phandle.
25 Some power domains might be powered from another power domain (or have
26 other hardware specific dependencies). For representing such dependency
27 a standard PM domain consumer binding is used. When provided, all domains
28 created by the given provider should be subdomains of the domain
29 specified by this binding. More details about power domain specifier are
30 available in the next section.
31
22Example: 32Example:
23 33
24 power: power-controller@12340000 { 34 power: power-controller@12340000 {
@@ -30,6 +40,25 @@ Example:
30The node above defines a power controller that is a PM domain provider and 40The node above defines a power controller that is a PM domain provider and
31expects one cell as its phandle argument. 41expects one cell as its phandle argument.
32 42
43Example 2:
44
45 parent: power-controller@12340000 {
46 compatible = "foo,power-controller";
47 reg = <0x12340000 0x1000>;
48 #power-domain-cells = <1>;
49 };
50
51 child: power-controller@12340000 {
52 compatible = "foo,power-controller";
53 reg = <0x12341000 0x1000>;
54 power-domains = <&parent 0>;
55 #power-domain-cells = <1>;
56 };
57
58The nodes above define two power controllers: 'parent' and 'child'.
59Domains created by the 'child' power controller are subdomains of '0' power
60domain provided by the 'parent' power controller.
61
33==PM domain consumers== 62==PM domain consumers==
34 63
35Required properties: 64Required properties:
diff --git a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
index f90e294d7631..a4d869744f59 100644
--- a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
@@ -26,6 +26,11 @@ Optional properties:
26- atmel,disable : Should be present if you want to disable the watchdog. 26- atmel,disable : Should be present if you want to disable the watchdog.
27- atmel,idle-halt : Should be present if you want to stop the watchdog when 27- atmel,idle-halt : Should be present if you want to stop the watchdog when
28 entering idle state. 28 entering idle state.
29 CAUTION: This property should be used with care, it actually makes the
30 watchdog not counting when the CPU is in idle state, therefore the
31 watchdog reset time depends on mean CPU usage and will not reset at all
32 if the CPU stop working while it is in idle state, which is probably
33 not what you want.
29- atmel,dbg-halt : Should be present if you want to stop the watchdog when 34- atmel,dbg-halt : Should be present if you want to stop the watchdog when
30 entering debug state. 35 entering debug state.
31 36
diff --git a/MAINTAINERS b/MAINTAINERS
index 69cc89f7a9c9..0e1abe8cc684 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1030,6 +1030,16 @@ F: arch/arm/mach-mxs/
1030F: arch/arm/boot/dts/imx* 1030F: arch/arm/boot/dts/imx*
1031F: arch/arm/configs/imx*_defconfig 1031F: arch/arm/configs/imx*_defconfig
1032 1032
1033ARM/FREESCALE VYBRID ARM ARCHITECTURE
1034M: Shawn Guo <shawn.guo@linaro.org>
1035M: Sascha Hauer <kernel@pengutronix.de>
1036R: Stefan Agner <stefan@agner.ch>
1037L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1038S: Maintained
1039T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
1040F: arch/arm/mach-imx/*vf610*
1041F: arch/arm/boot/dts/vf*
1042
1033ARM/GLOMATION GESBC9312SX MACHINE SUPPORT 1043ARM/GLOMATION GESBC9312SX MACHINE SUPPORT
1034M: Lennert Buytenhek <kernel@wantstofly.org> 1044M: Lennert Buytenhek <kernel@wantstofly.org>
1035L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1045L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -1188,6 +1198,7 @@ ARM/Marvell Dove/MV78xx0/Orion SOC support
1188M: Jason Cooper <jason@lakedaemon.net> 1198M: Jason Cooper <jason@lakedaemon.net>
1189M: Andrew Lunn <andrew@lunn.ch> 1199M: Andrew Lunn <andrew@lunn.ch>
1190M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 1200M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
1201M: Gregory Clement <gregory.clement@free-electrons.com>
1191L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1202L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1192S: Maintained 1203S: Maintained
1193F: arch/arm/mach-dove/ 1204F: arch/arm/mach-dove/
@@ -2107,7 +2118,6 @@ F: drivers/net/ethernet/broadcom/bnx2x/
2107 2118
2108BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITECTURE 2119BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITECTURE
2109M: Christian Daudt <bcm@fixthebug.org> 2120M: Christian Daudt <bcm@fixthebug.org>
2110M: Matt Porter <mporter@linaro.org>
2111M: Florian Fainelli <f.fainelli@gmail.com> 2121M: Florian Fainelli <f.fainelli@gmail.com>
2112L: bcm-kernel-feedback-list@broadcom.com 2122L: bcm-kernel-feedback-list@broadcom.com
2113T: git git://github.com/broadcom/mach-bcm 2123T: git git://github.com/broadcom/mach-bcm
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 7f99cd652203..eb7bb511f853 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -150,6 +150,7 @@ machine-$(CONFIG_ARCH_BERLIN) += berlin
150machine-$(CONFIG_ARCH_CLPS711X) += clps711x 150machine-$(CONFIG_ARCH_CLPS711X) += clps711x
151machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx 151machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
152machine-$(CONFIG_ARCH_DAVINCI) += davinci 152machine-$(CONFIG_ARCH_DAVINCI) += davinci
153machine-$(CONFIG_ARCH_DIGICOLOR) += digicolor
153machine-$(CONFIG_ARCH_DOVE) += dove 154machine-$(CONFIG_ARCH_DOVE) += dove
154machine-$(CONFIG_ARCH_EBSA110) += ebsa110 155machine-$(CONFIG_ARCH_EBSA110) += ebsa110
155machine-$(CONFIG_ARCH_EFM32) += efm32 156machine-$(CONFIG_ARCH_EFM32) += efm32
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 2c6248d9a9ef..c3255e0c90aa 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -301,3 +301,11 @@
301 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; 301 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
302 cd-inverted; 302 cd-inverted;
303}; 303};
304
305&aes {
306 status = "okay";
307};
308
309&sham {
310 status = "okay";
311};
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 83d40f7655e5..6b8493720424 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -24,11 +24,3 @@
24&mmc1 { 24&mmc1 {
25 vmmc-supply = <&ldo3_reg>; 25 vmmc-supply = <&ldo3_reg>;
26}; 26};
27
28&sham {
29 status = "okay";
30};
31
32&aes {
33 status = "okay";
34};
diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts
index 7266a00aab2e..5c5667a3624d 100644
--- a/arch/arm/boot/dts/am335x-lxm.dts
+++ b/arch/arm/boot/dts/am335x-lxm.dts
@@ -328,6 +328,10 @@
328 dual_emac_res_vlan = <3>; 328 dual_emac_res_vlan = <3>;
329}; 329};
330 330
331&phy_sel {
332 rmii-clock-ext;
333};
334
331&mac { 335&mac {
332 pinctrl-names = "default", "sleep"; 336 pinctrl-names = "default", "sleep";
333 pinctrl-0 = <&cpsw_default>; 337 pinctrl-0 = <&cpsw_default>;
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 712edce7d6fb..071b56aa0c7e 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -99,7 +99,7 @@
99 ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { 99 ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
100 #clock-cells = <0>; 100 #clock-cells = <0>;
101 compatible = "ti,gate-clock"; 101 compatible = "ti,gate-clock";
102 clocks = <&dpll_per_m2_ck>; 102 clocks = <&l4ls_gclk>;
103 ti,bit-shift = <0>; 103 ti,bit-shift = <0>;
104 reg = <0x0664>; 104 reg = <0x0664>;
105 }; 105 };
@@ -107,7 +107,7 @@
107 ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { 107 ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
108 #clock-cells = <0>; 108 #clock-cells = <0>;
109 compatible = "ti,gate-clock"; 109 compatible = "ti,gate-clock";
110 clocks = <&dpll_per_m2_ck>; 110 clocks = <&l4ls_gclk>;
111 ti,bit-shift = <1>; 111 ti,bit-shift = <1>;
112 reg = <0x0664>; 112 reg = <0x0664>;
113 }; 113 };
@@ -115,7 +115,7 @@
115 ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { 115 ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
116 #clock-cells = <0>; 116 #clock-cells = <0>;
117 compatible = "ti,gate-clock"; 117 compatible = "ti,gate-clock";
118 clocks = <&dpll_per_m2_ck>; 118 clocks = <&l4ls_gclk>;
119 ti,bit-shift = <2>; 119 ti,bit-shift = <2>;
120 reg = <0x0664>; 120 reg = <0x0664>;
121 }; 121 };
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index c7dc9dab93a4..cfb49686ab6a 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -107,7 +107,7 @@
107 ehrpwm0_tbclk: ehrpwm0_tbclk { 107 ehrpwm0_tbclk: ehrpwm0_tbclk {
108 #clock-cells = <0>; 108 #clock-cells = <0>;
109 compatible = "ti,gate-clock"; 109 compatible = "ti,gate-clock";
110 clocks = <&dpll_per_m2_ck>; 110 clocks = <&l4ls_gclk>;
111 ti,bit-shift = <0>; 111 ti,bit-shift = <0>;
112 reg = <0x0664>; 112 reg = <0x0664>;
113 }; 113 };
@@ -115,7 +115,7 @@
115 ehrpwm1_tbclk: ehrpwm1_tbclk { 115 ehrpwm1_tbclk: ehrpwm1_tbclk {
116 #clock-cells = <0>; 116 #clock-cells = <0>;
117 compatible = "ti,gate-clock"; 117 compatible = "ti,gate-clock";
118 clocks = <&dpll_per_m2_ck>; 118 clocks = <&l4ls_gclk>;
119 ti,bit-shift = <1>; 119 ti,bit-shift = <1>;
120 reg = <0x0664>; 120 reg = <0x0664>;
121 }; 121 };
@@ -123,7 +123,7 @@
123 ehrpwm2_tbclk: ehrpwm2_tbclk { 123 ehrpwm2_tbclk: ehrpwm2_tbclk {
124 #clock-cells = <0>; 124 #clock-cells = <0>;
125 compatible = "ti,gate-clock"; 125 compatible = "ti,gate-clock";
126 clocks = <&dpll_per_m2_ck>; 126 clocks = <&l4ls_gclk>;
127 ti,bit-shift = <2>; 127 ti,bit-shift = <2>;
128 reg = <0x0664>; 128 reg = <0x0664>;
129 }; 129 };
@@ -131,7 +131,7 @@
131 ehrpwm3_tbclk: ehrpwm3_tbclk { 131 ehrpwm3_tbclk: ehrpwm3_tbclk {
132 #clock-cells = <0>; 132 #clock-cells = <0>;
133 compatible = "ti,gate-clock"; 133 compatible = "ti,gate-clock";
134 clocks = <&dpll_per_m2_ck>; 134 clocks = <&l4ls_gclk>;
135 ti,bit-shift = <4>; 135 ti,bit-shift = <4>;
136 reg = <0x0664>; 136 reg = <0x0664>;
137 }; 137 };
@@ -139,7 +139,7 @@
139 ehrpwm4_tbclk: ehrpwm4_tbclk { 139 ehrpwm4_tbclk: ehrpwm4_tbclk {
140 #clock-cells = <0>; 140 #clock-cells = <0>;
141 compatible = "ti,gate-clock"; 141 compatible = "ti,gate-clock";
142 clocks = <&dpll_per_m2_ck>; 142 clocks = <&l4ls_gclk>;
143 ti,bit-shift = <5>; 143 ti,bit-shift = <5>;
144 reg = <0x0664>; 144 reg = <0x0664>;
145 }; 145 };
@@ -147,7 +147,7 @@
147 ehrpwm5_tbclk: ehrpwm5_tbclk { 147 ehrpwm5_tbclk: ehrpwm5_tbclk {
148 #clock-cells = <0>; 148 #clock-cells = <0>;
149 compatible = "ti,gate-clock"; 149 compatible = "ti,gate-clock";
150 clocks = <&dpll_per_m2_ck>; 150 clocks = <&l4ls_gclk>;
151 ti,bit-shift = <6>; 151 ti,bit-shift = <6>;
152 reg = <0x0664>; 152 reg = <0x0664>;
153 }; 153 };
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index fff0ee69aab4..e7f0a4ae271c 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -494,12 +494,12 @@
494 494
495 pinctrl_usart3_rts: usart3_rts-0 { 495 pinctrl_usart3_rts: usart3_rts-0 {
496 atmel,pins = 496 atmel,pins =
497 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC8 periph B */ 497 <AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
498 }; 498 };
499 499
500 pinctrl_usart3_cts: usart3_cts-0 { 500 pinctrl_usart3_cts: usart3_cts-0 {
501 atmel,pins = 501 atmel,pins =
502 <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */ 502 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
503 }; 503 };
504 }; 504 };
505 505
@@ -853,7 +853,7 @@
853 }; 853 };
854 854
855 usb1: gadget@fffa4000 { 855 usb1: gadget@fffa4000 {
856 compatible = "atmel,at91rm9200-udc"; 856 compatible = "atmel,at91sam9260-udc";
857 reg = <0xfffa4000 0x4000>; 857 reg = <0xfffa4000 0x4000>;
858 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; 858 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
859 clocks = <&udc_clk>, <&udpck>; 859 clocks = <&udc_clk>, <&udpck>;
@@ -976,7 +976,6 @@
976 atmel,watchdog-type = "hardware"; 976 atmel,watchdog-type = "hardware";
977 atmel,reset-type = "all"; 977 atmel,reset-type = "all";
978 atmel,dbg-halt; 978 atmel,dbg-halt;
979 atmel,idle-halt;
980 status = "disabled"; 979 status = "disabled";
981 }; 980 };
982 981
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index e247b0b5fdab..d55fdf2487ef 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -124,11 +124,12 @@
124 }; 124 };
125 125
126 usb1: gadget@fffa4000 { 126 usb1: gadget@fffa4000 {
127 compatible = "atmel,at91rm9200-udc"; 127 compatible = "atmel,at91sam9261-udc";
128 reg = <0xfffa4000 0x4000>; 128 reg = <0xfffa4000 0x4000>;
129 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; 129 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
130 clocks = <&usb>, <&udc_clk>, <&udpck>; 130 clocks = <&udc_clk>, <&udpck>;
131 clock-names = "usb_clk", "udc_clk", "udpck"; 131 clock-names = "pclk", "hclk";
132 atmel,matrix = <&matrix>;
132 status = "disabled"; 133 status = "disabled";
133 }; 134 };
134 135
@@ -262,7 +263,7 @@
262 }; 263 };
263 264
264 matrix: matrix@ffffee00 { 265 matrix: matrix@ffffee00 {
265 compatible = "atmel,at91sam9260-bus-matrix"; 266 compatible = "atmel,at91sam9260-bus-matrix", "syscon";
266 reg = <0xffffee00 0x200>; 267 reg = <0xffffee00 0x200>;
267 }; 268 };
268 269
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 1f67bb4c144e..fce301c4e9d6 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -69,7 +69,7 @@
69 69
70 sram1: sram@00500000 { 70 sram1: sram@00500000 {
71 compatible = "mmio-sram"; 71 compatible = "mmio-sram";
72 reg = <0x00300000 0x4000>; 72 reg = <0x00500000 0x4000>;
73 }; 73 };
74 74
75 ahb { 75 ahb {
@@ -856,7 +856,7 @@
856 }; 856 };
857 857
858 usb1: gadget@fff78000 { 858 usb1: gadget@fff78000 {
859 compatible = "atmel,at91rm9200-udc"; 859 compatible = "atmel,at91sam9263-udc";
860 reg = <0xfff78000 0x4000>; 860 reg = <0xfff78000 0x4000>;
861 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; 861 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
862 clocks = <&udc_clk>, <&udpck>; 862 clocks = <&udc_clk>, <&udpck>;
@@ -905,7 +905,6 @@
905 atmel,watchdog-type = "hardware"; 905 atmel,watchdog-type = "hardware";
906 atmel,reset-type = "all"; 906 atmel,reset-type = "all";
907 atmel,dbg-halt; 907 atmel,dbg-halt;
908 atmel,idle-halt;
909 status = "disabled"; 908 status = "disabled";
910 }; 909 };
911 910
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index ee80aa9c0759..488af63d5174 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -1116,7 +1116,6 @@
1116 atmel,watchdog-type = "hardware"; 1116 atmel,watchdog-type = "hardware";
1117 atmel,reset-type = "all"; 1117 atmel,reset-type = "all";
1118 atmel,dbg-halt; 1118 atmel,dbg-halt;
1119 atmel,idle-halt;
1120 status = "disabled"; 1119 status = "disabled";
1121 }; 1120 };
1122 1121
@@ -1301,7 +1300,7 @@
1301 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1300 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1302 reg = <0x00800000 0x100000>; 1301 reg = <0x00800000 0x100000>;
1303 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1302 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1304 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; 1303 clocks = <&utmi>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1305 clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck"; 1304 clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck";
1306 status = "disabled"; 1305 status = "disabled";
1307 }; 1306 };
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index c2666a7cb5b1..0c53a375ba99 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -894,7 +894,6 @@
894 atmel,watchdog-type = "hardware"; 894 atmel,watchdog-type = "hardware";
895 atmel,reset-type = "all"; 895 atmel,reset-type = "all";
896 atmel,dbg-halt; 896 atmel,dbg-halt;
897 atmel,idle-halt;
898 status = "disabled"; 897 status = "disabled";
899 }; 898 };
900 899
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 818dabdd8c0e..d221179d0f1a 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -1066,7 +1066,7 @@
1066 reg = <0x00500000 0x80000 1066 reg = <0x00500000 0x80000
1067 0xf803c000 0x400>; 1067 0xf803c000 0x400>;
1068 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; 1068 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
1069 clocks = <&usb>, <&udphs_clk>; 1069 clocks = <&utmi>, <&udphs_clk>;
1070 clock-names = "hclk", "pclk"; 1070 clock-names = "hclk", "pclk";
1071 status = "disabled"; 1071 status = "disabled";
1072 1072
@@ -1130,7 +1130,6 @@
1130 atmel,watchdog-type = "hardware"; 1130 atmel,watchdog-type = "hardware";
1131 atmel,reset-type = "all"; 1131 atmel,reset-type = "all";
1132 atmel,dbg-halt; 1132 atmel,dbg-halt;
1133 atmel,idle-halt;
1134 status = "disabled"; 1133 status = "disabled";
1135 }; 1134 };
1136 1135
@@ -1186,7 +1185,7 @@
1186 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1185 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1187 reg = <0x00700000 0x100000>; 1186 reg = <0x00700000 0x100000>;
1188 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1187 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1189 clocks = <&usb>, <&uhphs_clk>, <&uhpck>; 1188 clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
1190 clock-names = "usb_clk", "ehci_clk", "uhpck"; 1189 clock-names = "usb_clk", "ehci_clk", "uhpck";
1191 status = "disabled"; 1190 status = "disabled";
1192 }; 1191 };
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 3290a96ba586..7563d7ce01bb 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -263,17 +263,15 @@
263 263
264 dcan1_pins_default: dcan1_pins_default { 264 dcan1_pins_default: dcan1_pins_default {
265 pinctrl-single,pins = < 265 pinctrl-single,pins = <
266 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */ 266 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
267 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ 267 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
268 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
269 >; 268 >;
270 }; 269 };
271 270
272 dcan1_pins_sleep: dcan1_pins_sleep { 271 dcan1_pins_sleep: dcan1_pins_sleep {
273 pinctrl-single,pins = < 272 pinctrl-single,pins = <
274 0x3d0 (MUX_MODE15) /* dcan1_tx.off */ 273 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
275 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ 274 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
276 0x418 (MUX_MODE15) /* wakeup0.off */
277 >; 275 >;
278 }; 276 };
279}; 277};
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index e0264d0bf7b9..40ed539ce474 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -119,17 +119,15 @@
119 119
120 dcan1_pins_default: dcan1_pins_default { 120 dcan1_pins_default: dcan1_pins_default {
121 pinctrl-single,pins = < 121 pinctrl-single,pins = <
122 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */ 122 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
123 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ 123 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
124 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
125 >; 124 >;
126 }; 125 };
127 126
128 dcan1_pins_sleep: dcan1_pins_sleep { 127 dcan1_pins_sleep: dcan1_pins_sleep {
129 pinctrl-single,pins = < 128 pinctrl-single,pins = <
130 0x3d0 (MUX_MODE15) /* dcan1_tx.off */ 129 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
131 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ 130 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
132 0x418 (MUX_MODE15) /* wakeup0.off */
133 >; 131 >;
134 }; 132 };
135 133
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 4bdcbd61ce47..99b09a44e269 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -243,10 +243,18 @@
243 ti,invert-autoidle-bit; 243 ti,invert-autoidle-bit;
244 }; 244 };
245 245
246 dpll_core_byp_mux: dpll_core_byp_mux {
247 #clock-cells = <0>;
248 compatible = "ti,mux-clock";
249 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
250 ti,bit-shift = <23>;
251 reg = <0x012c>;
252 };
253
246 dpll_core_ck: dpll_core_ck { 254 dpll_core_ck: dpll_core_ck {
247 #clock-cells = <0>; 255 #clock-cells = <0>;
248 compatible = "ti,omap4-dpll-core-clock"; 256 compatible = "ti,omap4-dpll-core-clock";
249 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 257 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
250 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; 258 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
251 }; 259 };
252 260
@@ -309,10 +317,18 @@
309 clock-div = <1>; 317 clock-div = <1>;
310 }; 318 };
311 319
320 dpll_dsp_byp_mux: dpll_dsp_byp_mux {
321 #clock-cells = <0>;
322 compatible = "ti,mux-clock";
323 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
324 ti,bit-shift = <23>;
325 reg = <0x0240>;
326 };
327
312 dpll_dsp_ck: dpll_dsp_ck { 328 dpll_dsp_ck: dpll_dsp_ck {
313 #clock-cells = <0>; 329 #clock-cells = <0>;
314 compatible = "ti,omap4-dpll-clock"; 330 compatible = "ti,omap4-dpll-clock";
315 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; 331 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
316 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; 332 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
317 }; 333 };
318 334
@@ -335,10 +351,18 @@
335 clock-div = <1>; 351 clock-div = <1>;
336 }; 352 };
337 353
354 dpll_iva_byp_mux: dpll_iva_byp_mux {
355 #clock-cells = <0>;
356 compatible = "ti,mux-clock";
357 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
358 ti,bit-shift = <23>;
359 reg = <0x01ac>;
360 };
361
338 dpll_iva_ck: dpll_iva_ck { 362 dpll_iva_ck: dpll_iva_ck {
339 #clock-cells = <0>; 363 #clock-cells = <0>;
340 compatible = "ti,omap4-dpll-clock"; 364 compatible = "ti,omap4-dpll-clock";
341 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; 365 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
342 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; 366 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
343 }; 367 };
344 368
@@ -361,10 +385,18 @@
361 clock-div = <1>; 385 clock-div = <1>;
362 }; 386 };
363 387
388 dpll_gpu_byp_mux: dpll_gpu_byp_mux {
389 #clock-cells = <0>;
390 compatible = "ti,mux-clock";
391 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
392 ti,bit-shift = <23>;
393 reg = <0x02e4>;
394 };
395
364 dpll_gpu_ck: dpll_gpu_ck { 396 dpll_gpu_ck: dpll_gpu_ck {
365 #clock-cells = <0>; 397 #clock-cells = <0>;
366 compatible = "ti,omap4-dpll-clock"; 398 compatible = "ti,omap4-dpll-clock";
367 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 399 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
368 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; 400 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
369 }; 401 };
370 402
@@ -398,10 +430,18 @@
398 clock-div = <1>; 430 clock-div = <1>;
399 }; 431 };
400 432
433 dpll_ddr_byp_mux: dpll_ddr_byp_mux {
434 #clock-cells = <0>;
435 compatible = "ti,mux-clock";
436 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
437 ti,bit-shift = <23>;
438 reg = <0x021c>;
439 };
440
401 dpll_ddr_ck: dpll_ddr_ck { 441 dpll_ddr_ck: dpll_ddr_ck {
402 #clock-cells = <0>; 442 #clock-cells = <0>;
403 compatible = "ti,omap4-dpll-clock"; 443 compatible = "ti,omap4-dpll-clock";
404 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 444 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
405 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; 445 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
406 }; 446 };
407 447
@@ -416,10 +456,18 @@
416 ti,invert-autoidle-bit; 456 ti,invert-autoidle-bit;
417 }; 457 };
418 458
459 dpll_gmac_byp_mux: dpll_gmac_byp_mux {
460 #clock-cells = <0>;
461 compatible = "ti,mux-clock";
462 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
463 ti,bit-shift = <23>;
464 reg = <0x02b4>;
465 };
466
419 dpll_gmac_ck: dpll_gmac_ck { 467 dpll_gmac_ck: dpll_gmac_ck {
420 #clock-cells = <0>; 468 #clock-cells = <0>;
421 compatible = "ti,omap4-dpll-clock"; 469 compatible = "ti,omap4-dpll-clock";
422 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 470 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
423 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; 471 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
424 }; 472 };
425 473
@@ -482,10 +530,18 @@
482 clock-div = <1>; 530 clock-div = <1>;
483 }; 531 };
484 532
533 dpll_eve_byp_mux: dpll_eve_byp_mux {
534 #clock-cells = <0>;
535 compatible = "ti,mux-clock";
536 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
537 ti,bit-shift = <23>;
538 reg = <0x0290>;
539 };
540
485 dpll_eve_ck: dpll_eve_ck { 541 dpll_eve_ck: dpll_eve_ck {
486 #clock-cells = <0>; 542 #clock-cells = <0>;
487 compatible = "ti,omap4-dpll-clock"; 543 compatible = "ti,omap4-dpll-clock";
488 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; 544 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
489 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; 545 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
490 }; 546 };
491 547
@@ -1249,10 +1305,18 @@
1249 clock-div = <1>; 1305 clock-div = <1>;
1250 }; 1306 };
1251 1307
1308 dpll_per_byp_mux: dpll_per_byp_mux {
1309 #clock-cells = <0>;
1310 compatible = "ti,mux-clock";
1311 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1312 ti,bit-shift = <23>;
1313 reg = <0x014c>;
1314 };
1315
1252 dpll_per_ck: dpll_per_ck { 1316 dpll_per_ck: dpll_per_ck {
1253 #clock-cells = <0>; 1317 #clock-cells = <0>;
1254 compatible = "ti,omap4-dpll-clock"; 1318 compatible = "ti,omap4-dpll-clock";
1255 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; 1319 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1256 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; 1320 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1257 }; 1321 };
1258 1322
@@ -1275,10 +1339,18 @@
1275 clock-div = <1>; 1339 clock-div = <1>;
1276 }; 1340 };
1277 1341
1342 dpll_usb_byp_mux: dpll_usb_byp_mux {
1343 #clock-cells = <0>;
1344 compatible = "ti,mux-clock";
1345 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1346 ti,bit-shift = <23>;
1347 reg = <0x018c>;
1348 };
1349
1278 dpll_usb_ck: dpll_usb_ck { 1350 dpll_usb_ck: dpll_usb_ck {
1279 #clock-cells = <0>; 1351 #clock-cells = <0>;
1280 compatible = "ti,omap4-dpll-j-type-clock"; 1352 compatible = "ti,omap4-dpll-j-type-clock";
1281 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; 1353 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1282 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; 1354 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1283 }; 1355 };
1284 1356
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 277b48b0b6f9..ac6b0ae42caf 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -18,6 +18,7 @@
18 */ 18 */
19 19
20#include "skeleton.dtsi" 20#include "skeleton.dtsi"
21#include "exynos4-cpu-thermal.dtsi"
21#include <dt-bindings/clock/exynos3250.h> 22#include <dt-bindings/clock/exynos3250.h>
22 23
23/ { 24/ {
@@ -193,6 +194,7 @@
193 interrupts = <0 216 0>; 194 interrupts = <0 216 0>;
194 clocks = <&cmu CLK_TMU_APBIF>; 195 clocks = <&cmu CLK_TMU_APBIF>;
195 clock-names = "tmu_apbif"; 196 clock-names = "tmu_apbif";
197 #include "exynos4412-tmu-sensor-conf.dtsi"
196 status = "disabled"; 198 status = "disabled";
197 }; 199 };
198 200
diff --git a/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi b/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi
new file mode 100644
index 000000000000..735cb2f10817
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi
@@ -0,0 +1,52 @@
1/*
2 * Device tree sources for Exynos4 thermal zone
3 *
4 * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <dt-bindings/thermal/thermal.h>
13
14/ {
15thermal-zones {
16 cpu_thermal: cpu-thermal {
17 thermal-sensors = <&tmu 0>;
18 polling-delay-passive = <0>;
19 polling-delay = <0>;
20 trips {
21 cpu_alert0: cpu-alert-0 {
22 temperature = <70000>; /* millicelsius */
23 hysteresis = <10000>; /* millicelsius */
24 type = "active";
25 };
26 cpu_alert1: cpu-alert-1 {
27 temperature = <95000>; /* millicelsius */
28 hysteresis = <10000>; /* millicelsius */
29 type = "active";
30 };
31 cpu_alert2: cpu-alert-2 {
32 temperature = <110000>; /* millicelsius */
33 hysteresis = <10000>; /* millicelsius */
34 type = "active";
35 };
36 cpu_crit0: cpu-crit-0 {
37 temperature = <120000>; /* millicelsius */
38 hysteresis = <0>; /* millicelsius */
39 type = "critical";
40 };
41 };
42 cooling-maps {
43 map0 {
44 trip = <&cpu_alert0>;
45 };
46 map1 {
47 trip = <&cpu_alert1>;
48 };
49 };
50 };
51};
52};
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 76173cacd450..77ea547768f4 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -38,6 +38,7 @@
38 i2c5 = &i2c_5; 38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6; 39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7; 40 i2c7 = &i2c_7;
41 i2c8 = &i2c_8;
41 csis0 = &csis_0; 42 csis0 = &csis_0;
42 csis1 = &csis_1; 43 csis1 = &csis_1;
43 fimc0 = &fimc_0; 44 fimc0 = &fimc_0;
@@ -104,6 +105,7 @@
104 compatible = "samsung,exynos4210-pd"; 105 compatible = "samsung,exynos4210-pd";
105 reg = <0x10023C20 0x20>; 106 reg = <0x10023C20 0x20>;
106 #power-domain-cells = <0>; 107 #power-domain-cells = <0>;
108 power-domains = <&pd_lcd0>;
107 }; 109 };
108 110
109 pd_cam: cam-power-domain@10023C00 { 111 pd_cam: cam-power-domain@10023C00 {
@@ -554,6 +556,22 @@
554 status = "disabled"; 556 status = "disabled";
555 }; 557 };
556 558
559 i2c_8: i2c@138E0000 {
560 #address-cells = <1>;
561 #size-cells = <0>;
562 compatible = "samsung,s3c2440-hdmiphy-i2c";
563 reg = <0x138E0000 0x100>;
564 interrupts = <0 93 0>;
565 clocks = <&clock CLK_I2C_HDMI>;
566 clock-names = "i2c";
567 status = "disabled";
568
569 hdmi_i2c_phy: hdmiphy@38 {
570 compatible = "exynos4210-hdmiphy";
571 reg = <0x38>;
572 };
573 };
574
557 spi_0: spi@13920000 { 575 spi_0: spi@13920000 {
558 compatible = "samsung,exynos4210-spi"; 576 compatible = "samsung,exynos4210-spi";
559 reg = <0x13920000 0x100>; 577 reg = <0x13920000 0x100>;
@@ -663,6 +681,33 @@
663 status = "disabled"; 681 status = "disabled";
664 }; 682 };
665 683
684 tmu: tmu@100C0000 {
685 #include "exynos4412-tmu-sensor-conf.dtsi"
686 };
687
688 hdmi: hdmi@12D00000 {
689 compatible = "samsung,exynos4210-hdmi";
690 reg = <0x12D00000 0x70000>;
691 interrupts = <0 92 0>;
692 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
693 "mout_hdmi";
694 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
695 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
696 <&clock CLK_MOUT_HDMI>;
697 phy = <&hdmi_i2c_phy>;
698 power-domains = <&pd_tv>;
699 samsung,syscon-phandle = <&pmu_system_controller>;
700 status = "disabled";
701 };
702
703 mixer: mixer@12C10000 {
704 compatible = "samsung,exynos4210-mixer";
705 interrupts = <0 91 0>;
706 reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
707 power-domains = <&pd_tv>;
708 status = "disabled";
709 };
710
666 ppmu_dmc0: ppmu_dmc0@106a0000 { 711 ppmu_dmc0: ppmu_dmc0@106a0000 {
667 compatible = "samsung,exynos-ppmu"; 712 compatible = "samsung,exynos-ppmu";
668 reg = <0x106a0000 0x2000>; 713 reg = <0x106a0000 0x2000>;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 3d6652a4b6cb..32c5fd8f6269 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -426,6 +426,25 @@
426 status = "okay"; 426 status = "okay";
427 }; 427 };
428 428
429 tmu@100C0000 {
430 status = "okay";
431 };
432
433 thermal-zones {
434 cpu_thermal: cpu-thermal {
435 cooling-maps {
436 map0 {
437 /* Corresponds to 800MHz at freq_table */
438 cooling-device = <&cpu0 2 2>;
439 };
440 map1 {
441 /* Corresponds to 200MHz at freq_table */
442 cooling-device = <&cpu0 4 4>;
443 };
444 };
445 };
446 };
447
429 camera { 448 camera {
430 pinctrl-names = "default"; 449 pinctrl-names = "default";
431 pinctrl-0 = <>; 450 pinctrl-0 = <>;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index b57e6b82ea20..d4f2b11319dd 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -505,6 +505,63 @@
505 assigned-clock-rates = <0>, <160000000>; 505 assigned-clock-rates = <0>, <160000000>;
506 }; 506 };
507 }; 507 };
508
509 hdmi_en: voltage-regulator-hdmi-5v {
510 compatible = "regulator-fixed";
511 regulator-name = "HDMI_5V";
512 regulator-min-microvolt = <5000000>;
513 regulator-max-microvolt = <5000000>;
514 gpio = <&gpe0 1 0>;
515 enable-active-high;
516 };
517
518 hdmi_ddc: i2c-ddc {
519 compatible = "i2c-gpio";
520 gpios = <&gpe4 2 0 &gpe4 3 0>;
521 i2c-gpio,delay-us = <100>;
522 #address-cells = <1>;
523 #size-cells = <0>;
524
525 pinctrl-0 = <&i2c_ddc_bus>;
526 pinctrl-names = "default";
527 status = "okay";
528 };
529
530 mixer@12C10000 {
531 status = "okay";
532 };
533
534 hdmi@12D00000 {
535 hpd-gpio = <&gpx3 7 0>;
536 pinctrl-names = "default";
537 pinctrl-0 = <&hdmi_hpd>;
538 hdmi-en-supply = <&hdmi_en>;
539 vdd-supply = <&ldo3_reg>;
540 vdd_osc-supply = <&ldo4_reg>;
541 vdd_pll-supply = <&ldo3_reg>;
542 ddc = <&hdmi_ddc>;
543 status = "okay";
544 };
545
546 i2c@138E0000 {
547 status = "okay";
548 };
549};
550
551&pinctrl_1 {
552 hdmi_hpd: hdmi-hpd {
553 samsung,pins = "gpx3-7";
554 samsung,pin-pud = <0>;
555 };
556};
557
558&pinctrl_0 {
559 i2c_ddc_bus: i2c-ddc-bus {
560 samsung,pins = "gpe4-2", "gpe4-3";
561 samsung,pin-function = <2>;
562 samsung,pin-pud = <3>;
563 samsung,pin-drv = <0>;
564 };
508}; 565};
509 566
510&mdma1 { 567&mdma1 {
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 67c832c9dcf1..be89f83f70e7 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -21,6 +21,7 @@
21 21
22#include "exynos4.dtsi" 22#include "exynos4.dtsi"
23#include "exynos4210-pinctrl.dtsi" 23#include "exynos4210-pinctrl.dtsi"
24#include "exynos4-cpu-thermal.dtsi"
24 25
25/ { 26/ {
26 compatible = "samsung,exynos4210", "samsung,exynos4"; 27 compatible = "samsung,exynos4210", "samsung,exynos4";
@@ -35,10 +36,13 @@
35 #address-cells = <1>; 36 #address-cells = <1>;
36 #size-cells = <0>; 37 #size-cells = <0>;
37 38
38 cpu@900 { 39 cpu0: cpu@900 {
39 device_type = "cpu"; 40 device_type = "cpu";
40 compatible = "arm,cortex-a9"; 41 compatible = "arm,cortex-a9";
41 reg = <0x900>; 42 reg = <0x900>;
43 cooling-min-level = <4>;
44 cooling-max-level = <2>;
45 #cooling-cells = <2>; /* min followed by max */
42 }; 46 };
43 47
44 cpu@901 { 48 cpu@901 {
@@ -153,16 +157,38 @@
153 reg = <0x03860000 0x1000>; 157 reg = <0x03860000 0x1000>;
154 }; 158 };
155 159
156 tmu@100C0000 { 160 tmu: tmu@100C0000 {
157 compatible = "samsung,exynos4210-tmu"; 161 compatible = "samsung,exynos4210-tmu";
158 interrupt-parent = <&combiner>; 162 interrupt-parent = <&combiner>;
159 reg = <0x100C0000 0x100>; 163 reg = <0x100C0000 0x100>;
160 interrupts = <2 4>; 164 interrupts = <2 4>;
161 clocks = <&clock CLK_TMU_APBIF>; 165 clocks = <&clock CLK_TMU_APBIF>;
162 clock-names = "tmu_apbif"; 166 clock-names = "tmu_apbif";
167 samsung,tmu_gain = <15>;
168 samsung,tmu_reference_voltage = <7>;
163 status = "disabled"; 169 status = "disabled";
164 }; 170 };
165 171
172 thermal-zones {
173 cpu_thermal: cpu-thermal {
174 polling-delay-passive = <0>;
175 polling-delay = <0>;
176 thermal-sensors = <&tmu 0>;
177
178 trips {
179 cpu_alert0: cpu-alert-0 {
180 temperature = <85000>; /* millicelsius */
181 };
182 cpu_alert1: cpu-alert-1 {
183 temperature = <100000>; /* millicelsius */
184 };
185 cpu_alert2: cpu-alert-2 {
186 temperature = <110000>; /* millicelsius */
187 };
188 };
189 };
190 };
191
166 g2d@12800000 { 192 g2d@12800000 {
167 compatible = "samsung,s5pv210-g2d"; 193 compatible = "samsung,s5pv210-g2d";
168 reg = <0x12800000 0x1000>; 194 reg = <0x12800000 0x1000>;
@@ -203,6 +229,14 @@
203 }; 229 };
204 }; 230 };
205 231
232 mixer: mixer@12C10000 {
233 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
234 "sclk_mixer";
235 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
236 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
237 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
238 };
239
206 ppmu_lcd1: ppmu_lcd1@12240000 { 240 ppmu_lcd1: ppmu_lcd1@12240000 {
207 compatible = "samsung,exynos-ppmu"; 241 compatible = "samsung,exynos-ppmu";
208 reg = <0x12240000 0x2000>; 242 reg = <0x12240000 0x2000>;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index dd0a43ec56da..5be03288f1ee 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -26,10 +26,13 @@
26 #address-cells = <1>; 26 #address-cells = <1>;
27 #size-cells = <0>; 27 #size-cells = <0>;
28 28
29 cpu@A00 { 29 cpu0: cpu@A00 {
30 device_type = "cpu"; 30 device_type = "cpu";
31 compatible = "arm,cortex-a9"; 31 compatible = "arm,cortex-a9";
32 reg = <0xA00>; 32 reg = <0xA00>;
33 cooling-min-level = <13>;
34 cooling-max-level = <7>;
35 #cooling-cells = <2>; /* min followed by max */
33 }; 36 };
34 37
35 cpu@A01 { 38 cpu@A01 {
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index de80b5bba204..adb4f6a97a1d 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -249,6 +249,20 @@
249 regulator-always-on; 249 regulator-always-on;
250 }; 250 };
251 251
252 ldo8_reg: ldo@8 {
253 regulator-compatible = "LDO8";
254 regulator-name = "VDD10_HDMI_1.0V";
255 regulator-min-microvolt = <1000000>;
256 regulator-max-microvolt = <1000000>;
257 };
258
259 ldo10_reg: ldo@10 {
260 regulator-compatible = "LDO10";
261 regulator-name = "VDDQ_MIPIHSI_1.8V";
262 regulator-min-microvolt = <1800000>;
263 regulator-max-microvolt = <1800000>;
264 };
265
252 ldo11_reg: LDO11 { 266 ldo11_reg: LDO11 {
253 regulator-name = "VDD18_ABB1_1.8V"; 267 regulator-name = "VDD18_ABB1_1.8V";
254 regulator-min-microvolt = <1800000>; 268 regulator-min-microvolt = <1800000>;
@@ -411,6 +425,51 @@
411 ehci: ehci@12580000 { 425 ehci: ehci@12580000 {
412 status = "okay"; 426 status = "okay";
413 }; 427 };
428
429 tmu@100C0000 {
430 vtmu-supply = <&ldo10_reg>;
431 status = "okay";
432 };
433
434 thermal-zones {
435 cpu_thermal: cpu-thermal {
436 cooling-maps {
437 map0 {
438 /* Corresponds to 800MHz at freq_table */
439 cooling-device = <&cpu0 7 7>;
440 };
441 map1 {
442 /* Corresponds to 200MHz at freq_table */
443 cooling-device = <&cpu0 13 13>;
444 };
445 };
446 };
447 };
448
449 mixer: mixer@12C10000 {
450 status = "okay";
451 };
452
453 hdmi@12D00000 {
454 hpd-gpio = <&gpx3 7 0>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&hdmi_hpd>;
457 vdd-supply = <&ldo8_reg>;
458 vdd_osc-supply = <&ldo10_reg>;
459 vdd_pll-supply = <&ldo8_reg>;
460 ddc = <&hdmi_ddc>;
461 status = "okay";
462 };
463
464 hdmi_ddc: i2c@13880000 {
465 status = "okay";
466 pinctrl-names = "default";
467 pinctrl-0 = <&i2c2_bus>;
468 };
469
470 i2c@138E0000 {
471 status = "okay";
472 };
414}; 473};
415 474
416&pinctrl_1 { 475&pinctrl_1 {
@@ -425,4 +484,9 @@
425 samsung,pin-pud = <0>; 484 samsung,pin-pud = <0>;
426 samsung,pin-drv = <0>; 485 samsung,pin-drv = <0>;
427 }; 486 };
487
488 hdmi_hpd: hdmi-hpd {
489 samsung,pins = "gpx3-7";
490 samsung,pin-pud = <1>;
491 };
428}; 492};
diff --git a/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi b/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi
new file mode 100644
index 000000000000..e3f7934d19d0
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi
@@ -0,0 +1,24 @@
1/*
2 * Device tree sources for Exynos4412 TMU sensor configuration
3 *
4 * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <dt-bindings/thermal/thermal_exynos.h>
13
14#thermal-sensor-cells = <0>;
15samsung,tmu_gain = <8>;
16samsung,tmu_reference_voltage = <16>;
17samsung,tmu_noise_cancel_mode = <4>;
18samsung,tmu_efuse_value = <55>;
19samsung,tmu_min_efuse_value = <40>;
20samsung,tmu_max_efuse_value = <100>;
21samsung,tmu_first_point_trim = <25>;
22samsung,tmu_second_point_trim = <85>;
23samsung,tmu_default_temp_offset = <50>;
24samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>;
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 21f748083586..173ffa479ad3 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -927,6 +927,21 @@
927 pulldown-ohm = <100000>; /* 100K */ 927 pulldown-ohm = <100000>; /* 100K */
928 io-channels = <&adc 2>; /* Battery temperature */ 928 io-channels = <&adc 2>; /* Battery temperature */
929 }; 929 };
930
931 thermal-zones {
932 cpu_thermal: cpu-thermal {
933 cooling-maps {
934 map0 {
935 /* Corresponds to 800MHz at freq_table */
936 cooling-device = <&cpu0 7 7>;
937 };
938 map1 {
939 /* Corresponds to 200MHz at freq_table */
940 cooling-device = <&cpu0 13 13>;
941 };
942 };
943 };
944 };
930}; 945};
931 946
932&pmu_system_controller { 947&pmu_system_controller {
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 0f6ec93bb1d8..68ad43b391ae 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -26,10 +26,13 @@
26 #address-cells = <1>; 26 #address-cells = <1>;
27 #size-cells = <0>; 27 #size-cells = <0>;
28 28
29 cpu@A00 { 29 cpu0: cpu@A00 {
30 device_type = "cpu"; 30 device_type = "cpu";
31 compatible = "arm,cortex-a9"; 31 compatible = "arm,cortex-a9";
32 reg = <0xA00>; 32 reg = <0xA00>;
33 cooling-min-level = <13>;
34 cooling-max-level = <7>;
35 #cooling-cells = <2>; /* min followed by max */
33 }; 36 };
34 37
35 cpu@A01 { 38 cpu@A01 {
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index f5e0ae780d6c..6a6abe14fd9b 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -19,6 +19,7 @@
19 19
20#include "exynos4.dtsi" 20#include "exynos4.dtsi"
21#include "exynos4x12-pinctrl.dtsi" 21#include "exynos4x12-pinctrl.dtsi"
22#include "exynos4-cpu-thermal.dtsi"
22 23
23/ { 24/ {
24 aliases { 25 aliases {
@@ -297,4 +298,15 @@
297 clock-names = "tmu_apbif"; 298 clock-names = "tmu_apbif";
298 status = "disabled"; 299 status = "disabled";
299 }; 300 };
301
302 hdmi: hdmi@12D00000 {
303 compatible = "samsung,exynos4212-hdmi";
304 };
305
306 mixer: mixer@12C10000 {
307 compatible = "samsung,exynos4212-mixer";
308 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
309 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
310 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
311 };
300}; 312};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 9bb1b0b738f5..adbde1adad95 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -20,7 +20,7 @@
20#include <dt-bindings/clock/exynos5250.h> 20#include <dt-bindings/clock/exynos5250.h>
21#include "exynos5.dtsi" 21#include "exynos5.dtsi"
22#include "exynos5250-pinctrl.dtsi" 22#include "exynos5250-pinctrl.dtsi"
23 23#include "exynos4-cpu-thermal.dtsi"
24#include <dt-bindings/clock/exynos-audss-clk.h> 24#include <dt-bindings/clock/exynos-audss-clk.h>
25 25
26/ { 26/ {
@@ -58,11 +58,14 @@
58 #address-cells = <1>; 58 #address-cells = <1>;
59 #size-cells = <0>; 59 #size-cells = <0>;
60 60
61 cpu@0 { 61 cpu0: cpu@0 {
62 device_type = "cpu"; 62 device_type = "cpu";
63 compatible = "arm,cortex-a15"; 63 compatible = "arm,cortex-a15";
64 reg = <0>; 64 reg = <0>;
65 clock-frequency = <1700000000>; 65 clock-frequency = <1700000000>;
66 cooling-min-level = <15>;
67 cooling-max-level = <9>;
68 #cooling-cells = <2>; /* min followed by max */
66 }; 69 };
67 cpu@1 { 70 cpu@1 {
68 device_type = "cpu"; 71 device_type = "cpu";
@@ -102,6 +105,12 @@
102 #power-domain-cells = <0>; 105 #power-domain-cells = <0>;
103 }; 106 };
104 107
108 pd_disp1: disp1-power-domain@100440A0 {
109 compatible = "samsung,exynos4210-pd";
110 reg = <0x100440A0 0x20>;
111 #power-domain-cells = <0>;
112 };
113
105 clock: clock-controller@10010000 { 114 clock: clock-controller@10010000 {
106 compatible = "samsung,exynos5250-clock"; 115 compatible = "samsung,exynos5250-clock";
107 reg = <0x10010000 0x30000>; 116 reg = <0x10010000 0x30000>;
@@ -235,12 +244,32 @@
235 status = "disabled"; 244 status = "disabled";
236 }; 245 };
237 246
238 tmu@10060000 { 247 tmu: tmu@10060000 {
239 compatible = "samsung,exynos5250-tmu"; 248 compatible = "samsung,exynos5250-tmu";
240 reg = <0x10060000 0x100>; 249 reg = <0x10060000 0x100>;
241 interrupts = <0 65 0>; 250 interrupts = <0 65 0>;
242 clocks = <&clock CLK_TMU>; 251 clocks = <&clock CLK_TMU>;
243 clock-names = "tmu_apbif"; 252 clock-names = "tmu_apbif";
253 #include "exynos4412-tmu-sensor-conf.dtsi"
254 };
255
256 thermal-zones {
257 cpu_thermal: cpu-thermal {
258 polling-delay-passive = <0>;
259 polling-delay = <0>;
260 thermal-sensors = <&tmu 0>;
261
262 cooling-maps {
263 map0 {
264 /* Corresponds to 800MHz at freq_table */
265 cooling-device = <&cpu0 9 9>;
266 };
267 map1 {
268 /* Corresponds to 200MHz at freq_table */
269 cooling-device = <&cpu0 15 15>;
270 };
271 };
272 };
244 }; 273 };
245 274
246 serial@12C00000 { 275 serial@12C00000 {
@@ -719,6 +748,7 @@
719 hdmi: hdmi { 748 hdmi: hdmi {
720 compatible = "samsung,exynos4212-hdmi"; 749 compatible = "samsung,exynos4212-hdmi";
721 reg = <0x14530000 0x70000>; 750 reg = <0x14530000 0x70000>;
751 power-domains = <&pd_disp1>;
722 interrupts = <0 95 0>; 752 interrupts = <0 95 0>;
723 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 753 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
724 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 754 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
@@ -731,9 +761,11 @@
731 mixer { 761 mixer {
732 compatible = "samsung,exynos5250-mixer"; 762 compatible = "samsung,exynos5250-mixer";
733 reg = <0x14450000 0x10000>; 763 reg = <0x14450000 0x10000>;
764 power-domains = <&pd_disp1>;
734 interrupts = <0 94 0>; 765 interrupts = <0 94 0>;
735 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; 766 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
736 clock-names = "mixer", "sclk_hdmi"; 767 <&clock CLK_SCLK_HDMI>;
768 clock-names = "mixer", "hdmi", "sclk_hdmi";
737 }; 769 };
738 770
739 dp_phy: video-phy@10040720 { 771 dp_phy: video-phy@10040720 {
@@ -743,6 +775,7 @@
743 }; 775 };
744 776
745 dp: dp-controller@145B0000 { 777 dp: dp-controller@145B0000 {
778 power-domains = <&pd_disp1>;
746 clocks = <&clock CLK_DP>; 779 clocks = <&clock CLK_DP>;
747 clock-names = "dp"; 780 clock-names = "dp";
748 phys = <&dp_phy>; 781 phys = <&dp_phy>;
@@ -750,6 +783,7 @@
750 }; 783 };
751 784
752 fimd: fimd@14400000 { 785 fimd: fimd@14400000 {
786 power-domains = <&pd_disp1>;
753 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 787 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
754 clock-names = "sclk_fimd", "fimd"; 788 clock-names = "sclk_fimd", "fimd";
755 }; 789 };
diff --git a/arch/arm/boot/dts/exynos5420-trip-points.dtsi b/arch/arm/boot/dts/exynos5420-trip-points.dtsi
new file mode 100644
index 000000000000..5d31fc140823
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-trip-points.dtsi
@@ -0,0 +1,35 @@
1/*
2 * Device tree sources for default Exynos5420 thermal zone definition
3 *
4 * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12polling-delay-passive = <0>;
13polling-delay = <0>;
14trips {
15 cpu-alert-0 {
16 temperature = <85000>; /* millicelsius */
17 hysteresis = <10000>; /* millicelsius */
18 type = "active";
19 };
20 cpu-alert-1 {
21 temperature = <103000>; /* millicelsius */
22 hysteresis = <10000>; /* millicelsius */
23 type = "active";
24 };
25 cpu-alert-2 {
26 temperature = <110000>; /* millicelsius */
27 hysteresis = <10000>; /* millicelsius */
28 type = "active";
29 };
30 cpu-crit-0 {
31 temperature = <1200000>; /* millicelsius */
32 hysteresis = <0>; /* millicelsius */
33 type = "critical";
34 };
35};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 9dc2e9773b30..c0e98cf3514f 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -740,8 +740,9 @@
740 compatible = "samsung,exynos5420-mixer"; 740 compatible = "samsung,exynos5420-mixer";
741 reg = <0x14450000 0x10000>; 741 reg = <0x14450000 0x10000>;
742 interrupts = <0 94 0>; 742 interrupts = <0 94 0>;
743 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; 743 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
744 clock-names = "mixer", "sclk_hdmi"; 744 <&clock CLK_SCLK_HDMI>;
745 clock-names = "mixer", "hdmi", "sclk_hdmi";
745 power-domains = <&disp_pd>; 746 power-domains = <&disp_pd>;
746 }; 747 };
747 748
@@ -782,6 +783,7 @@
782 interrupts = <0 65 0>; 783 interrupts = <0 65 0>;
783 clocks = <&clock CLK_TMU>; 784 clocks = <&clock CLK_TMU>;
784 clock-names = "tmu_apbif"; 785 clock-names = "tmu_apbif";
786 #include "exynos4412-tmu-sensor-conf.dtsi"
785 }; 787 };
786 788
787 tmu_cpu1: tmu@10064000 { 789 tmu_cpu1: tmu@10064000 {
@@ -790,6 +792,7 @@
790 interrupts = <0 183 0>; 792 interrupts = <0 183 0>;
791 clocks = <&clock CLK_TMU>; 793 clocks = <&clock CLK_TMU>;
792 clock-names = "tmu_apbif"; 794 clock-names = "tmu_apbif";
795 #include "exynos4412-tmu-sensor-conf.dtsi"
793 }; 796 };
794 797
795 tmu_cpu2: tmu@10068000 { 798 tmu_cpu2: tmu@10068000 {
@@ -798,6 +801,7 @@
798 interrupts = <0 184 0>; 801 interrupts = <0 184 0>;
799 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; 802 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
800 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 803 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
804 #include "exynos4412-tmu-sensor-conf.dtsi"
801 }; 805 };
802 806
803 tmu_cpu3: tmu@1006c000 { 807 tmu_cpu3: tmu@1006c000 {
@@ -806,6 +810,7 @@
806 interrupts = <0 185 0>; 810 interrupts = <0 185 0>;
807 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; 811 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
808 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 812 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
813 #include "exynos4412-tmu-sensor-conf.dtsi"
809 }; 814 };
810 815
811 tmu_gpu: tmu@100a0000 { 816 tmu_gpu: tmu@100a0000 {
@@ -814,6 +819,30 @@
814 interrupts = <0 215 0>; 819 interrupts = <0 215 0>;
815 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; 820 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
816 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 821 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
822 #include "exynos4412-tmu-sensor-conf.dtsi"
823 };
824
825 thermal-zones {
826 cpu0_thermal: cpu0-thermal {
827 thermal-sensors = <&tmu_cpu0>;
828 #include "exynos5420-trip-points.dtsi"
829 };
830 cpu1_thermal: cpu1-thermal {
831 thermal-sensors = <&tmu_cpu1>;
832 #include "exynos5420-trip-points.dtsi"
833 };
834 cpu2_thermal: cpu2-thermal {
835 thermal-sensors = <&tmu_cpu2>;
836 #include "exynos5420-trip-points.dtsi"
837 };
838 cpu3_thermal: cpu3-thermal {
839 thermal-sensors = <&tmu_cpu3>;
840 #include "exynos5420-trip-points.dtsi"
841 };
842 gpu_thermal: gpu-thermal {
843 thermal-sensors = <&tmu_gpu>;
844 #include "exynos5420-trip-points.dtsi"
845 };
817 }; 846 };
818 847
819 watchdog: watchdog@101D0000 { 848 watchdog: watchdog@101D0000 {
diff --git a/arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi b/arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi
new file mode 100644
index 000000000000..7b2fba0ae92b
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi
@@ -0,0 +1,24 @@
1/*
2 * Device tree sources for Exynos5440 TMU sensor configuration
3 *
4 * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <dt-bindings/thermal/thermal_exynos.h>
13
14#thermal-sensor-cells = <0>;
15samsung,tmu_gain = <5>;
16samsung,tmu_reference_voltage = <16>;
17samsung,tmu_noise_cancel_mode = <4>;
18samsung,tmu_efuse_value = <0x5d2d>;
19samsung,tmu_min_efuse_value = <16>;
20samsung,tmu_max_efuse_value = <76>;
21samsung,tmu_first_point_trim = <25>;
22samsung,tmu_second_point_trim = <70>;
23samsung,tmu_default_temp_offset = <25>;
24samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>;
diff --git a/arch/arm/boot/dts/exynos5440-trip-points.dtsi b/arch/arm/boot/dts/exynos5440-trip-points.dtsi
new file mode 100644
index 000000000000..48adfa8f4300
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5440-trip-points.dtsi
@@ -0,0 +1,25 @@
1/*
2 * Device tree sources for default Exynos5440 thermal zone definition
3 *
4 * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12polling-delay-passive = <0>;
13polling-delay = <0>;
14trips {
15 cpu-alert-0 {
16 temperature = <100000>; /* millicelsius */
17 hysteresis = <0>; /* millicelsius */
18 type = "active";
19 };
20 cpu-crit-0 {
21 temperature = <1050000>; /* millicelsius */
22 hysteresis = <0>; /* millicelsius */
23 type = "critical";
24 };
25};
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 8f3373cd7b87..59d9416b3b03 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -219,6 +219,7 @@
219 interrupts = <0 58 0>; 219 interrupts = <0 58 0>;
220 clocks = <&clock CLK_B_125>; 220 clocks = <&clock CLK_B_125>;
221 clock-names = "tmu_apbif"; 221 clock-names = "tmu_apbif";
222 #include "exynos5440-tmu-sensor-conf.dtsi"
222 }; 223 };
223 224
224 tmuctrl_1: tmuctrl@16011C { 225 tmuctrl_1: tmuctrl@16011C {
@@ -227,6 +228,7 @@
227 interrupts = <0 58 0>; 228 interrupts = <0 58 0>;
228 clocks = <&clock CLK_B_125>; 229 clocks = <&clock CLK_B_125>;
229 clock-names = "tmu_apbif"; 230 clock-names = "tmu_apbif";
231 #include "exynos5440-tmu-sensor-conf.dtsi"
230 }; 232 };
231 233
232 tmuctrl_2: tmuctrl@160120 { 234 tmuctrl_2: tmuctrl@160120 {
@@ -235,6 +237,22 @@
235 interrupts = <0 58 0>; 237 interrupts = <0 58 0>;
236 clocks = <&clock CLK_B_125>; 238 clocks = <&clock CLK_B_125>;
237 clock-names = "tmu_apbif"; 239 clock-names = "tmu_apbif";
240 #include "exynos5440-tmu-sensor-conf.dtsi"
241 };
242
243 thermal-zones {
244 cpu0_thermal: cpu0-thermal {
245 thermal-sensors = <&tmuctrl_0>;
246 #include "exynos5440-trip-points.dtsi"
247 };
248 cpu1_thermal: cpu1-thermal {
249 thermal-sensors = <&tmuctrl_1>;
250 #include "exynos5440-trip-points.dtsi"
251 };
252 cpu2_thermal: cpu2-thermal {
253 thermal-sensors = <&tmuctrl_2>;
254 #include "exynos5440-trip-points.dtsi"
255 };
238 }; 256 };
239 257
240 sata@210000 { 258 sata@210000 {
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index f1cd2147421d..a626e6dd8022 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -35,6 +35,7 @@
35 regulator-max-microvolt = <5000000>; 35 regulator-max-microvolt = <5000000>;
36 gpio = <&gpio3 22 0>; 36 gpio = <&gpio3 22 0>;
37 enable-active-high; 37 enable-active-high;
38 vin-supply = <&swbst_reg>;
38 }; 39 };
39 40
40 reg_usb_h1_vbus: regulator@1 { 41 reg_usb_h1_vbus: regulator@1 {
@@ -45,6 +46,7 @@
45 regulator-max-microvolt = <5000000>; 46 regulator-max-microvolt = <5000000>;
46 gpio = <&gpio1 29 0>; 47 gpio = <&gpio1 29 0>;
47 enable-active-high; 48 enable-active-high;
49 vin-supply = <&swbst_reg>;
48 }; 50 };
49 51
50 reg_audio: regulator@2 { 52 reg_audio: regulator@2 {
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index fda4932faefd..945887d3fdb3 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -52,6 +52,7 @@
52 regulator-max-microvolt = <5000000>; 52 regulator-max-microvolt = <5000000>;
53 gpio = <&gpio4 0 0>; 53 gpio = <&gpio4 0 0>;
54 enable-active-high; 54 enable-active-high;
55 vin-supply = <&swbst_reg>;
55 }; 56 };
56 57
57 reg_usb_otg2_vbus: regulator@1 { 58 reg_usb_otg2_vbus: regulator@1 {
@@ -62,6 +63,7 @@
62 regulator-max-microvolt = <5000000>; 63 regulator-max-microvolt = <5000000>;
63 gpio = <&gpio4 2 0>; 64 gpio = <&gpio4 2 0>;
64 enable-active-high; 65 enable-active-high;
66 vin-supply = <&swbst_reg>;
65 }; 67 };
66 68
67 reg_aud3v: regulator@2 { 69 reg_aud3v: regulator@2 {
diff --git a/arch/arm/boot/dts/omap5-core-thermal.dtsi b/arch/arm/boot/dts/omap5-core-thermal.dtsi
index 19212ac6eef0..de8a3d456cf7 100644
--- a/arch/arm/boot/dts/omap5-core-thermal.dtsi
+++ b/arch/arm/boot/dts/omap5-core-thermal.dtsi
@@ -13,7 +13,7 @@
13 13
14core_thermal: core_thermal { 14core_thermal: core_thermal {
15 polling-delay-passive = <250>; /* milliseconds */ 15 polling-delay-passive = <250>; /* milliseconds */
16 polling-delay = <1000>; /* milliseconds */ 16 polling-delay = <500>; /* milliseconds */
17 17
18 /* sensor ID */ 18 /* sensor ID */
19 thermal-sensors = <&bandgap 2>; 19 thermal-sensors = <&bandgap 2>;
diff --git a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi b/arch/arm/boot/dts/omap5-gpu-thermal.dtsi
index 1b87aca88b77..bc3090f2e84b 100644
--- a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi
+++ b/arch/arm/boot/dts/omap5-gpu-thermal.dtsi
@@ -13,7 +13,7 @@
13 13
14gpu_thermal: gpu_thermal { 14gpu_thermal: gpu_thermal {
15 polling-delay-passive = <250>; /* milliseconds */ 15 polling-delay-passive = <250>; /* milliseconds */
16 polling-delay = <1000>; /* milliseconds */ 16 polling-delay = <500>; /* milliseconds */
17 17
18 /* sensor ID */ 18 /* sensor ID */
19 thermal-sensors = <&bandgap 1>; 19 thermal-sensors = <&bandgap 1>;
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index ddff674bd05e..4a485b63a141 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -1079,4 +1079,8 @@
1079 }; 1079 };
1080}; 1080};
1081 1081
1082&cpu_thermal {
1083 polling-delay = <500>; /* milliseconds */
1084};
1085
1082/include/ "omap54xx-clocks.dtsi" 1086/include/ "omap54xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 58c27466f012..83b425fb3ac2 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -167,10 +167,18 @@
167 ti,index-starts-at-one; 167 ti,index-starts-at-one;
168 }; 168 };
169 169
170 dpll_core_byp_mux: dpll_core_byp_mux {
171 #clock-cells = <0>;
172 compatible = "ti,mux-clock";
173 clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
174 ti,bit-shift = <23>;
175 reg = <0x012c>;
176 };
177
170 dpll_core_ck: dpll_core_ck { 178 dpll_core_ck: dpll_core_ck {
171 #clock-cells = <0>; 179 #clock-cells = <0>;
172 compatible = "ti,omap4-dpll-core-clock"; 180 compatible = "ti,omap4-dpll-core-clock";
173 clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; 181 clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
174 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; 182 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
175 }; 183 };
176 184
@@ -294,10 +302,18 @@
294 clock-div = <1>; 302 clock-div = <1>;
295 }; 303 };
296 304
305 dpll_iva_byp_mux: dpll_iva_byp_mux {
306 #clock-cells = <0>;
307 compatible = "ti,mux-clock";
308 clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
309 ti,bit-shift = <23>;
310 reg = <0x01ac>;
311 };
312
297 dpll_iva_ck: dpll_iva_ck { 313 dpll_iva_ck: dpll_iva_ck {
298 #clock-cells = <0>; 314 #clock-cells = <0>;
299 compatible = "ti,omap4-dpll-clock"; 315 compatible = "ti,omap4-dpll-clock";
300 clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; 316 clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
301 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; 317 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
302 }; 318 };
303 319
@@ -599,10 +615,19 @@
599 }; 615 };
600}; 616};
601&cm_core_clocks { 617&cm_core_clocks {
618
619 dpll_per_byp_mux: dpll_per_byp_mux {
620 #clock-cells = <0>;
621 compatible = "ti,mux-clock";
622 clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
623 ti,bit-shift = <23>;
624 reg = <0x014c>;
625 };
626
602 dpll_per_ck: dpll_per_ck { 627 dpll_per_ck: dpll_per_ck {
603 #clock-cells = <0>; 628 #clock-cells = <0>;
604 compatible = "ti,omap4-dpll-clock"; 629 compatible = "ti,omap4-dpll-clock";
605 clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; 630 clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
606 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; 631 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
607 }; 632 };
608 633
@@ -714,10 +739,18 @@
714 ti,index-starts-at-one; 739 ti,index-starts-at-one;
715 }; 740 };
716 741
742 dpll_usb_byp_mux: dpll_usb_byp_mux {
743 #clock-cells = <0>;
744 compatible = "ti,mux-clock";
745 clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
746 ti,bit-shift = <23>;
747 reg = <0x018c>;
748 };
749
717 dpll_usb_ck: dpll_usb_ck { 750 dpll_usb_ck: dpll_usb_ck {
718 #clock-cells = <0>; 751 #clock-cells = <0>;
719 compatible = "ti,omap4-dpll-j-type-clock"; 752 compatible = "ti,omap4-dpll-j-type-clock";
720 clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; 753 clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
721 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; 754 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
722 }; 755 };
723 756
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 261311bdf65b..367af53c1b84 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1248,7 +1248,6 @@
1248 atmel,watchdog-type = "hardware"; 1248 atmel,watchdog-type = "hardware";
1249 atmel,reset-type = "all"; 1249 atmel,reset-type = "all";
1250 atmel,dbg-halt; 1250 atmel,dbg-halt;
1251 atmel,idle-halt;
1252 status = "disabled"; 1251 status = "disabled";
1253 }; 1252 };
1254 1253
@@ -1416,7 +1415,7 @@
1416 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1415 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1417 reg = <0x00700000 0x100000>; 1416 reg = <0x00700000 0x100000>;
1418 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; 1417 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
1419 clocks = <&usb>, <&uhphs_clk>, <&uhpck>; 1418 clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
1420 clock-names = "usb_clk", "ehci_clk", "uhpck"; 1419 clock-names = "usb_clk", "ehci_clk", "uhpck";
1421 status = "disabled"; 1420 status = "disabled";
1422 }; 1421 };
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index d986b41b9654..4303874889c6 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -66,6 +66,7 @@
66 gpio4 = &pioE; 66 gpio4 = &pioE;
67 tcb0 = &tcb0; 67 tcb0 = &tcb0;
68 tcb1 = &tcb1; 68 tcb1 = &tcb1;
69 i2c0 = &i2c0;
69 i2c2 = &i2c2; 70 i2c2 = &i2c2;
70 }; 71 };
71 cpus { 72 cpus {
@@ -259,7 +260,7 @@
259 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 260 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
260 reg = <0x00600000 0x100000>; 261 reg = <0x00600000 0x100000>;
261 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; 262 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
262 clocks = <&usb>, <&uhphs_clk>, <&uhpck>; 263 clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
263 clock-names = "usb_clk", "ehci_clk", "uhpck"; 264 clock-names = "usb_clk", "ehci_clk", "uhpck";
264 status = "disabled"; 265 status = "disabled";
265 }; 266 };
@@ -461,8 +462,8 @@
461 462
462 lcdck: lcdck { 463 lcdck: lcdck {
463 #clock-cells = <0>; 464 #clock-cells = <0>;
464 reg = <4>; 465 reg = <3>;
465 clocks = <&smd>; 466 clocks = <&mck>;
466 }; 467 };
467 468
468 smdck: smdck { 469 smdck: smdck {
@@ -770,7 +771,7 @@
770 reg = <50>; 771 reg = <50>;
771 }; 772 };
772 773
773 lcd_clk: lcd_clk { 774 lcdc_clk: lcdc_clk {
774 #clock-cells = <0>; 775 #clock-cells = <0>;
775 reg = <51>; 776 reg = <51>;
776 }; 777 };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 252c3d1bda50..9d8760956752 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -713,6 +713,9 @@
713 reg-shift = <2>; 713 reg-shift = <2>;
714 reg-io-width = <4>; 714 reg-io-width = <4>;
715 clocks = <&l4_sp_clk>; 715 clocks = <&l4_sp_clk>;
716 dmas = <&pdma 28>,
717 <&pdma 29>;
718 dma-names = "tx", "rx";
716 }; 719 };
717 720
718 uart1: serial1@ffc03000 { 721 uart1: serial1@ffc03000 {
@@ -722,6 +725,9 @@
722 reg-shift = <2>; 725 reg-shift = <2>;
723 reg-io-width = <4>; 726 reg-io-width = <4>;
724 clocks = <&l4_sp_clk>; 727 clocks = <&l4_sp_clk>;
728 dmas = <&pdma 30>,
729 <&pdma 31>;
730 dma-names = "tx", "rx";
725 }; 731 };
726 732
727 rst: rstmgr@ffd05000 { 733 rst: rstmgr@ffd05000 {
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index f2670f638e97..811e72bbe642 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -70,6 +70,7 @@ CONFIG_SCSI=y
70CONFIG_BLK_DEV_SD=y 70CONFIG_BLK_DEV_SD=y
71# CONFIG_SCSI_LOWLEVEL is not set 71# CONFIG_SCSI_LOWLEVEL is not set
72CONFIG_NETDEVICES=y 72CONFIG_NETDEVICES=y
73CONFIG_ARM_AT91_ETHER=y
73CONFIG_MACB=y 74CONFIG_MACB=y
74# CONFIG_NET_VENDOR_BROADCOM is not set 75# CONFIG_NET_VENDOR_BROADCOM is not set
75CONFIG_DM9000=y 76CONFIG_DM9000=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index b7e6b6fba5e0..06075b6d2463 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -99,7 +99,7 @@ CONFIG_PCI_RCAR_GEN2=y
99CONFIG_PCI_RCAR_GEN2_PCIE=y 99CONFIG_PCI_RCAR_GEN2_PCIE=y
100CONFIG_PCIEPORTBUS=y 100CONFIG_PCIEPORTBUS=y
101CONFIG_SMP=y 101CONFIG_SMP=y
102CONFIG_NR_CPUS=8 102CONFIG_NR_CPUS=16
103CONFIG_HIGHPTE=y 103CONFIG_HIGHPTE=y
104CONFIG_CMA=y 104CONFIG_CMA=y
105CONFIG_ARM_APPENDED_DTB=y 105CONFIG_ARM_APPENDED_DTB=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index a097cffa1231..8e108599e1af 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -377,6 +377,7 @@ CONFIG_PWM_TWL=m
377CONFIG_PWM_TWL_LED=m 377CONFIG_PWM_TWL_LED=m
378CONFIG_OMAP_USB2=m 378CONFIG_OMAP_USB2=m
379CONFIG_TI_PIPE3=y 379CONFIG_TI_PIPE3=y
380CONFIG_TWL4030_USB=m
380CONFIG_EXT2_FS=y 381CONFIG_EXT2_FS=y
381CONFIG_EXT3_FS=y 382CONFIG_EXT3_FS=y
382# CONFIG_EXT3_FS_XATTR is not set 383# CONFIG_EXT3_FS_XATTR is not set
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index 41d856effe6c..510c747c65b4 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -3,8 +3,6 @@
3CONFIG_SYSVIPC=y 3CONFIG_SYSVIPC=y
4CONFIG_IRQ_DOMAIN_DEBUG=y 4CONFIG_IRQ_DOMAIN_DEBUG=y
5CONFIG_LOG_BUF_SHIFT=14 5CONFIG_LOG_BUF_SHIFT=14
6CONFIG_SYSFS_DEPRECATED=y
7CONFIG_SYSFS_DEPRECATED_V2=y
8CONFIG_BLK_DEV_INITRD=y 6CONFIG_BLK_DEV_INITRD=y
9CONFIG_EMBEDDED=y 7CONFIG_EMBEDDED=y
10CONFIG_SLAB=y 8CONFIG_SLAB=y
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 38840a812924..8f6a5702b696 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -4,6 +4,7 @@ CONFIG_BLK_DEV_INITRD=y
4CONFIG_PERF_EVENTS=y 4CONFIG_PERF_EVENTS=y
5CONFIG_ARCH_SUNXI=y 5CONFIG_ARCH_SUNXI=y
6CONFIG_SMP=y 6CONFIG_SMP=y
7CONFIG_NR_CPUS=8
7CONFIG_AEABI=y 8CONFIG_AEABI=y
8CONFIG_HIGHMEM=y 9CONFIG_HIGHMEM=y
9CONFIG_HIGHPTE=y 10CONFIG_HIGHPTE=y
diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig
index f489fdaa19b8..37fe607a4ede 100644
--- a/arch/arm/configs/vexpress_defconfig
+++ b/arch/arm/configs/vexpress_defconfig
@@ -118,8 +118,8 @@ CONFIG_HID_ZEROPLUS=y
118CONFIG_USB=y 118CONFIG_USB=y
119CONFIG_USB_ANNOUNCE_NEW_DEVICES=y 119CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
120CONFIG_USB_MON=y 120CONFIG_USB_MON=y
121CONFIG_USB_ISP1760_HCD=y
122CONFIG_USB_STORAGE=y 121CONFIG_USB_STORAGE=y
122CONFIG_USB_ISP1760=y
123CONFIG_MMC=y 123CONFIG_MMC=y
124CONFIG_MMC_ARMMMCI=y 124CONFIG_MMC_ARMMMCI=y
125CONFIG_NEW_LEDS=y 125CONFIG_NEW_LEDS=y
diff --git a/arch/arm/include/debug/at91.S b/arch/arm/include/debug/at91.S
index 80a6501b4d50..c3c45e628e33 100644
--- a/arch/arm/include/debug/at91.S
+++ b/arch/arm/include/debug/at91.S
@@ -18,8 +18,11 @@
18#define AT91_DBGU 0xfc00c000 /* SAMA5D4_BASE_USART3 */ 18#define AT91_DBGU 0xfc00c000 /* SAMA5D4_BASE_USART3 */
19#endif 19#endif
20 20
21/* Keep in sync with mach-at91/include/mach/hardware.h */ 21#ifdef CONFIG_MMU
22#define AT91_IO_P2V(x) ((x) - 0x01000000) 22#define AT91_IO_P2V(x) ((x) - 0x01000000)
23#else
24#define AT91_IO_P2V(x) (x)
25#endif
23 26
24#define AT91_DBGU_SR (0x14) /* Status Register */ 27#define AT91_DBGU_SR (0x14) /* Status Register */
25#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */ 28#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 5e34fb143309..aa4116e9452f 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -270,37 +270,35 @@ static void __init at91_pm_sram_init(void)
270 phys_addr_t sram_pbase; 270 phys_addr_t sram_pbase;
271 unsigned long sram_base; 271 unsigned long sram_base;
272 struct device_node *node; 272 struct device_node *node;
273 struct platform_device *pdev; 273 struct platform_device *pdev = NULL;
274 274
275 node = of_find_compatible_node(NULL, NULL, "mmio-sram"); 275 for_each_compatible_node(node, NULL, "mmio-sram") {
276 if (!node) { 276 pdev = of_find_device_by_node(node);
277 pr_warn("%s: failed to find sram node!\n", __func__); 277 if (pdev) {
278 return; 278 of_node_put(node);
279 break;
280 }
279 } 281 }
280 282
281 pdev = of_find_device_by_node(node);
282 if (!pdev) { 283 if (!pdev) {
283 pr_warn("%s: failed to find sram device!\n", __func__); 284 pr_warn("%s: failed to find sram device!\n", __func__);
284 goto put_node; 285 return;
285 } 286 }
286 287
287 sram_pool = dev_get_gen_pool(&pdev->dev); 288 sram_pool = dev_get_gen_pool(&pdev->dev);
288 if (!sram_pool) { 289 if (!sram_pool) {
289 pr_warn("%s: sram pool unavailable!\n", __func__); 290 pr_warn("%s: sram pool unavailable!\n", __func__);
290 goto put_node; 291 return;
291 } 292 }
292 293
293 sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz); 294 sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz);
294 if (!sram_base) { 295 if (!sram_base) {
295 pr_warn("%s: unable to alloc ocram!\n", __func__); 296 pr_warn("%s: unable to alloc ocram!\n", __func__);
296 goto put_node; 297 return;
297 } 298 }
298 299
299 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); 300 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
300 slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false); 301 slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false);
301
302put_node:
303 of_node_put(node);
304} 302}
305#endif 303#endif
306 304
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index d2c89963af2d..86c0aa819d25 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -44,7 +44,7 @@ static inline void at91rm9200_standby(void)
44 " mcr p15, 0, %0, c7, c0, 4\n\t" 44 " mcr p15, 0, %0, c7, c0, 4\n\t"
45 " str %5, [%1, %2]" 45 " str %5, [%1, %2]"
46 : 46 :
47 : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR), 47 : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
48 "r" (1), "r" (AT91RM9200_SDRAMC_SRR), 48 "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
49 "r" (lpr)); 49 "r" (lpr));
50} 50}
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 556151e85ec4..931f0e302c03 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -25,11 +25,6 @@
25 */ 25 */
26#undef SLOWDOWN_MASTER_CLOCK 26#undef SLOWDOWN_MASTER_CLOCK
27 27
28#define MCKRDY_TIMEOUT 1000
29#define MOSCRDY_TIMEOUT 1000
30#define PLLALOCK_TIMEOUT 1000
31#define PLLBLOCK_TIMEOUT 1000
32
33pmc .req r0 28pmc .req r0
34sdramc .req r1 29sdramc .req r1
35ramc1 .req r2 30ramc1 .req r2
@@ -41,60 +36,42 @@ tmp2 .req r5
41 * Wait until master clock is ready (after switching master clock source) 36 * Wait until master clock is ready (after switching master clock source)
42 */ 37 */
43 .macro wait_mckrdy 38 .macro wait_mckrdy
44 mov tmp2, #MCKRDY_TIMEOUT 391: ldr tmp1, [pmc, #AT91_PMC_SR]
451: sub tmp2, tmp2, #1
46 cmp tmp2, #0
47 beq 2f
48 ldr tmp1, [pmc, #AT91_PMC_SR]
49 tst tmp1, #AT91_PMC_MCKRDY 40 tst tmp1, #AT91_PMC_MCKRDY
50 beq 1b 41 beq 1b
512:
52 .endm 42 .endm
53 43
54/* 44/*
55 * Wait until master oscillator has stabilized. 45 * Wait until master oscillator has stabilized.
56 */ 46 */
57 .macro wait_moscrdy 47 .macro wait_moscrdy
58 mov tmp2, #MOSCRDY_TIMEOUT 481: ldr tmp1, [pmc, #AT91_PMC_SR]
591: sub tmp2, tmp2, #1
60 cmp tmp2, #0
61 beq 2f
62 ldr tmp1, [pmc, #AT91_PMC_SR]
63 tst tmp1, #AT91_PMC_MOSCS 49 tst tmp1, #AT91_PMC_MOSCS
64 beq 1b 50 beq 1b
652:
66 .endm 51 .endm
67 52
68/* 53/*
69 * Wait until PLLA has locked. 54 * Wait until PLLA has locked.
70 */ 55 */
71 .macro wait_pllalock 56 .macro wait_pllalock
72 mov tmp2, #PLLALOCK_TIMEOUT 571: ldr tmp1, [pmc, #AT91_PMC_SR]
731: sub tmp2, tmp2, #1
74 cmp tmp2, #0
75 beq 2f
76 ldr tmp1, [pmc, #AT91_PMC_SR]
77 tst tmp1, #AT91_PMC_LOCKA 58 tst tmp1, #AT91_PMC_LOCKA
78 beq 1b 59 beq 1b
792:
80 .endm 60 .endm
81 61
82/* 62/*
83 * Wait until PLLB has locked. 63 * Wait until PLLB has locked.
84 */ 64 */
85 .macro wait_pllblock 65 .macro wait_pllblock
86 mov tmp2, #PLLBLOCK_TIMEOUT 661: ldr tmp1, [pmc, #AT91_PMC_SR]
871: sub tmp2, tmp2, #1
88 cmp tmp2, #0
89 beq 2f
90 ldr tmp1, [pmc, #AT91_PMC_SR]
91 tst tmp1, #AT91_PMC_LOCKB 67 tst tmp1, #AT91_PMC_LOCKB
92 beq 1b 68 beq 1b
932:
94 .endm 69 .endm
95 70
96 .text 71 .text
97 72
73 .arm
74
98/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc, 75/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
99 * void __iomem *ramc1, int memctrl) 76 * void __iomem *ramc1, int memctrl)
100 */ 77 */
@@ -134,6 +111,16 @@ ddr_sr_enable:
134 cmp memctrl, #AT91_MEMCTRL_DDRSDR 111 cmp memctrl, #AT91_MEMCTRL_DDRSDR
135 bne sdr_sr_enable 112 bne sdr_sr_enable
136 113
114 /* LPDDR1 --> force DDR2 mode during self-refresh */
115 ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR]
116 str tmp1, .saved_sam9_mdr
117 bic tmp1, tmp1, #~AT91_DDRSDRC_MD
118 cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
119 ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
120 biceq tmp1, tmp1, #AT91_DDRSDRC_MD
121 orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
122 streq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
123
137 /* prepare for DDRAM self-refresh mode */ 124 /* prepare for DDRAM self-refresh mode */
138 ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR] 125 ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
139 str tmp1, .saved_sam9_lpr 126 str tmp1, .saved_sam9_lpr
@@ -142,14 +129,26 @@ ddr_sr_enable:
142 129
143 /* figure out if we use the second ram controller */ 130 /* figure out if we use the second ram controller */
144 cmp ramc1, #0 131 cmp ramc1, #0
145 ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR] 132 beq ddr_no_2nd_ctrl
146 strne tmp2, .saved_sam9_lpr1 133
147 bicne tmp2, #AT91_DDRSDRC_LPCB 134 ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
148 orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH 135 str tmp2, .saved_sam9_mdr1
136 bic tmp2, tmp2, #~AT91_DDRSDRC_MD
137 cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
138 ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
139 biceq tmp2, tmp2, #AT91_DDRSDRC_MD
140 orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
141 streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
142
143 ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
144 str tmp2, .saved_sam9_lpr1
145 bic tmp2, #AT91_DDRSDRC_LPCB
146 orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
149 147
150 /* Enable DDRAM self-refresh mode */ 148 /* Enable DDRAM self-refresh mode */
149 str tmp2, [ramc1, #AT91_DDRSDRC_LPR]
150ddr_no_2nd_ctrl:
151 str tmp1, [sdramc, #AT91_DDRSDRC_LPR] 151 str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
152 strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
153 152
154 b sdr_sr_done 153 b sdr_sr_done
155 154
@@ -208,6 +207,7 @@ sdr_sr_done:
208 /* Turn off the main oscillator */ 207 /* Turn off the main oscillator */
209 ldr tmp1, [pmc, #AT91_CKGR_MOR] 208 ldr tmp1, [pmc, #AT91_CKGR_MOR]
210 bic tmp1, tmp1, #AT91_PMC_MOSCEN 209 bic tmp1, tmp1, #AT91_PMC_MOSCEN
210 orr tmp1, tmp1, #AT91_PMC_KEY
211 str tmp1, [pmc, #AT91_CKGR_MOR] 211 str tmp1, [pmc, #AT91_CKGR_MOR]
212 212
213 /* Wait for interrupt */ 213 /* Wait for interrupt */
@@ -216,6 +216,7 @@ sdr_sr_done:
216 /* Turn on the main oscillator */ 216 /* Turn on the main oscillator */
217 ldr tmp1, [pmc, #AT91_CKGR_MOR] 217 ldr tmp1, [pmc, #AT91_CKGR_MOR]
218 orr tmp1, tmp1, #AT91_PMC_MOSCEN 218 orr tmp1, tmp1, #AT91_PMC_MOSCEN
219 orr tmp1, tmp1, #AT91_PMC_KEY
219 str tmp1, [pmc, #AT91_CKGR_MOR] 220 str tmp1, [pmc, #AT91_CKGR_MOR]
220 221
221 wait_moscrdy 222 wait_moscrdy
@@ -280,12 +281,17 @@ sdr_sr_done:
280 */ 281 */
281 cmp memctrl, #AT91_MEMCTRL_DDRSDR 282 cmp memctrl, #AT91_MEMCTRL_DDRSDR
282 bne sdr_en_restore 283 bne sdr_en_restore
284 /* Restore MDR in case of LPDDR1 */
285 ldr tmp1, .saved_sam9_mdr
286 str tmp1, [sdramc, #AT91_DDRSDRC_MDR]
283 /* Restore LPR on AT91 with DDRAM */ 287 /* Restore LPR on AT91 with DDRAM */
284 ldr tmp1, .saved_sam9_lpr 288 ldr tmp1, .saved_sam9_lpr
285 str tmp1, [sdramc, #AT91_DDRSDRC_LPR] 289 str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
286 290
287 /* if we use the second ram controller */ 291 /* if we use the second ram controller */
288 cmp ramc1, #0 292 cmp ramc1, #0
293 ldrne tmp2, .saved_sam9_mdr1
294 strne tmp2, [ramc1, #AT91_DDRSDRC_MDR]
289 ldrne tmp2, .saved_sam9_lpr1 295 ldrne tmp2, .saved_sam9_lpr1
290 strne tmp2, [ramc1, #AT91_DDRSDRC_LPR] 296 strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
291 297
@@ -319,5 +325,11 @@ ram_restored:
319.saved_sam9_lpr1: 325.saved_sam9_lpr1:
320 .word 0 326 .word 0
321 327
328.saved_sam9_mdr:
329 .word 0
330
331.saved_sam9_mdr1:
332 .word 0
333
322ENTRY(at91_slow_clock_sz) 334ENTRY(at91_slow_clock_sz)
323 .word .-at91_slow_clock 335 .word .-at91_slow_clock
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 3f32c47a6d74..d2e9f12d12f1 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -126,8 +126,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
126 */ 126 */
127void exynos_cpu_power_down(int cpu) 127void exynos_cpu_power_down(int cpu)
128{ 128{
129 if (cpu == 0 && (of_machine_is_compatible("samsung,exynos5420") || 129 if (cpu == 0 && (soc_is_exynos5420() || soc_is_exynos5800())) {
130 of_machine_is_compatible("samsung,exynos5800"))) {
131 /* 130 /*
132 * Bypass power down for CPU0 during suspend. Check for 131 * Bypass power down for CPU0 during suspend. Check for
133 * the SYS_PWR_REG value to decide if we are suspending 132 * the SYS_PWR_REG value to decide if we are suspending
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 20f267121b3e..37266a826437 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -161,6 +161,34 @@ no_clk:
161 of_genpd_add_provider_simple(np, &pd->pd); 161 of_genpd_add_provider_simple(np, &pd->pd);
162 } 162 }
163 163
164 /* Assign the child power domains to their parents */
165 for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
166 struct generic_pm_domain *child_domain, *parent_domain;
167 struct of_phandle_args args;
168
169 args.np = np;
170 args.args_count = 0;
171 child_domain = of_genpd_get_from_provider(&args);
172 if (!child_domain)
173 continue;
174
175 if (of_parse_phandle_with_args(np, "power-domains",
176 "#power-domain-cells", 0, &args) != 0)
177 continue;
178
179 parent_domain = of_genpd_get_from_provider(&args);
180 if (!parent_domain)
181 continue;
182
183 if (pm_genpd_add_subdomain(parent_domain, child_domain))
184 pr_warn("%s failed to add subdomain: %s\n",
185 parent_domain->name, child_domain->name);
186 else
187 pr_info("%s has as child subdomain: %s.\n",
188 parent_domain->name, child_domain->name);
189 of_node_put(np);
190 }
191
164 return 0; 192 return 0;
165} 193}
166arch_initcall(exynos4_pm_init_power_domain); 194arch_initcall(exynos4_pm_init_power_domain);
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 52e2b1a2fddb..318d127df147 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -87,8 +87,8 @@ static unsigned int exynos_pmu_spare3;
87static u32 exynos_irqwake_intmask = 0xffffffff; 87static u32 exynos_irqwake_intmask = 0xffffffff;
88 88
89static const struct exynos_wkup_irq exynos3250_wkup_irq[] = { 89static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
90 { 73, BIT(1) }, /* RTC alarm */ 90 { 105, BIT(1) }, /* RTC alarm */
91 { 74, BIT(2) }, /* RTC tick */ 91 { 106, BIT(2) }, /* RTC tick */
92 { /* sentinel */ }, 92 { /* sentinel */ },
93}; 93};
94 94
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 92afb723dcfc..355b08936871 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1692,16 +1692,15 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
1692 if (ret == -EBUSY) 1692 if (ret == -EBUSY)
1693 pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name); 1693 pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name);
1694 1694
1695 if (!ret) { 1695 if (oh->clkdm) {
1696 /* 1696 /*
1697 * Set the clockdomain to HW_AUTO, assuming that the 1697 * Set the clockdomain to HW_AUTO, assuming that the
1698 * previous state was HW_AUTO. 1698 * previous state was HW_AUTO.
1699 */ 1699 */
1700 if (oh->clkdm && hwsup) 1700 if (hwsup)
1701 clkdm_allow_idle(oh->clkdm); 1701 clkdm_allow_idle(oh->clkdm);
1702 } else { 1702
1703 if (oh->clkdm) 1703 clkdm_hwmod_disable(oh->clkdm, oh);
1704 clkdm_hwmod_disable(oh->clkdm, oh);
1705 } 1704 }
1706 1705
1707 return ret; 1706 return ret;
@@ -2698,6 +2697,7 @@ static int __init _register(struct omap_hwmod *oh)
2698 INIT_LIST_HEAD(&oh->master_ports); 2697 INIT_LIST_HEAD(&oh->master_ports);
2699 INIT_LIST_HEAD(&oh->slave_ports); 2698 INIT_LIST_HEAD(&oh->slave_ports);
2700 spin_lock_init(&oh->_lock); 2699 spin_lock_init(&oh->_lock);
2700 lockdep_set_class(&oh->_lock, &oh->hwmod_key);
2701 2701
2702 oh->_state = _HWMOD_STATE_REGISTERED; 2702 oh->_state = _HWMOD_STATE_REGISTERED;
2703 2703
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 9d4bec6ee742..9611c91d9b82 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -674,6 +674,7 @@ struct omap_hwmod {
674 u32 _sysc_cache; 674 u32 _sysc_cache;
675 void __iomem *_mpu_rt_va; 675 void __iomem *_mpu_rt_va;
676 spinlock_t _lock; 676 spinlock_t _lock;
677 struct lock_class_key hwmod_key; /* unique lock class */
677 struct list_head node; 678 struct list_head node;
678 struct omap_hwmod_ocp_if *_mpu_port; 679 struct omap_hwmod_ocp_if *_mpu_port;
679 unsigned int (*xlate_irq)(unsigned int); 680 unsigned int (*xlate_irq)(unsigned int);
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index e8692e7675b8..16fe7a1b7a35 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1466,55 +1466,18 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1466 * 1466 *
1467 */ 1467 */
1468 1468
1469static struct omap_hwmod_class dra7xx_pcie_hwmod_class = { 1469static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1470 .name = "pcie", 1470 .name = "pcie",
1471}; 1471};
1472 1472
1473/* pcie1 */ 1473/* pcie1 */
1474static struct omap_hwmod dra7xx_pcie1_hwmod = { 1474static struct omap_hwmod dra7xx_pciess1_hwmod = {
1475 .name = "pcie1", 1475 .name = "pcie1",
1476 .class = &dra7xx_pcie_hwmod_class, 1476 .class = &dra7xx_pciess_hwmod_class,
1477 .clkdm_name = "pcie_clkdm", 1477 .clkdm_name = "pcie_clkdm",
1478 .main_clk = "l4_root_clk_div", 1478 .main_clk = "l4_root_clk_div",
1479 .prcm = { 1479 .prcm = {
1480 .omap4 = { 1480 .omap4 = {
1481 .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1482 .modulemode = MODULEMODE_SWCTRL,
1483 },
1484 },
1485};
1486
1487/* pcie2 */
1488static struct omap_hwmod dra7xx_pcie2_hwmod = {
1489 .name = "pcie2",
1490 .class = &dra7xx_pcie_hwmod_class,
1491 .clkdm_name = "pcie_clkdm",
1492 .main_clk = "l4_root_clk_div",
1493 .prcm = {
1494 .omap4 = {
1495 .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1496 .modulemode = MODULEMODE_SWCTRL,
1497 },
1498 },
1499};
1500
1501/*
1502 * 'PCIE PHY' class
1503 *
1504 */
1505
1506static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
1507 .name = "pcie-phy",
1508};
1509
1510/* pcie1 phy */
1511static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
1512 .name = "pcie1-phy",
1513 .class = &dra7xx_pcie_phy_hwmod_class,
1514 .clkdm_name = "l3init_clkdm",
1515 .main_clk = "l4_root_clk_div",
1516 .prcm = {
1517 .omap4 = {
1518 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET, 1481 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1519 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET, 1482 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1520 .modulemode = MODULEMODE_SWCTRL, 1483 .modulemode = MODULEMODE_SWCTRL,
@@ -1522,11 +1485,11 @@ static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
1522 }, 1485 },
1523}; 1486};
1524 1487
1525/* pcie2 phy */ 1488/* pcie2 */
1526static struct omap_hwmod dra7xx_pcie2_phy_hwmod = { 1489static struct omap_hwmod dra7xx_pciess2_hwmod = {
1527 .name = "pcie2-phy", 1490 .name = "pcie2",
1528 .class = &dra7xx_pcie_phy_hwmod_class, 1491 .class = &dra7xx_pciess_hwmod_class,
1529 .clkdm_name = "l3init_clkdm", 1492 .clkdm_name = "pcie_clkdm",
1530 .main_clk = "l4_root_clk_div", 1493 .main_clk = "l4_root_clk_div",
1531 .prcm = { 1494 .prcm = {
1532 .omap4 = { 1495 .omap4 = {
@@ -2877,50 +2840,34 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2877 .user = OCP_USER_MPU | OCP_USER_SDMA, 2840 .user = OCP_USER_MPU | OCP_USER_SDMA,
2878}; 2841};
2879 2842
2880/* l3_main_1 -> pcie1 */ 2843/* l3_main_1 -> pciess1 */
2881static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = { 2844static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
2882 .master = &dra7xx_l3_main_1_hwmod, 2845 .master = &dra7xx_l3_main_1_hwmod,
2883 .slave = &dra7xx_pcie1_hwmod, 2846 .slave = &dra7xx_pciess1_hwmod,
2884 .clk = "l3_iclk_div", 2847 .clk = "l3_iclk_div",
2885 .user = OCP_USER_MPU | OCP_USER_SDMA, 2848 .user = OCP_USER_MPU | OCP_USER_SDMA,
2886}; 2849};
2887 2850
2888/* l4_cfg -> pcie1 */ 2851/* l4_cfg -> pciess1 */
2889static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = { 2852static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
2890 .master = &dra7xx_l4_cfg_hwmod, 2853 .master = &dra7xx_l4_cfg_hwmod,
2891 .slave = &dra7xx_pcie1_hwmod, 2854 .slave = &dra7xx_pciess1_hwmod,
2892 .clk = "l4_root_clk_div", 2855 .clk = "l4_root_clk_div",
2893 .user = OCP_USER_MPU | OCP_USER_SDMA, 2856 .user = OCP_USER_MPU | OCP_USER_SDMA,
2894}; 2857};
2895 2858
2896/* l3_main_1 -> pcie2 */ 2859/* l3_main_1 -> pciess2 */
2897static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = { 2860static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
2898 .master = &dra7xx_l3_main_1_hwmod, 2861 .master = &dra7xx_l3_main_1_hwmod,
2899 .slave = &dra7xx_pcie2_hwmod, 2862 .slave = &dra7xx_pciess2_hwmod,
2900 .clk = "l3_iclk_div", 2863 .clk = "l3_iclk_div",
2901 .user = OCP_USER_MPU | OCP_USER_SDMA, 2864 .user = OCP_USER_MPU | OCP_USER_SDMA,
2902}; 2865};
2903 2866
2904/* l4_cfg -> pcie2 */ 2867/* l4_cfg -> pciess2 */
2905static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = { 2868static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
2906 .master = &dra7xx_l4_cfg_hwmod,
2907 .slave = &dra7xx_pcie2_hwmod,
2908 .clk = "l4_root_clk_div",
2909 .user = OCP_USER_MPU | OCP_USER_SDMA,
2910};
2911
2912/* l4_cfg -> pcie1 phy */
2913static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
2914 .master = &dra7xx_l4_cfg_hwmod,
2915 .slave = &dra7xx_pcie1_phy_hwmod,
2916 .clk = "l4_root_clk_div",
2917 .user = OCP_USER_MPU | OCP_USER_SDMA,
2918};
2919
2920/* l4_cfg -> pcie2 phy */
2921static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
2922 .master = &dra7xx_l4_cfg_hwmod, 2869 .master = &dra7xx_l4_cfg_hwmod,
2923 .slave = &dra7xx_pcie2_phy_hwmod, 2870 .slave = &dra7xx_pciess2_hwmod,
2924 .clk = "l4_root_clk_div", 2871 .clk = "l4_root_clk_div",
2925 .user = OCP_USER_MPU | OCP_USER_SDMA, 2872 .user = OCP_USER_MPU | OCP_USER_SDMA,
2926}; 2873};
@@ -3327,12 +3274,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3327 &dra7xx_l4_cfg__mpu, 3274 &dra7xx_l4_cfg__mpu,
3328 &dra7xx_l4_cfg__ocp2scp1, 3275 &dra7xx_l4_cfg__ocp2scp1,
3329 &dra7xx_l4_cfg__ocp2scp3, 3276 &dra7xx_l4_cfg__ocp2scp3,
3330 &dra7xx_l3_main_1__pcie1, 3277 &dra7xx_l3_main_1__pciess1,
3331 &dra7xx_l4_cfg__pcie1, 3278 &dra7xx_l4_cfg__pciess1,
3332 &dra7xx_l3_main_1__pcie2, 3279 &dra7xx_l3_main_1__pciess2,
3333 &dra7xx_l4_cfg__pcie2, 3280 &dra7xx_l4_cfg__pciess2,
3334 &dra7xx_l4_cfg__pcie1_phy,
3335 &dra7xx_l4_cfg__pcie2_phy,
3336 &dra7xx_l3_main_1__qspi, 3281 &dra7xx_l3_main_1__qspi,
3337 &dra7xx_l4_per3__rtcss, 3282 &dra7xx_l4_per3__rtcss,
3338 &dra7xx_l4_cfg__sata, 3283 &dra7xx_l4_cfg__sata,
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 190fa43e7479..e642b079e9f3 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -173,6 +173,7 @@ static void __init omap3_igep0030_rev_g_legacy_init(void)
173 173
174static void __init omap3_evm_legacy_init(void) 174static void __init omap3_evm_legacy_init(void)
175{ 175{
176 hsmmc2_internal_input_clk();
176 legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 149); 177 legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 149);
177} 178}
178 179
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a08a617a6c11..d6d6bc39e05c 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -252,10 +252,10 @@ static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
252{ 252{
253 saved_mask[0] = 253 saved_mask[0] =
254 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, 254 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
255 OMAP4_PRM_IRQSTATUS_MPU_OFFSET); 255 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
256 saved_mask[1] = 256 saved_mask[1] =
257 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, 257 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
258 OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET); 258 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
259 259
260 omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, 260 omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
261 OMAP4_PRM_IRQENABLE_MPU_OFFSET); 261 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 483cb467bf65..a0f3b1cd497c 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -45,6 +45,6 @@ extern char secondary_trampoline, secondary_trampoline_end;
45 45
46extern unsigned long socfpga_cpu1start_addr; 46extern unsigned long socfpga_cpu1start_addr;
47 47
48#define SOCFPGA_SCU_VIRT_BASE 0xfffec000 48#define SOCFPGA_SCU_VIRT_BASE 0xfee00000
49 49
50#endif 50#endif
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 383d61e138af..f5e597c207b9 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -23,6 +23,7 @@
23#include <asm/hardware/cache-l2x0.h> 23#include <asm/hardware/cache-l2x0.h>
24#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
25#include <asm/mach/map.h> 25#include <asm/mach/map.h>
26#include <asm/cacheflush.h>
26 27
27#include "core.h" 28#include "core.h"
28 29
@@ -73,6 +74,10 @@ void __init socfpga_sysmgr_init(void)
73 (u32 *) &socfpga_cpu1start_addr)) 74 (u32 *) &socfpga_cpu1start_addr))
74 pr_err("SMP: Need cpu1-start-addr in device tree.\n"); 75 pr_err("SMP: Need cpu1-start-addr in device tree.\n");
75 76
77 /* Ensure that socfpga_cpu1start_addr is visible to other CPUs */
78 smp_wmb();
79 sync_cache_w(&socfpga_cpu1start_addr);
80
76 sys_manager_base_addr = of_iomap(np, 0); 81 sys_manager_base_addr = of_iomap(np, 0);
77 82
78 np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr"); 83 np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
index b067390cef4e..b373acade338 100644
--- a/arch/arm/mach-sti/board-dt.c
+++ b/arch/arm/mach-sti/board-dt.c
@@ -18,6 +18,7 @@ static const char *stih41x_dt_match[] __initdata = {
18 "st,stih415", 18 "st,stih415",
19 "st,stih416", 19 "st,stih416",
20 "st,stih407", 20 "st,stih407",
21 "st,stih410",
21 "st,stih418", 22 "st,stih418",
22 NULL 23 NULL
23}; 24};
diff --git a/include/dt-bindings/pinctrl/am33xx.h b/include/dt-bindings/pinctrl/am33xx.h
index 2fbc804e1a45..226f77246a70 100644
--- a/include/dt-bindings/pinctrl/am33xx.h
+++ b/include/dt-bindings/pinctrl/am33xx.h
@@ -13,7 +13,8 @@
13 13
14#define PULL_DISABLE (1 << 3) 14#define PULL_DISABLE (1 << 3)
15#define INPUT_EN (1 << 5) 15#define INPUT_EN (1 << 5)
16#define SLEWCTRL_FAST (1 << 6) 16#define SLEWCTRL_SLOW (1 << 6)
17#define SLEWCTRL_FAST 0
17 18
18/* update macro depending on INPUT_EN and PULL_ENA */ 19/* update macro depending on INPUT_EN and PULL_ENA */
19#undef PIN_OUTPUT 20#undef PIN_OUTPUT
diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h
index 9c2e4f82381e..5f4d01898c9c 100644
--- a/include/dt-bindings/pinctrl/am43xx.h
+++ b/include/dt-bindings/pinctrl/am43xx.h
@@ -18,7 +18,8 @@
18#define PULL_DISABLE (1 << 16) 18#define PULL_DISABLE (1 << 16)
19#define PULL_UP (1 << 17) 19#define PULL_UP (1 << 17)
20#define INPUT_EN (1 << 18) 20#define INPUT_EN (1 << 18)
21#define SLEWCTRL_FAST (1 << 19) 21#define SLEWCTRL_SLOW (1 << 19)
22#define SLEWCTRL_FAST 0
22#define DS0_PULL_UP_DOWN_EN (1 << 27) 23#define DS0_PULL_UP_DOWN_EN (1 << 27)
23 24
24#define PIN_OUTPUT (PULL_DISABLE) 25#define PIN_OUTPUT (PULL_DISABLE)
diff --git a/include/soc/at91/at91sam9_ddrsdr.h b/include/soc/at91/at91sam9_ddrsdr.h
index 0210797abf2e..dc10c52e0e91 100644
--- a/include/soc/at91/at91sam9_ddrsdr.h
+++ b/include/soc/at91/at91sam9_ddrsdr.h
@@ -92,7 +92,7 @@
92#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ 92#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
93 93
94#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ 94#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
95#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ 95#define AT91_DDRSDRC_MD (7 << 0) /* Memory Device Type */
96#define AT91_DDRSDRC_MD_SDR 0 96#define AT91_DDRSDRC_MD_SDR 0
97#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 97#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
98#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 98#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-30 13:35:30 -0500