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-rw-r--r--MAINTAINERS7
-rw-r--r--drivers/pci/host/Kconfig6
-rw-r--r--drivers/pci/host/Makefile1
-rw-r--r--drivers/pci/host/pci-v3-semi.c959
4 files changed, 973 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 65b0c88d5ee0..5cb4bf4a06cd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10503,6 +10503,13 @@ S: Maintained
10503F: Documentation/devicetree/bindings/pci/rockchip-pcie.txt 10503F: Documentation/devicetree/bindings/pci/rockchip-pcie.txt
10504F: drivers/pci/host/pcie-rockchip.c 10504F: drivers/pci/host/pcie-rockchip.c
10505 10505
10506PCI DRIVER FOR V3 SEMICONDUCTOR V360EPC
10507M: Linus Walleij <linus.walleij@linaro.org>
10508L: linux-pci@vger.kernel.org
10509S: Maintained
10510F: Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt
10511F: drivers/pci/host/pci-v3-semi.c
10512
10506PCIE DRIVER FOR ST SPEAR13XX 10513PCIE DRIVER FOR ST SPEAR13XX
10507M: Pratyush Anand <pratyush.anand@gmail.com> 10514M: Pratyush Anand <pratyush.anand@gmail.com>
10508L: linux-pci@vger.kernel.org 10515L: linux-pci@vger.kernel.org
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index b868803792d8..38d12980db0f 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -95,6 +95,12 @@ config PCI_XGENE_MSI
95 Say Y here if you want PCIe MSI support for the APM X-Gene v1 SoC. 95 Say Y here if you want PCIe MSI support for the APM X-Gene v1 SoC.
96 This MSI driver supports 5 PCIe ports on the APM X-Gene v1 SoC. 96 This MSI driver supports 5 PCIe ports on the APM X-Gene v1 SoC.
97 97
98config PCI_V3_SEMI
99 bool "V3 Semiconductor PCI controller"
100 depends on OF
101 depends on ARM
102 default ARCH_INTEGRATOR_AP
103
98config PCI_VERSATILE 104config PCI_VERSATILE
99 bool "ARM Versatile PB PCI controller" 105 bool "ARM Versatile PB PCI controller"
100 depends on ARCH_VERSATILE 106 depends on ARCH_VERSATILE
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 12382785e02a..ee7cd492bb7f 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_PCI_HOST_COMMON) += pci-host-common.o
9obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o 9obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
10obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o 10obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
11obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o 11obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
12obj-$(CONFIG_PCI_V3_SEMI) += pci-v3-semi.o
12obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o 13obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o
13obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o 14obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
14obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o 15obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
diff --git a/drivers/pci/host/pci-v3-semi.c b/drivers/pci/host/pci-v3-semi.c
new file mode 100644
index 000000000000..02f6e1e3a421
--- /dev/null
+++ b/drivers/pci/host/pci-v3-semi.c
@@ -0,0 +1,959 @@
1/*
2 * Support for V3 Semiconductor PCI Local Bus to PCI Bridge
3 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
4 *
5 * Based on the code from arch/arm/mach-integrator/pci_v3.c
6 * Copyright (C) 1999 ARM Limited
7 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
8 *
9 * Contributors to the old driver include:
10 * Russell King <linux@armlinux.org.uk>
11 * David A. Rusling <david.rusling@linaro.org> (uHAL, ARM Firmware suite)
12 * Rob Herring <robh@kernel.org>
13 * Liviu Dudau <Liviu.Dudau@arm.com>
14 * Grant Likely <grant.likely@secretlab.ca>
15 * Arnd Bergmann <arnd@arndb.de>
16 * Bjorn Helgaas <bhelgaas@google.com>
17 */
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/kernel.h>
22#include <linux/of_address.h>
23#include <linux/of_device.h>
24#include <linux/of_irq.h>
25#include <linux/of_pci.h>
26#include <linux/pci.h>
27#include <linux/platform_device.h>
28#include <linux/slab.h>
29#include <linux/bitops.h>
30#include <linux/irq.h>
31#include <linux/mfd/syscon.h>
32#include <linux/regmap.h>
33#include <linux/clk.h>
34
35#define V3_PCI_VENDOR 0x00000000
36#define V3_PCI_DEVICE 0x00000002
37#define V3_PCI_CMD 0x00000004
38#define V3_PCI_STAT 0x00000006
39#define V3_PCI_CC_REV 0x00000008
40#define V3_PCI_HDR_CFG 0x0000000C
41#define V3_PCI_IO_BASE 0x00000010
42#define V3_PCI_BASE0 0x00000014
43#define V3_PCI_BASE1 0x00000018
44#define V3_PCI_SUB_VENDOR 0x0000002C
45#define V3_PCI_SUB_ID 0x0000002E
46#define V3_PCI_ROM 0x00000030
47#define V3_PCI_BPARAM 0x0000003C
48#define V3_PCI_MAP0 0x00000040
49#define V3_PCI_MAP1 0x00000044
50#define V3_PCI_INT_STAT 0x00000048
51#define V3_PCI_INT_CFG 0x0000004C
52#define V3_LB_BASE0 0x00000054
53#define V3_LB_BASE1 0x00000058
54#define V3_LB_MAP0 0x0000005E
55#define V3_LB_MAP1 0x00000062
56#define V3_LB_BASE2 0x00000064
57#define V3_LB_MAP2 0x00000066
58#define V3_LB_SIZE 0x00000068
59#define V3_LB_IO_BASE 0x0000006E
60#define V3_FIFO_CFG 0x00000070
61#define V3_FIFO_PRIORITY 0x00000072
62#define V3_FIFO_STAT 0x00000074
63#define V3_LB_ISTAT 0x00000076
64#define V3_LB_IMASK 0x00000077
65#define V3_SYSTEM 0x00000078
66#define V3_LB_CFG 0x0000007A
67#define V3_PCI_CFG 0x0000007C
68#define V3_DMA_PCI_ADR0 0x00000080
69#define V3_DMA_PCI_ADR1 0x00000090
70#define V3_DMA_LOCAL_ADR0 0x00000084
71#define V3_DMA_LOCAL_ADR1 0x00000094
72#define V3_DMA_LENGTH0 0x00000088
73#define V3_DMA_LENGTH1 0x00000098
74#define V3_DMA_CSR0 0x0000008B
75#define V3_DMA_CSR1 0x0000009B
76#define V3_DMA_CTLB_ADR0 0x0000008C
77#define V3_DMA_CTLB_ADR1 0x0000009C
78#define V3_DMA_DELAY 0x000000E0
79#define V3_MAIL_DATA 0x000000C0
80#define V3_PCI_MAIL_IEWR 0x000000D0
81#define V3_PCI_MAIL_IERD 0x000000D2
82#define V3_LB_MAIL_IEWR 0x000000D4
83#define V3_LB_MAIL_IERD 0x000000D6
84#define V3_MAIL_WR_STAT 0x000000D8
85#define V3_MAIL_RD_STAT 0x000000DA
86#define V3_QBA_MAP 0x000000DC
87
88/* PCI STATUS bits */
89#define V3_PCI_STAT_PAR_ERR BIT(15)
90#define V3_PCI_STAT_SYS_ERR BIT(14)
91#define V3_PCI_STAT_M_ABORT_ERR BIT(13)
92#define V3_PCI_STAT_T_ABORT_ERR BIT(12)
93
94/* LB ISTAT bits */
95#define V3_LB_ISTAT_MAILBOX BIT(7)
96#define V3_LB_ISTAT_PCI_RD BIT(6)
97#define V3_LB_ISTAT_PCI_WR BIT(5)
98#define V3_LB_ISTAT_PCI_INT BIT(4)
99#define V3_LB_ISTAT_PCI_PERR BIT(3)
100#define V3_LB_ISTAT_I2O_QWR BIT(2)
101#define V3_LB_ISTAT_DMA1 BIT(1)
102#define V3_LB_ISTAT_DMA0 BIT(0)
103
104/* PCI COMMAND bits */
105#define V3_COMMAND_M_FBB_EN BIT(9)
106#define V3_COMMAND_M_SERR_EN BIT(8)
107#define V3_COMMAND_M_PAR_EN BIT(6)
108#define V3_COMMAND_M_MASTER_EN BIT(2)
109#define V3_COMMAND_M_MEM_EN BIT(1)
110#define V3_COMMAND_M_IO_EN BIT(0)
111
112/* SYSTEM bits */
113#define V3_SYSTEM_M_RST_OUT BIT(15)
114#define V3_SYSTEM_M_LOCK BIT(14)
115#define V3_SYSTEM_UNLOCK 0xa05f
116
117/* PCI CFG bits */
118#define V3_PCI_CFG_M_I2O_EN BIT(15)
119#define V3_PCI_CFG_M_IO_REG_DIS BIT(14)
120#define V3_PCI_CFG_M_IO_DIS BIT(13)
121#define V3_PCI_CFG_M_EN3V BIT(12)
122#define V3_PCI_CFG_M_RETRY_EN BIT(10)
123#define V3_PCI_CFG_M_AD_LOW1 BIT(9)
124#define V3_PCI_CFG_M_AD_LOW0 BIT(8)
125/*
126 * This is the value applied to C/BE[3:1], with bit 0 always held 0
127 * during DMA access.
128 */
129#define V3_PCI_CFG_M_RTYPE_SHIFT 5
130#define V3_PCI_CFG_M_WTYPE_SHIFT 1
131#define V3_PCI_CFG_TYPE_DEFAULT 0x3
132
133/* PCI BASE bits (PCI -> Local Bus) */
134#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000U
135#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00U
136#define V3_PCI_BASE_M_PREFETCH BIT(3)
137#define V3_PCI_BASE_M_TYPE (3 << 1)
138#define V3_PCI_BASE_M_IO BIT(0)
139
140/* PCI MAP bits (PCI -> Local bus) */
141#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000U
142#define V3_PCI_MAP_M_RD_POST_INH BIT(15)
143#define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
144#define V3_PCI_MAP_M_SWAP (3 << 8)
145#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0U
146#define V3_PCI_MAP_M_REG_EN BIT(1)
147#define V3_PCI_MAP_M_ENABLE BIT(0)
148
149/* LB_BASE0,1 bits (Local bus -> PCI) */
150#define V3_LB_BASE_ADR_BASE 0xfff00000U
151#define V3_LB_BASE_SWAP (3 << 8)
152#define V3_LB_BASE_ADR_SIZE (15 << 4)
153#define V3_LB_BASE_PREFETCH BIT(3)
154#define V3_LB_BASE_ENABLE BIT(0)
155
156#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
157#define V3_LB_BASE_ADR