1 files changed, 170 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
new file mode 100644
index 000000000000..b878a1e305af
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
@@ -0,0 +1,170 @@
+Marvell Xenon SDHCI Controller device tree bindings
+This file documents differences between the core mmc properties
+described by mmc.txt and the properties used by the Xenon implementation.
+Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
+Each SDHC is independent and owns independent resources, such as register sets,
+clock and PHY.
+Each SDHC should have an independent device tree node.
+Required Properties:
+- compatible: should be one of the following
+  - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
+  Must provide a second register area and marvell,pad-type.
+  - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
+  - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
+- clocks:
+  Array of clocks required for SDHC.
+  Require at least input clock for Xenon IP core.
+- clock-names:
+  Array of names corresponding to clocks property.
+  The input clock for Xenon IP core should be named as "core".
+- reg:
+  * For "marvell,armada-3700-sdhci", two register areas.
+    The first one for Xenon IP register. The second one for the Armada 3700 SoC
+    PHY PAD Voltage Control register.
+    Please follow the examples with compatible "marvell,armada-3700-sdhci"
+    in below.
+    Please also check property marvell,pad-type in below.
+  * For other compatible strings, one register area for Xenon IP.
+Optional Properties:
+- marvell,xenon-sdhc-id:
+  Indicate the corresponding bit index of current SDHC in
+  SDHC System Operation Control Register Bit[7:0].
+  Set/clear the corresponding bit to enable/disable current SDHC.
+  If Xenon IP contains only one SDHC, this property is optional.
+- marvell,xenon-phy-type:
+  Xenon support multiple types of PHYs.
+  To select eMMC 5.1 PHY, set:
+  marvell,xenon-phy-type = "emmc 5.1 phy"
+  eMMC 5.1 PHY is the default choice if this property is not provided.
+  To select eMMC 5.0 PHY, set:
+  marvell,xenon-phy-type = "emmc 5.0 phy"
+  All those types of PHYs can support eMMC, SD and SDIO.
+  Please note that this property only presents the type of PHY.
+  It doesn't stand for the entire SDHC type or property.
+  For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only
+  supports eMMC 5.1.
+- marvell,xenon-phy-znr:
+  Set PHY ZNR value.
+  Only available for eMMC PHY.
+  Valid range = [0:0x1F].
+  ZNR is set as 0xF by default if this property is not provided.
+- marvell,xenon-phy-zpr:
+  Set PHY ZPR value.
+  Only available for eMMC PHY.
+  Valid range = [0:0x1F].
+  ZPR is set as 0xF by default if this property is not provided.
+- marvell,xenon-phy-nr-success-tun:
+  Set the number of required consecutive successful sampling points
+  used to identify a valid sampling window, in tuning process.
+  Valid range = [1:7].
+  Set as 0x4 by default if this property is not provided.
+- marvell,xenon-phy-tun-step-divider:
+  Set the divider for calculating TUN_STEP.
+  Set as 64 by default if this property is not provided.
+- marvell,xenon-phy-slow-mode:
+  If this property is selected, transfers will bypass PHY.
+  Only available when bus frequency lower than 55MHz in SDR mode.
+  Disabled by default. Please only try this property if timing issues
+  always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
+  SD Default Speed and HS mode and eMMC legacy speed mode.
+- marvell,xenon-tun-count:
+  Xenon SDHC SoC usually doesn't provide re-tuning counter in
+  Capabilities Register 3 Bit[11:8].
+  This property provides the re-tuning counter.
+  If this property is not set, default re-tuning counter will
+  be set as 0x9 in driver.
+- marvell,pad-type:
+  Type of Armada 3700 SoC PHY PAD Voltage Controller register.
+  Only valid when "marvell,armada-3700-sdhci" is selected.
+  Two types: "sd" and "fixed-1-8v".
+  If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning and is
+  switched to 1.8V when later in higher speed mode.
+  If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for eMMC.
+  Please follow the examples with compatible "marvell,armada-3700-sdhci"
+  in below.
+Example:
+- For eMMC:
+        sdhci@aa0000 {
+                compatible = "marvell,armada-ap806-sdhci";
+                reg = <0xaa0000 0x1000>;
+                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
+                clocks = <&emmc_clk>;
+                clock-names = "core";
+                bus-width = <4>;
+                marvell,xenon-phy-slow-mode;
+                marvell,xenon-tun-count = <11>;
+                non-removable;
+                no-sd;
+                no-sdio;
+                /* Vmmc and Vqmmc are both fixed */
+        };
+- For SD/SDIO:
+        sdhci@ab0000 {
+                compatible = "marvell,armada-cp110-sdhci";
+                reg = <0xab0000 0x1000>;
+                interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
+                vqmmc-supply = <&sd_vqmmc_regulator>;
+                vmmc-supply = <&sd_vmmc_regulator>;
+                clocks = <&sdclk>;
+                clock-names = "core";
+                bus-width = <4>;
+                marvell,xenon-tun-count = <9>;
+        };
+- For eMMC with compatible "marvell,armada-3700-sdhci":
+        sdhci@aa0000 {
+                compatible = "marvell,armada-3700-sdhci";
+                reg = <0xaa0000 0x1000>,
+                      <phy_addr 0x4>;
+                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
+                clocks = <&emmcclk>;
+                clock-names = "core";
+                bus-width = <8>;
+                mmc-ddr-1_8v;
+                mmc-hs400-1_8v;
+                non-removable;
+                no-sd;
+                no-sdio;
+                /* Vmmc and Vqmmc are both fixed */
+                marvell,pad-type = "fixed-1-8v";
+        };
+- For SD/SDIO with compatible "marvell,armada-3700-sdhci":
+        sdhci@ab0000 {
+                compatible = "marvell,armada-3700-sdhci";
+                reg = <0xab0000 0x1000>,
+                      <phy_addr 0x4>;
+                interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
+                vqmmc-supply = <&sd_regulator>;
+                /* Vmmc is fixed */
+                clocks = <&sdclk>;
+                clock-names = "core";
+                bus-width = <4>;
+                marvell,pad-type = "sd";
+        };

diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt new file mode 100644 index 000000000000..b878a1e305af --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
@@ -0,0 +1,170 @@
	1	Marvell Xenon SDHCI Controller device tree bindings
	2	This file documents differences between the core mmc properties
	3	described by mmc.txt and the properties used by the Xenon implementation.
	4
	5	Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
	6	Each SDHC is independent and owns independent resources, such as register sets,
	7	clock and PHY.
	8	Each SDHC should have an independent device tree node.
	9
	10	Required Properties:
	11	- compatible: should be one of the following
	12	- "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
	13	Must provide a second register area and marvell,pad-type.
	14	- "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
	15	- "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
	16
	17	- clocks:
	18	Array of clocks required for SDHC.
	19	Require at least input clock for Xenon IP core.
	20
	21	- clock-names:
	22	Array of names corresponding to clocks property.
	23	The input clock for Xenon IP core should be named as "core".
	24
	25	- reg:
	26	* For "marvell,armada-3700-sdhci", two register areas.
	27	The first one for Xenon IP register. The second one for the Armada 3700 SoC
	28	PHY PAD Voltage Control register.
	29	Please follow the examples with compatible "marvell,armada-3700-sdhci"
	30	in below.
	31	Please also check property marvell,pad-type in below.
	32
	33	* For other compatible strings, one register area for Xenon IP.
	34
	35	Optional Properties:
	36	- marvell,xenon-sdhc-id:
	37	Indicate the corresponding bit index of current SDHC in
	38	SDHC System Operation Control Register Bit[7:0].
	39	Set/clear the corresponding bit to enable/disable current SDHC.
	40	If Xenon IP contains only one SDHC, this property is optional.
	41
	42	- marvell,xenon-phy-type:
	43	Xenon support multiple types of PHYs.
	44	To select eMMC 5.1 PHY, set:
	45	marvell,xenon-phy-type = "emmc 5.1 phy"
	46	eMMC 5.1 PHY is the default choice if this property is not provided.
	47	To select eMMC 5.0 PHY, set:
	48	marvell,xenon-phy-type = "emmc 5.0 phy"
	49
	50	All those types of PHYs can support eMMC, SD and SDIO.
	51	Please note that this property only presents the type of PHY.
	52	It doesn't stand for the entire SDHC type or property.
	53	For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only
	54	supports eMMC 5.1.
	55
	56	- marvell,xenon-phy-znr:
	57	Set PHY ZNR value.
	58	Only available for eMMC PHY.
	59	Valid range = [0:0x1F].
	60	ZNR is set as 0xF by default if this property is not provided.
	61
	62	- marvell,xenon-phy-zpr:
	63	Set PHY ZPR value.
	64	Only available for eMMC PHY.
	65	Valid range = [0:0x1F].
	66	ZPR is set as 0xF by default if this property is not provided.
	67
	68	- marvell,xenon-phy-nr-success-tun:
	69	Set the number of required consecutive successful sampling points
	70	used to identify a valid sampling window, in tuning process.
	71	Valid range = [1:7].
	72	Set as 0x4 by default if this property is not provided.
	73
	74	- marvell,xenon-phy-tun-step-divider:
	75	Set the divider for calculating TUN_STEP.
	76	Set as 64 by default if this property is not provided.
	77
	78	- marvell,xenon-phy-slow-mode:
	79	If this property is selected, transfers will bypass PHY.
	80	Only available when bus frequency lower than 55MHz in SDR mode.
	81	Disabled by default. Please only try this property if timing issues
	82	always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
	83	SD Default Speed and HS mode and eMMC legacy speed mode.
	84
	85	- marvell,xenon-tun-count:
	86	Xenon SDHC SoC usually doesn't provide re-tuning counter in
	87	Capabilities Register 3 Bit[11:8].
	88	This property provides the re-tuning counter.
	89	If this property is not set, default re-tuning counter will
	90	be set as 0x9 in driver.
	91
	92	- marvell,pad-type:
	93	Type of Armada 3700 SoC PHY PAD Voltage Controller register.
	94	Only valid when "marvell,armada-3700-sdhci" is selected.
	95	Two types: "sd" and "fixed-1-8v".
	96	If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning and is
	97	switched to 1.8V when later in higher speed mode.
	98	If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for eMMC.
	99	Please follow the examples with compatible "marvell,armada-3700-sdhci"
	100	in below.
	101
	102	Example:
	103	- For eMMC:
	104
	105	sdhci@aa0000 {
	106	compatible = "marvell,armada-ap806-sdhci";
	107	reg = <0xaa0000 0x1000>;
	108	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
	109	clocks = <&emmc_clk>;
	110	clock-names = "core";
	111	bus-width = <4>;
	112	marvell,xenon-phy-slow-mode;
	113	marvell,xenon-tun-count = <11>;
	114	non-removable;
	115	no-sd;
	116	no-sdio;
	117
	118	/* Vmmc and Vqmmc are both fixed */
	119	};
	120
	121	- For SD/SDIO:
	122
	123	sdhci@ab0000 {
	124	compatible = "marvell,armada-cp110-sdhci";
	125	reg = <0xab0000 0x1000>;
	126	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
	127	vqmmc-supply = <&sd_vqmmc_regulator>;
	128	vmmc-supply = <&sd_vmmc_regulator>;
	129	clocks = <&sdclk>;
	130	clock-names = "core";
	131	bus-width = <4>;
	132	marvell,xenon-tun-count = <9>;
	133	};
	134
	135	- For eMMC with compatible "marvell,armada-3700-sdhci":
	136
	137	sdhci@aa0000 {
	138	compatible = "marvell,armada-3700-sdhci";
	139	reg = <0xaa0000 0x1000>,
	140	<phy_addr 0x4>;
	141	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
	142	clocks = <&emmcclk>;
	143	clock-names = "core";
	144	bus-width = <8>;
	145	mmc-ddr-1_8v;
	146	mmc-hs400-1_8v;
	147	non-removable;
	148	no-sd;
	149	no-sdio;
	150
	151	/* Vmmc and Vqmmc are both fixed */
	152
	153	marvell,pad-type = "fixed-1-8v";
	154	};
	155
	156	- For SD/SDIO with compatible "marvell,armada-3700-sdhci":
	157
	158	sdhci@ab0000 {
	159	compatible = "marvell,armada-3700-sdhci";
	160	reg = <0xab0000 0x1000>,
	161	<phy_addr 0x4>;
	162	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
	163	vqmmc-supply = <&sd_regulator>;
	164	/* Vmmc is fixed */
	165	clocks = <&sdclk>;
	166	clock-names = "core";
	167	bus-width = <4>;
	168
	169	marvell,pad-type = "sd";
	170	};