aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/boot/dts/stih407-clock.dtsi18
-rw-r--r--arch/arm/boot/dts/stih410-clock.dtsi16
-rw-r--r--arch/arm/boot/dts/stih418-clock.dtsi16
3 files changed, 25 insertions, 25 deletions
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index ad45f5e8fac7..38a56d7edab3 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -42,7 +42,7 @@
42 42
43 clockgen_a9_pll: clockgen-a9-pll { 43 clockgen_a9_pll: clockgen-a9-pll {
44 #clock-cells = <1>; 44 #clock-cells = <1>;
45 compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; 45 compatible = "st,stih407-clkgen-plla9";
46 46
47 clocks = <&clk_sysin>; 47 clocks = <&clk_sysin>;
48 48
@@ -55,7 +55,7 @@
55 */ 55 */
56 clk_m_a9: clk-m-a9@92b0000 { 56 clk_m_a9: clk-m-a9@92b0000 {
57 #clock-cells = <0>; 57 #clock-cells = <0>;
58 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; 58 compatible = "st,stih407-clkgen-a9-mux";
59 reg = <0x92b0000 0x10000>; 59 reg = <0x92b0000 0x10000>;
60 60
61 clocks = <&clockgen_a9_pll 0>, 61 clocks = <&clockgen_a9_pll 0>,
@@ -96,7 +96,7 @@
96 96
97 clk_s_a0_pll: clk-s-a0-pll { 97 clk_s_a0_pll: clk-s-a0-pll {
98 #clock-cells = <1>; 98 #clock-cells = <1>;
99 compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; 99 compatible = "st,clkgen-pll0";
100 100
101 clocks = <&clk_sysin>; 101 clocks = <&clk_sysin>;
102 102
@@ -117,7 +117,7 @@
117 117
118 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { 118 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
119 #clock-cells = <1>; 119 #clock-cells = <1>;
120 compatible = "st,stih407-quadfs660-C", "st,quadfs"; 120 compatible = "st,quadfs-pll";
121 reg = <0x9103000 0x1000>; 121 reg = <0x9103000 0x1000>;
122 122
123 clocks = <&clk_sysin>; 123 clocks = <&clk_sysin>;
@@ -134,7 +134,7 @@
134 134
135 clk_s_c0_pll0: clk-s-c0-pll0 { 135 clk_s_c0_pll0: clk-s-c0-pll0 {
136 #clock-cells = <1>; 136 #clock-cells = <1>;
137 compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; 137 compatible = "st,clkgen-pll0";
138 138
139 clocks = <&clk_sysin>; 139 clocks = <&clk_sysin>;
140 140
@@ -143,7 +143,7 @@
143 143
144 clk_s_c0_pll1: clk-s-c0-pll1 { 144 clk_s_c0_pll1: clk-s-c0-pll1 {
145 #clock-cells = <1>; 145 #clock-cells = <1>;
146 compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; 146 compatible = "st,clkgen-pll1";
147 147
148 clocks = <&clk_sysin>; 148 clocks = <&clk_sysin>;
149 149
@@ -199,7 +199,7 @@
199 199
200 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { 200 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
201 #clock-cells = <1>; 201 #clock-cells = <1>;
202 compatible = "st,stih407-quadfs660-D", "st,quadfs"; 202 compatible = "st,quadfs";
203 reg = <0x9104000 0x1000>; 203 reg = <0x9104000 0x1000>;
204 204
205 clocks = <&clk_sysin>; 205 clocks = <&clk_sysin>;
@@ -233,7 +233,7 @@
233 233
234 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { 234 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
235 #clock-cells = <1>; 235 #clock-cells = <1>;
236 compatible = "st,stih407-quadfs660-D", "st,quadfs"; 236 compatible = "st,quadfs";
237 reg = <0x9106000 0x1000>; 237 reg = <0x9106000 0x1000>;
238 238
239 clocks = <&clk_sysin>; 239 clocks = <&clk_sysin>;
@@ -287,7 +287,7 @@
287 287
288 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { 288 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
289 #clock-cells = <1>; 289 #clock-cells = <1>;
290 compatible = "st,stih407-quadfs660-D", "st,quadfs"; 290 compatible = "st,quadfs";
291 reg = <0x9107000 0x1000>; 291 reg = <0x9107000 0x1000>;
292 292
293 clocks = <&clk_sysin>; 293 clocks = <&clk_sysin>;
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
index fd5049682181..e8f4d4421e62 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -44,7 +44,7 @@
44 44
45 clockgen_a9_pll: clockgen-a9-pll { 45 clockgen_a9_pll: clockgen-a9-pll {
46 #clock-cells = <1>; 46 #clock-cells = <1>;
47 compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; 47 compatible = "st,stih407-clkgen-plla9";
48 48
49 clocks = <&clk_sysin>; 49 clocks = <&clk_sysin>;
50 50
@@ -98,7 +98,7 @@
98 98
99 clk_s_a0_pll: clk-s-a0-pll { 99 clk_s_a0_pll: clk-s-a0-pll {
100 #clock-cells = <1>; 100 #clock-cells = <1>;
101 compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; 101 compatible = "st,clkgen-pll0";
102 102
103 clocks = <&clk_sysin>; 103 clocks = <&clk_sysin>;
104 104
@@ -122,7 +122,7 @@
122 122
123 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { 123 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
124 #clock-cells = <1>; 124 #clock-cells = <1>;
125 compatible = "st,stih407-quadfs660-C", "st,quadfs"; 125 compatible = "st,quadfs-pll";
126 reg = <0x9103000 0x1000>; 126 reg = <0x9103000 0x1000>;
127 127
128 clocks = <&clk_sysin>; 128 clocks = <&clk_sysin>;
@@ -140,7 +140,7 @@
140 140
141 clk_s_c0_pll0: clk-s-c0-pll0 { 141 clk_s_c0_pll0: clk-s-c0-pll0 {
142 #clock-cells = <1>; 142 #clock-cells = <1>;
143 compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; 143 compatible = "st,clkgen-pll0";
144 144
145 clocks = <&clk_sysin>; 145 clocks = <&clk_sysin>;
146 146
@@ -150,7 +150,7 @@
150 150
151 clk_s_c0_pll1: clk-s-c0-pll1 { 151 clk_s_c0_pll1: clk-s-c0-pll1 {
152 #clock-cells = <1>; 152 #clock-cells = <1>;
153 compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; 153 compatible = "st,clkgen-pll1";
154 154
155 clocks = <&clk_sysin>; 155 clocks = <&clk_sysin>;
156 156
@@ -218,7 +218,7 @@
218 218
219 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { 219 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
220 #clock-cells = <1>; 220 #clock-cells = <1>;
221 compatible = "st,stih407-quadfs660-D", "st,quadfs"; 221 compatible = "st,quadfs";
222 reg = <0x9104000 0x1000>; 222 reg = <0x9104000 0x1000>;
223 223
224 clocks = <&clk_sysin>; 224 clocks = <&clk_sysin>;
@@ -254,7 +254,7 @@
254 254
255 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { 255 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
256 #clock-cells = <1>; 256 #clock-cells = <1>;
257 compatible = "st,stih407-quadfs660-D", "st,quadfs"; 257 compatible = "st,quadfs";
258 reg = <0x9106000 0x1000>; 258 reg = <0x9106000 0x1000>;
259 259
260 clocks = <&clk_sysin>; 260 clocks = <&clk_sysin>;
@@ -308,7 +308,7 @@
308 308
309 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { 309 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
310 #clock-cells = <1>; 310 #clock-cells = <1>;
311 compatible = "st,stih407-quadfs660-D", "st,quadfs"; 311 compatible = "st,quadfs";
312 reg = <0x9107000 0x1000>; 312 reg = <0x9107000 0x1000>;
313 313
314 clocks = <&clk_sysin>; 314 clocks = <&clk_sysin>;
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
index ae6d9978ea19..0fd0fa54132c 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -44,7 +44,7 @@
44 44
45 clockgen_a9_pll: clockgen-a9-pll { 45 clockgen_a9_pll: clockgen-a9-pll {
46 #clock-cells = <1>; 46 #clock-cells = <1>;
47 compatible = "st,stih418-plls-c28-a9", "st,clkgen-plls-c32"; 47 compatible = "st,stih418-clkgen-plla9";
48 48
49 clocks = <&clk_sysin>; 49 clocks = <&clk_sysin>;
50 50
@@ -98,7 +98,7 @@
98 98
99 clk_s_a0_pll: clk-s-a0-pll { 99 clk_s_a0_pll: clk-s-a0-pll {
100 #clock-cells = <1>; 100 #clock-cells = <1>;
101 compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; 101 compatible = "st,clkgen-pll0";
102 102
103 clocks = <&clk_sysin>; 103 clocks = <&clk_sysin>;
104 104
@@ -120,7 +120,7 @@
120 120
121 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { 121 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
122 #clock-cells = <1>; 122 #clock-cells = <1>;
123 compatible = "st,stih407-quadfs660-C", "st,quadfs"; 123 compatible = "st,quadfs-pll";
124 reg = <0x9103000 0x1000>; 124 reg = <0x9103000 0x1000>;
125 125
126 clocks = <&clk_sysin>; 126 clocks = <&clk_sysin>;
@@ -137,7 +137,7 @@
137 137
138 clk_s_c0_pll0: clk-s-c0-pll0 { 138 clk_s_c0_pll0: clk-s-c0-pll0 {
139 #clock-cells = <1>; 139 #clock-cells = <1>;
140 compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; 140 compatible = "st,clkgen-pll0";
141 141
142 clocks = <&clk_sysin>; 142 clocks = <&clk_sysin>;
143 143
@@ -146,7 +146,7 @@
146 146
147 clk_s_c0_pll1: clk-s-c0-pll1 { 147 clk_s_c0_pll1: clk-s-c0-pll1 {
148 #clock-cells = <1>; 148 #clock-cells = <1>;
149 compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; 149 compatible = "st,clkgen-pll1";
150 150
151 clocks = <&clk_sysin>; 151 clocks = <&clk_sysin>;
152 152
@@ -212,7 +212,7 @@
212 212
213 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { 213 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
214 #clock-cells = <1>; 214 #clock-cells = <1>;
215 compatible = "st,stih407-quadfs660-D", "st,quadfs"; 215 compatible = "st,quadfs";
216 reg = <0x9104000 0x1000>; 216 reg = <0x9104000 0x1000>;
217 217
218 clocks = <&clk_sysin>; 218 clocks = <&clk_sysin>;
@@ -248,7 +248,7 @@
248 248
249 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { 249 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
250 #clock-cells = <1>; 250 #clock-cells = <1>;
251 compatible = "st,stih407-quadfs660-D", "st,quadfs"; 251 compatible = "st,quadfs";
252 reg = <0x9106000 0x1000>; 252 reg = <0x9106000 0x1000>;
253 253
254 clocks = <&clk_sysin>; 254 clocks = <&clk_sysin>;
@@ -309,7 +309,7 @@
309 309
310 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { 310 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
311 #clock-cells = <1>; 311 #clock-cells = <1>;
312 compatible = "st,stih407-quadfs660-D", "st,quadfs"; 312 compatible = "st,quadfs";
313 reg = <0x9107000 0x1000>; 313 reg = <0x9107000 0x1000>;
314 314
315 clocks = <&clk_sysin>; 315 clocks = <&clk_sysin>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 20:15:57 -0400