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-rw-r--r--Documentation/x86/x86_64/5level-paging.txt9
-rw-r--r--arch/x86/Kconfig4
-rw-r--r--arch/x86/boot/compressed/misc.c16
-rw-r--r--arch/x86/include/asm/required-features.h8
4 files changed, 6 insertions, 31 deletions
diff --git a/Documentation/x86/x86_64/5level-paging.txt b/Documentation/x86/x86_64/5level-paging.txt
index 087251a0d99c..2432a5ef86d9 100644
--- a/Documentation/x86/x86_64/5level-paging.txt
+++ b/Documentation/x86/x86_64/5level-paging.txt
@@ -20,12 +20,9 @@ Documentation/x86/x86_64/mm.txt
20 20
21CONFIG_X86_5LEVEL=y enables the feature. 21CONFIG_X86_5LEVEL=y enables the feature.
22 22
23So far, a kernel compiled with the option enabled will be able to boot 23Kernel with CONFIG_X86_5LEVEL=y still able to boot on 4-level hardware.
24only on machines that supports the feature -- see for 'la57' flag in 24In this case additional page table level -- p4d -- will be folded at
25/proc/cpuinfo. 25runtime.
26
27The plan is to implement boot-time switching between 4- and 5-level paging
28in the future.
29 26
30== User-space and large virtual address space == 27== User-space and large virtual address space ==
31 28
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index fcc3f88996b3..1c4f7b6a94f4 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1440,8 +1440,8 @@ config X86_5LEVEL
1440 1440
1441 It will be supported by future Intel CPUs. 1441 It will be supported by future Intel CPUs.
1442 1442
1443 Note: a kernel with this option enabled can only be booted 1443 A kernel with the option enabled can be booted on machines that
1444 on machines that support the feature. 1444 support 4- or 5-level paging.
1445 1445
1446 See Documentation/x86/x86_64/5level-paging.txt for more 1446 See Documentation/x86/x86_64/5level-paging.txt for more
1447 information. 1447 information.
diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/misc.c
index 98761a1576ce..b50c42455e25 100644
--- a/arch/x86/boot/compressed/misc.c
+++ b/arch/x86/boot/compressed/misc.c
@@ -169,16 +169,6 @@ void __puthex(unsigned long value)
169 } 169 }
170} 170}
171 171
172static bool l5_supported(void)
173{
174 /* Check if leaf 7 is supported. */
175 if (native_cpuid_eax(0) < 7)
176 return 0;
177
178 /* Check if la57 is supported. */
179 return native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31));
180}
181
182#if CONFIG_X86_NEED_RELOCS 172#if CONFIG_X86_NEED_RELOCS
183static void handle_relocations(void *output, unsigned long output_len, 173static void handle_relocations(void *output, unsigned long output_len,
184 unsigned long virt_addr) 174 unsigned long virt_addr)
@@ -372,12 +362,6 @@ asmlinkage __visible void *extract_kernel(void *rmode, memptr heap,
372 console_init(); 362 console_init();
373 debug_putstr("early console in extract_kernel\n"); 363 debug_putstr("early console in extract_kernel\n");
374 364
375 if (IS_ENABLED(CONFIG_X86_5LEVEL) && !l5_supported()) {
376 error("This linux kernel as configured requires 5-level paging\n"
377 "This CPU does not support the required 'cr4.la57' feature\n"
378 "Unable to boot - please use a kernel appropriate for your CPU\n");
379 }
380
381 free_mem_ptr = heap; /* Heap */ 365 free_mem_ptr = heap; /* Heap */
382 free_mem_end_ptr = heap + BOOT_HEAP_SIZE; 366 free_mem_end_ptr = heap + BOOT_HEAP_SIZE;
383 367
diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h
index fb3a6de7440b..6847d85400a8 100644
--- a/arch/x86/include/asm/required-features.h
+++ b/arch/x86/include/asm/required-features.h
@@ -53,12 +53,6 @@
53# define NEED_MOVBE 0 53# define NEED_MOVBE 0
54#endif 54#endif
55 55
56#ifdef CONFIG_X86_5LEVEL
57# define NEED_LA57 (1<<(X86_FEATURE_LA57 & 31))
58#else
59# define NEED_LA57 0
60#endif
61
62#ifdef CONFIG_X86_64 56#ifdef CONFIG_X86_64
63#ifdef CONFIG_PARAVIRT 57#ifdef CONFIG_PARAVIRT
64/* Paravirtualized systems may not have PSE or PGE available */ 58/* Paravirtualized systems may not have PSE or PGE available */
@@ -104,7 +98,7 @@
104#define REQUIRED_MASK13 0 98#define REQUIRED_MASK13 0
105#define REQUIRED_MASK14 0 99#define REQUIRED_MASK14 0
106#define REQUIRED_MASK15 0 100#define REQUIRED_MASK15 0
107#define REQUIRED_MASK16 (NEED_LA57) 101#define REQUIRED_MASK16 0
108#define REQUIRED_MASK17 0 102#define REQUIRED_MASK17 0
109#define REQUIRED_MASK18 0 103#define REQUIRED_MASK18 0
110#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19) 104#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)