12 files changed, 101 insertions, 55 deletions

diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 5a9b87b7993e..c1eb1ff7c800 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -1619,6 +1619,12 @@ static int __init octeon_irq_init_gpio(
                 return -ENOMEM;
         }
 
+        /*
+         * Clear the OF_POPULATED flag that was set by of_irq_init()
+         * so that all GPIO devices will be probed.
+         */
+        of_node_clear_flag(gpio_node, OF_POPULATED);
+
         return 0;
 }
 /*
diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S
index d7b99180c6e1..1910223a9c02 100644
--- a/arch/mips/dec/int-handler.S
+++ b/arch/mips/dec/int-handler.S
@@ -146,7 +146,25 @@
                 /*
                  * Find irq with highest priority
                  */
-                 PTR_LA t1,cpu_mask_nr_tbl
+                # open coded PTR_LA t1, cpu_mask_nr_tbl
+#if (_MIPS_SZPTR == 32)
+                # open coded la t1, cpu_mask_nr_tbl
+                lui     t1, %hi(cpu_mask_nr_tbl)
+                addiu   t1, %lo(cpu_mask_nr_tbl)
+
+#endif
+#if (_MIPS_SZPTR == 64)
+                # open coded dla t1, cpu_mask_nr_tbl
+                .set    push
+                .set    noat
+                lui     t1, %highest(cpu_mask_nr_tbl)
+                lui     AT, %hi(cpu_mask_nr_tbl)
+                daddiu  t1, t1, %higher(cpu_mask_nr_tbl)
+                daddiu  AT, AT, %lo(cpu_mask_nr_tbl)
+                dsll    t1, 32
+                daddu   t1, t1, AT
+                .set    pop
+#endif
 1:              lw      t2,(t1)
                 nop
                 and     t2,t0
@@ -195,7 +213,25 @@
                 /*
                  * Find irq with highest priority
                  */
-                 PTR_LA t1,asic_mask_nr_tbl
+                # open coded PTR_LA t1,asic_mask_nr_tbl
+#if (_MIPS_SZPTR == 32)
+                # open coded la t1, asic_mask_nr_tbl
+                lui     t1, %hi(asic_mask_nr_tbl)
+                addiu   t1, %lo(asic_mask_nr_tbl)
+
+#endif
+#if (_MIPS_SZPTR == 64)
+                # open coded dla t1, asic_mask_nr_tbl
+                .set    push
+                .set    noat
+                lui     t1, %highest(asic_mask_nr_tbl)
+                lui     AT, %hi(asic_mask_nr_tbl)
+                daddiu  t1, t1, %higher(asic_mask_nr_tbl)
+                daddiu  AT, AT, %lo(asic_mask_nr_tbl)
+                dsll    t1, 32
+                daddu   t1, t1, AT
+                .set    pop
+#endif
 2:              lw      t2,(t1)
                 nop
                 and     t2,t0
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index 58e7874e9347..4fafeefe65c2 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -458,10 +458,21 @@ static inline int mips_cm_revision(void)
 static inline unsigned int mips_cm_max_vp_width(void)
 {
         extern int smp_num_siblings;
+        uint32_t cfg;
 
         if (mips_cm_revision() >= CM_REV_CM3)
                 return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW_MSK;
 
+        if (mips_cm_present()) {
+                /*
+                 * We presume that all cores in the system will have the same
+                 * number of VP(E)s, and if that ever changes then this will
+                 * need revisiting.
+                 */
+                cfg = read_gcr_cl_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
+                return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
+        }
+
         if (IS_ENABLED(CONFIG_SMP))
                 return smp_num_siblings;
 
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index def9d8d13f6e..7dd2dd47909a 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -660,8 +660,6 @@
 
 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
-/* FTLB probability bits for R6 */
-#define MIPS_CONF7_FTLBP_SHIFT  (18)
 
 /* WatchLo* register definitions */
 #define MIPS_WATCHLO_IRW        (_ULCAST_(0x7) << 0)
diff --git a/arch/mips/include/asm/uprobes.h b/arch/mips/include/asm/uprobes.h
index 34c325c674c4..70a4a2f173ff 100644
--- a/arch/mips/include/asm/uprobes.h
+++ b/arch/mips/include/asm/uprobes.h
@@ -36,7 +36,6 @@ struct arch_uprobe {
         unsigned long   resume_epc;
         u32     insn[2];
         u32     ixol[2];
-        union   mips_instruction orig_inst[MAX_UINSN_BYTES / 4];
 };
 
 struct arch_uprobe_task {
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index a88d44247cc8..dd3175442c9e 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -352,7 +352,12 @@ __setup("nohtw", htw_disable);
 static int mips_ftlb_disabled;
 static int mips_has_ftlb_configured;
 
-static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
+enum ftlb_flags {
+        FTLB_EN         = 1 << 0,
+        FTLB_SET_PROB   = 1 << 1,
+};
+
+static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
 
 static int __init ftlb_disable(char *s)
 {
@@ -371,8 +376,6 @@ static int __init ftlb_disable(char *s)
                 return 1;
         }
 
-        back_to_back_c0_hazard();
-
         config4 = read_c0_config4();
 
         /* Check that FTLB has been disabled */
@@ -531,7 +534,7 @@ static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
                 return 3;
 }
 
-static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
+static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
 {
         unsigned int config;
 
@@ -542,33 +545,33 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
         case CPU_P6600:
                 /* proAptiv & related cores use Config6 to enable the FTLB */
                 config = read_c0_config6();
-                /* Clear the old probability value */
-                config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
-                if (enable)
-                        /* Enable FTLB */
-                        write_c0_config6(config |
-                                         (calculate_ftlb_probability(c)
-                                          << MIPS_CONF6_FTLBP_SHIFT)
-                                         | MIPS_CONF6_FTLBEN);
+
+                if (flags & FTLB_EN)
+                        config |= MIPS_CONF6_FTLBEN;
                 else
-                        /* Disable FTLB */
-                        write_c0_config6(config &  ~MIPS_CONF6_FTLBEN);
+                        config &= ~MIPS_CONF6_FTLBEN;
+
+                if (flags & FTLB_SET_PROB) {
+                        config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
+                        config |= calculate_ftlb_probability(c)
+                                  << MIPS_CONF6_FTLBP_SHIFT;
+                }
+
+                write_c0_config6(config);
+                back_to_back_c0_hazard();
                 break;
         case CPU_I6400:
-                /* I6400 & related cores use Config7 to configure FTLB */
-                config = read_c0_config7();
-                /* Clear the old probability value */
-                config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
-                write_c0_config7(config | (calculate_ftlb_probability(c)
-                                           << MIPS_CONF7_FTLBP_SHIFT));
-                break;
+                /* There's no way to disable the FTLB */
+                if (!(flags & FTLB_EN))
+                        return 1;
+                return 0;
         case CPU_LOONGSON3:
                 /* Flush ITLB, DTLB, VTLB and FTLB */
                 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
                               LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
                 /* Loongson-3 cores use Config6 to enable the FTLB */
                 config = read_c0_config6();
-                if (enable)
+                if (flags & FTLB_EN)
                         /* Enable FTLB */
                         write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
                 else
@@ -788,6 +791,7 @@ static inline unsigned int decode_config4(struct cpuinfo_mips *c)
                                        PAGE_SIZE, config4);
                                 /* Switch FTLB off */
                                 set_ftlb_enable(c, 0);
+                                mips_ftlb_disabled = 1;
                                 break;
                         }
                         c->tlbsizeftlbsets = 1 <<
@@ -852,7 +856,7 @@ static void decode_configs(struct cpuinfo_mips *c)
         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 
         /* Enable FTLB if present and not disabled */
-        set_ftlb_enable(c, !mips_ftlb_disabled);
+        set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
 
         ok = decode_config0(c);                 /* Read Config registers.  */
         BUG_ON(!ok);                            /* Arch spec violation!  */
@@ -902,6 +906,9 @@ static void decode_configs(struct cpuinfo_mips *c)
                 }
         }
 
+        /* configure the FTLB write probability */
+        set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
+
         mips_probe_watch_registers(c);
 
 #ifndef CONFIG_MIPS_CPS
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 17326a90d53c..dc0b29612891 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -142,9 +142,8 @@ LEAF(__r4k_wait)
         PTR_LA  k1, __r4k_wait
         ori     k0, 0x1f        /* 32 byte rollback region */
         xori    k0, 0x1f
-        bne     k0, k1, 9f
+        bne     k0, k1, \handler
         MTC0    k0, CP0_EPC
-9:
         .set pop
         .endm
 
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 3be0e6ba2797..0d57909d9026 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -764,7 +764,6 @@ static void __init arch_mem_init(char **cmdline_p)
         device_tree_init();
         sparse_init();
         plat_swiotlb_setup();
-        paging_init();
 
         dma_contiguous_reserve(PFN_PHYS(max_low_pfn));
         /* Tell bootmem about cma reserved memblock section */
@@ -877,6 +876,7 @@ void __init setup_arch(char **cmdline_p)
         prefill_possible_map();
 
         cpu_cache_init();
+        paging_init();
 }
 
 unsigned long kernelsp[NR_CPUS];
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index e9d9fc6c754c..6183ad84cc73 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -513,7 +513,7 @@ static void cps_cpu_die(unsigned int cpu)
                  * in which case the CPC will refuse to power down the core.
                  */
                 do {
-                        mips_cm_lock_other(core, vpe_id);
+                        mips_cm_lock_other(core, 0);
                         mips_cpc_lock_other(core);
                         stat = read_cpc_co_stat_conf();
                         stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK;
diff --git a/arch/mips/kernel/uprobes.c b/arch/mips/kernel/uprobes.c
index 1149b30c9aeb..4c7c1558944a 100644
--- a/arch/mips/kernel/uprobes.c
+++ b/arch/mips/kernel/uprobes.c
@@ -157,7 +157,6 @@ bool is_trap_insn(uprobe_opcode_t *insn)
 int arch_uprobe_pre_xol(struct arch_uprobe *aup, struct pt_regs *regs)
 {
         struct uprobe_task *utask = current->utask;
-        union mips_instruction insn;
 
         /*
          * Now find the EPC where to resume after the breakpoint has been
@@ -168,10 +167,10 @@ int arch_uprobe_pre_xol(struct arch_uprobe *aup, struct pt_regs *regs)
                 unsigned long epc;
 
                 epc = regs->cp0_epc;
-                __compute_return_epc_for_insn(regs, insn);
+                __compute_return_epc_for_insn(regs,
+                        (union mips_instruction) aup->insn[0]);
                 aup->resume_epc = regs->cp0_epc;
         }
-
         utask->autask.saved_trap_nr = current->thread.trap_nr;
         current->thread.trap_nr = UPROBE_TRAP_NR;
         regs->cp0_epc = current->utask->xol_vaddr;
@@ -257,7 +256,7 @@ unsigned long arch_uretprobe_hijack_return_addr(
         ra = regs->regs[31];
 
         /* Replace the return address with the trampoline address */
-        regs->regs[31] = ra;
+        regs->regs[31] = trampoline_vaddr;
 
         return ra;
 }
@@ -280,24 +279,6 @@ int __weak set_swbp(struct arch_uprobe *auprobe, struct mm_struct *mm,
         return uprobe_write_opcode(mm, vaddr, UPROBE_SWBP_INSN);
 }
 
-/**
- * set_orig_insn - Restore the original instruction.
- * @mm: the probed process address space.
- * @auprobe: arch specific probepoint information.
- * @vaddr: the virtual address to insert the opcode.
- *
- * For mm @mm, restore the original opcode (opcode) at @vaddr.
- * Return 0 (success) or a negative errno.
- *
- * This overrides the weak version in kernel/events/uprobes.c.
- */
-int set_orig_insn(struct arch_uprobe *auprobe, struct mm_struct *mm,
-                 unsigned long vaddr)
-{
-        return uprobe_write_opcode(mm, vaddr,
-                        *(uprobe_opcode_t *)&auprobe->orig_inst[0].word);
-}
-
 void __weak arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr,
                                   void *src, unsigned long len)
 {
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 2c3749d98f04..72f7478ee068 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -440,6 +440,9 @@ static inline void mem_init_free_highmem(void)
 #ifdef CONFIG_HIGHMEM
         unsigned long tmp;
 
+        if (cpu_has_dc_aliases)
+                return;
+
         for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
                 struct page *page = pfn_to_page(tmp);
 
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index ec5b21678fad..7e7364b0501e 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -39,6 +39,9 @@
 #include <linux/console.h>
 #endif
 
+#define ROCIT_CONFIG_GEN0               0x1f403000
+#define  ROCIT_CONFIG_GEN0_PCI_IOCU     BIT(7)
+
 extern void malta_be_init(void);
 extern int malta_be_handler(struct pt_regs *regs, int is_fixup);
 
@@ -107,6 +110,8 @@ static void __init fd_activate(void)
 static int __init plat_enable_iocoherency(void)
 {
         int supported = 0;
+        u32 cfg;
+
         if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
                 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
                         BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
@@ -129,7 +134,8 @@ static int __init plat_enable_iocoherency(void)
         } else if (mips_cm_numiocu() != 0) {
                 /* Nothing special needs to be done to enable coherency */
                 pr_info("CMP IOCU detected\n");
-                if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) {
+                cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
+                if (!(cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)) {
                         pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
                         return 0;
                 }