diff options
| -rw-r--r-- | sound/soc/codecs/rt5640.c | 2 | ||||
| -rw-r--r-- | sound/soc/codecs/rt5640.h | 36 |
2 files changed, 19 insertions, 19 deletions
diff --git a/sound/soc/codecs/rt5640.c b/sound/soc/codecs/rt5640.c index e8b5ba04417a..09e8988bbb2d 100644 --- a/sound/soc/codecs/rt5640.c +++ b/sound/soc/codecs/rt5640.c | |||
| @@ -359,7 +359,7 @@ static const DECLARE_TLV_DB_RANGE(bst_tlv, | |||
| 359 | 359 | ||
| 360 | /* Interface data select */ | 360 | /* Interface data select */ |
| 361 | static const char * const rt5640_data_select[] = { | 361 | static const char * const rt5640_data_select[] = { |
| 362 | "Normal", "left copy to right", "right copy to left", "Swap"}; | 362 | "Normal", "Swap", "left copy to right", "right copy to left"}; |
| 363 | 363 | ||
| 364 | static SOC_ENUM_SINGLE_DECL(rt5640_if1_dac_enum, RT5640_DIG_INF_DATA, | 364 | static SOC_ENUM_SINGLE_DECL(rt5640_if1_dac_enum, RT5640_DIG_INF_DATA, |
| 365 | RT5640_IF1_DAC_SEL_SFT, rt5640_data_select); | 365 | RT5640_IF1_DAC_SEL_SFT, rt5640_data_select); |
diff --git a/sound/soc/codecs/rt5640.h b/sound/soc/codecs/rt5640.h index 1761c3a98b76..58b664b06c16 100644 --- a/sound/soc/codecs/rt5640.h +++ b/sound/soc/codecs/rt5640.h | |||
| @@ -443,39 +443,39 @@ | |||
| 443 | #define RT5640_IF1_DAC_SEL_MASK (0x3 << 14) | 443 | #define RT5640_IF1_DAC_SEL_MASK (0x3 << 14) |
| 444 | #define RT5640_IF1_DAC_SEL_SFT 14 | 444 | #define RT5640_IF1_DAC_SEL_SFT 14 |
| 445 | #define RT5640_IF1_DAC_SEL_NOR (0x0 << 14) | 445 | #define RT5640_IF1_DAC_SEL_NOR (0x0 << 14) |
| 446 | #define RT5640_IF1_DAC_SEL_L2R (0x1 << 14) | 446 | #define RT5640_IF1_DAC_SEL_SWAP (0x1 << 14) |
| 447 | #define RT5640_IF1_DAC_SEL_R2L (0x2 << 14) | 447 | #define RT5640_IF1_DAC_SEL_L2R (0x2 << 14) |
| 448 | #define RT5640_IF1_DAC_SEL_SWAP (0x3 << 14) | 448 | #define RT5640_IF1_DAC_SEL_R2L (0x3 << 14) |
| 449 | #define RT5640_IF1_ADC_SEL_MASK (0x3 << 12) | 449 | #define RT5640_IF1_ADC_SEL_MASK (0x3 << 12) |
| 450 | #define RT5640_IF1_ADC_SEL_SFT 12 | 450 | #define RT5640_IF1_ADC_SEL_SFT 12 |
| 451 | #define RT5640_IF1_ADC_SEL_NOR (0x0 << 12) | 451 | #define RT5640_IF1_ADC_SEL_NOR (0x0 << 12) |
| 452 | #define RT5640_IF1_ADC_SEL_L2R (0x1 << 12) | 452 | #define RT5640_IF1_ADC_SEL_SWAP (0x1 << 12) |
| 453 | #define RT5640_IF1_ADC_SEL_R2L (0x2 << 12) | 453 | #define RT5640_IF1_ADC_SEL_L2R (0x2 << 12) |
| 454 | #define RT5640_IF1_ADC_SEL_SWAP (0x3 << 12) | 454 | #define RT5640_IF1_ADC_SEL_R2L (0x3 << 12) |
| 455 | #define RT5640_IF2_DAC_SEL_MASK (0x3 << 10) | 455 | #define RT5640_IF2_DAC_SEL_MASK (0x3 << 10) |
| 456 | #define RT5640_IF2_DAC_SEL_SFT 10 | 456 | #define RT5640_IF2_DAC_SEL_SFT 10 |
| 457 | #define RT5640_IF2_DAC_SEL_NOR (0x0 << 10) | 457 | #define RT5640_IF2_DAC_SEL_NOR (0x0 << 10) |
| 458 | #define RT5640_IF2_DAC_SEL_L2R (0x1 << 10) | 458 | #define RT5640_IF2_DAC_SEL_SWAP (0x1 << 10) |
| 459 | #define RT5640_IF2_DAC_SEL_R2L (0x2 << 10) | 459 | #define RT5640_IF2_DAC_SEL_L2R (0x2 << 10) |
| 460 | #define RT5640_IF2_DAC_SEL_SWAP (0x3 << 10) | 460 | #define RT5640_IF2_DAC_SEL_R2L (0x3 << 10) |
| 461 | #define RT5640_IF2_ADC_SEL_MASK (0x3 << 8) | 461 | #define RT5640_IF2_ADC_SEL_MASK (0x3 << 8) |
| 462 | #define RT5640_IF2_ADC_SEL_SFT 8 | 462 | #define RT5640_IF2_ADC_SEL_SFT 8 |
| 463 | #define RT5640_IF2_ADC_SEL_NOR (0x0 << 8) | 463 | #define RT5640_IF2_ADC_SEL_NOR (0x0 << 8) |
| 464 | #define RT5640_IF2_ADC_SEL_L2R (0x1 << 8) | 464 | #define RT5640_IF2_ADC_SEL_SWAP (0x1 << 8) |
| 465 | #define RT5640_IF2_ADC_SEL_R2L (0x2 << 8) | 465 | #define RT5640_IF2_ADC_SEL_L2R (0x2 << 8) |
| 466 | #define RT5640_IF2_ADC_SEL_SWAP (0x3 << 8) | 466 | #define RT5640_IF2_ADC_SEL_R2L (0x3 << 8) |
| 467 | #define RT5640_IF3_DAC_SEL_MASK (0x3 << 6) | 467 | #define RT5640_IF3_DAC_SEL_MASK (0x3 << 6) |
| 468 | #define RT5640_IF3_DAC_SEL_SFT 6 | 468 | #define RT5640_IF3_DAC_SEL_SFT 6 |
| 469 | #define RT5640_IF3_DAC_SEL_NOR (0x0 << 6) | 469 | #define RT5640_IF3_DAC_SEL_NOR (0x0 << 6) |
| 470 | #define RT5640_IF3_DAC_SEL_L2R (0x1 << 6) | 470 | #define RT5640_IF3_DAC_SEL_SWAP (0x1 << 6) |
| 471 | #define RT5640_IF3_DAC_SEL_R2L (0x2 << 6) | 471 | #define RT5640_IF3_DAC_SEL_L2R (0x2 << 6) |
| 472 | #define RT5640_IF3_DAC_SEL_SWAP (0x3 << 6) | 472 | #define RT5640_IF3_DAC_SEL_R2L (0x3 << 6) |
| 473 | #define RT5640_IF3_ADC_SEL_MASK (0x3 << 4) | 473 | #define RT5640_IF3_ADC_SEL_MASK (0x3 << 4) |
| 474 | #define RT5640_IF3_ADC_SEL_SFT 4 | 474 | #define RT5640_IF3_ADC_SEL_SFT 4 |
| 475 | #define RT5640_IF3_ADC_SEL_NOR (0x0 << 4) | 475 | #define RT5640_IF3_ADC_SEL_NOR (0x0 << 4) |
| 476 | #define RT5640_IF3_ADC_SEL_L2R (0x1 << 4) | 476 | #define RT5640_IF3_ADC_SEL_SWAP (0x1 << 4) |
| 477 | #define RT5640_IF3_ADC_SEL_R2L (0x2 << 4) | 477 | #define RT5640_IF3_ADC_SEL_L2R (0x2 << 4) |
| 478 | #define RT5640_IF3_ADC_SEL_SWAP (0x3 << 4) | 478 | #define RT5640_IF3_ADC_SEL_R2L (0x3 << 4) |
| 479 | 479 | ||
| 480 | /* REC Left Mixer Control 1 (0x3b) */ | 480 | /* REC Left Mixer Control 1 (0x3b) */ |
| 481 | #define RT5640_G_HP_L_RM_L_MASK (0x7 << 13) | 481 | #define RT5640_G_HP_L_RM_L_MASK (0x7 << 13) |
