3 files changed, 46 insertions, 0 deletions

diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/include/asm/intel_rdt.h
index 4a9005766d96..bd184e1fd207 100644
--- a/arch/x86/include/asm/intel_rdt.h
+++ b/arch/x86/include/asm/intel_rdt.h
@@ -181,6 +181,7 @@ struct rdt_resource {
 void rdt_get_cache_infofile(struct rdt_resource *r);
 void rdt_get_mba_infofile(struct rdt_resource *r);
 int parse_cbm(char *buf, struct rdt_resource *r, struct rdt_domain *d);
+int parse_bw(char *buf, struct rdt_resource *r,  struct rdt_domain *d);
 
 extern struct mutex rdtgroup_mutex;
 
diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index 1e410ea6905e..731f70ae57d0 100644
--- a/arch/x86/kernel/cpu/intel_rdt.c
+++ b/arch/x86/kernel/cpu/intel_rdt.c
@@ -116,6 +116,8 @@ struct rdt_resource rdt_resources_all[] = {
                 .msr_base               = IA32_MBA_THRTL_BASE,
                 .msr_update             = mba_wrmsr,
                 .cache_level            = 3,
+                .parse_ctrlval          = parse_bw,
+                .format_str             = "%d=%*d",
         },
 };
 
diff --git a/arch/x86/kernel/cpu/intel_rdt_schemata.c b/arch/x86/kernel/cpu/intel_rdt_schemata.c
index c72c9cc17aac..9467a00c947b 100644
--- a/arch/x86/kernel/cpu/intel_rdt_schemata.c
+++ b/arch/x86/kernel/cpu/intel_rdt_schemata.c
@@ -29,6 +29,49 @@
 #include <asm/intel_rdt.h>
 
 /*
+ * Check whether MBA bandwidth percentage value is correct. The value is
+ * checked against the minimum and max bandwidth values specified by the
+ * hardware. The allocated bandwidth percentage is rounded to the next
+ * control step available on the hardware.
+ */
+static bool bw_validate(char *buf, unsigned long *data, struct rdt_resource *r)
+{
+        unsigned long bw;
+        int ret;
+
+        /*
+         * Only linear delay values is supported for current Intel SKUs.
+         */
+        if (!r->membw.delay_linear)
+                return false;
+
+        ret = kstrtoul(buf, 10, &bw);
+        if (ret)
+                return false;
+
+        if (bw < r->membw.min_bw || bw > r->default_ctrl)
+                return false;
+
+        *data = roundup(bw, (unsigned long)r->membw.bw_gran);
+        return true;
+}
+
+int parse_bw(char *buf, struct rdt_resource *r, struct rdt_domain *d)
+{
+        unsigned long data;
+
+        if (d->have_new_ctrl)
+                return -EINVAL;
+
+        if (!bw_validate(buf, &data, r))
+                return -EINVAL;
+        d->new_ctrl = data;
+        d->have_new_ctrl = true;
+
+        return 0;
+}
+
+/*
  * Check whether a cache bit mask is valid. The SDM says:
  *      Please note that all (and only) contiguous '1' combinations
  *      are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.).