4 files changed, 48 insertions, 48 deletions

diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt
index fa00e62e1cf6..a6671bd2c85a 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi.txt
+++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
@@ -13,16 +13,16 @@ Required properties:
 - power-domains: Should be <&mmcc MDSS_GDSC>.
 - clocks: Phandles to device clocks.
 - clock-names: the following clocks are required:
-  * "mdp_core_clk"
-  * "iface_clk"
-  * "bus_clk"
-  * "core_mmss_clk"
-  * "byte_clk"
-  * "pixel_clk"
-  * "core_clk"
+  * "mdp_core"
+  * "iface"
+  * "bus"
+  * "core_mmss"
+  * "byte"
+  * "pixel"
+  * "core"
   For DSIv2, we need an additional clock:
-   * "src_clk"
-- assigned-clocks: Parents of "byte_clk" and "pixel_clk" for the given platform.
+   * "src"
+- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
 - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
   by a DSI PHY block. See [1] for details on clock bindings.
 - vdd-supply: phandle to vdd regulator device node
@@ -101,7 +101,7 @@ Required properties:
 - power-domains: Should be <&mmcc MDSS_GDSC>.
 - clocks: Phandles to device clocks. See [1] for details on clock bindings.
 - clock-names: the following clocks are required:
-  * "iface_clk"
+  * "iface"
 - vddio-supply: phandle to vdd-io regulator device node
 
 Optional properties:
@@ -123,13 +123,13 @@ Example:
                 reg = <0xfd922800 0x200>;
                 power-domains = <&mmcc MDSS_GDSC>;
                 clock-names =
-                        "bus_clk",
-                        "byte_clk",
-                        "core_clk",
-                        "core_mmss_clk",
-                        "iface_clk",
-                        "mdp_core_clk",
-                        "pixel_clk";
+                        "bus",
+                        "byte",
+                        "core",
+                        "core_mmss",
+                        "iface",
+                        "mdp_core",
+                        "pixel";
                 clocks =
                         <&mmcc MDSS_AXI_CLK>,
                         <&mmcc MDSS_BYTE0_CLK>,
@@ -207,7 +207,7 @@ Example:
                 reg =   <0xfd922a00 0xd4>,
                         <0xfd922b00 0x2b0>,
                         <0xfd922d80 0x7b>;
-                clock-names = "iface_clk";
+                clock-names = "iface";
                 clocks = <&mmcc MDSS_AHB_CLK>;
                 #clock-cells = <1>;
                 vddio-supply = <&pma8084_l12>;
diff --git a/Documentation/devicetree/bindings/display/msm/edp.txt b/Documentation/devicetree/bindings/display/msm/edp.txt
index e63032be5401..95ce19ca7bc5 100644
--- a/Documentation/devicetree/bindings/display/msm/edp.txt
+++ b/Documentation/devicetree/bindings/display/msm/edp.txt
@@ -12,11 +12,11 @@ Required properties:
 - clocks: device clocks
   See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
 - clock-names: the following clocks are required:
-  * "core_clk"
-  * "iface_clk"
-  * "mdp_core_clk"
-  * "pixel_clk"
-  * "link_clk"
+  * "core"
+  * "iface"
+  * "mdp_core"
+  * "pixel"
+  * "link"
 - #clock-cells: The value should be 1.
 - vdda-supply: phandle to vdda regulator device node
 - lvl-vdd-supply: phandle to regulator device node which is used to supply power
@@ -41,11 +41,11 @@ Example:
                         interrupts = <12 0>;
                         power-domains = <&mmcc MDSS_GDSC>;
                         clock-names =
-                                "core_clk",
-                                "pixel_clk",
-                                "iface_clk",
-                                "link_clk",
-                                "mdp_core_clk";
+                                "core",
+                                "pixel",
+                                "iface",
+                                "link",
+                                "mdp_core";
                         clocks =
                                 <&mmcc MDSS_EDPAUX_CLK>,
                                 <&mmcc MDSS_EDPPIXEL_CLK>,
diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.txt b/Documentation/devicetree/bindings/display/msm/hdmi.txt
index 2d306f402d18..5f90a40da51b 100644
--- a/Documentation/devicetree/bindings/display/msm/hdmi.txt
+++ b/Documentation/devicetree/bindings/display/msm/hdmi.txt
@@ -64,9 +64,9 @@ Example:
                 interrupts = <GIC_SPI 79 0>;
                 power-domains = <&mmcc MDSS_GDSC>;
                 clock-names =
-                    "core_clk",
-                    "master_iface_clk",
-                    "slave_iface_clk";
+                    "core",
+                    "master_iface",
+                    "slave_iface";
                 clocks =
                     <&mmcc HDMI_APP_CLK>,
                     <&mmcc HDMI_M_AHB_CLK>,
@@ -92,7 +92,7 @@ Example:
                       <0x4a00500 0x100>;
                 #phy-cells = <0>;
                 power-domains = <&mmcc MDSS_GDSC>;
-                clock-names = "slave_iface_clk";
+                clock-names = "slave_iface";
                 clocks = <&mmcc HDMI_S_AHB_CLK>;
                 core-vdda-supply = <&pm8921_hdmi_mvs>;
         };
diff --git a/Documentation/devicetree/bindings/display/msm/mdp5.txt b/Documentation/devicetree/bindings/display/msm/mdp5.txt
index 30c11ea83754..1b31977a68ba 100644
--- a/Documentation/devicetree/bindings/display/msm/mdp5.txt
+++ b/Documentation/devicetree/bindings/display/msm/mdp5.txt
@@ -22,16 +22,16 @@ Required properties:
   Documentation/devicetree/bindings/power/power_domain.txt
 - clocks: device clocks. See ../clocks/clock-bindings.txt for details.
 - clock-names: the following clocks are required.
-  * "iface_clk"
-  * "bus_clk"
-  * "vsync_clk"
+  * "iface"
+  * "bus"
+  * "vsync"
 - #address-cells: number of address cells for the MDSS children. Should be 1.
 - #size-cells: Should be 1.
 - ranges: parent bus address space is the same as the child bus address space.
 
 Optional properties:
 - clock-names: the following clocks are optional:
-  * "lut_clk"
+  * "lut"
 
 MDP5:
 Required properties:
@@ -45,10 +45,10 @@ Required properties:
   through MDP block
 - clocks: device clocks. See ../clocks/clock-bindings.txt for details.
 - clock-names: the following clocks are required.
--   * "bus_clk"
--   * "iface_clk"
--   * "core_clk"
--   * "vsync_clk"
+-   * "bus"
+-   * "iface"
+-   * "core"
+-   * "vsync"
 - ports: contains the list of output ports from MDP. These connect to interfaces
   that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
   special case since it is a part of the MDP block itself).
@@ -77,7 +77,7 @@ Required properties:
 
 Optional properties:
 - clock-names: the following clocks are optional:
-  * "lut_clk"
+  * "lut"
 
 Example:
 
@@ -95,9 +95,9 @@ Example:
                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
                          <&gcc GCC_MDSS_AXI_CLK>,
                          <&gcc GCC_MDSS_VSYNC_CLK>;
-                clock-names = "iface_clk",
-                              "bus_clk",
-                              "vsync_clk"
+                clock-names = "iface",
+                              "bus",
+                              "vsync"
 
                 interrupts = <0 72 0>;
 
@@ -120,10 +120,10 @@ Example:
                                  <&gcc GCC_MDSS_AXI_CLK>,
                                  <&gcc GCC_MDSS_MDP_CLK>,
                                  <&gcc GCC_MDSS_VSYNC_CLK>;
-                        clock-names = "iface_clk",
-                                      "bus_clk",
-                                      "core_clk",
-                                      "vsync_clk";
+                        clock-names = "iface",
+                                      "bus",
+                                      "core",
+                                      "vsync";
 
                         ports {
                                 #address-cells = <1>;