1 files changed, 389 insertions, 0 deletions

diff --git a/include/dt-bindings/clock/px30-cru.h b/include/dt-bindings/clock/px30-cru.h
new file mode 100644
index 000000000000..00101479f7c4
--- /dev/null
+++ b/include/dt-bindings/clock/px30-cru.h
@@ -0,0 +1,389 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
+
+/* core clocks */
+#define PLL_APLL                1
+#define PLL_DPLL                2
+#define PLL_CPLL                3
+#define PLL_NPLL                4
+#define APLL_BOOST_H            5
+#define APLL_BOOST_L            6
+#define ARMCLK                  7
+
+/* sclk gates (special clocks) */
+#define USB480M                 14
+#define SCLK_PDM                15
+#define SCLK_I2S0_TX            16
+#define SCLK_I2S0_TX_OUT        17
+#define SCLK_I2S0_RX            18
+#define SCLK_I2S0_RX_OUT        19
+#define SCLK_I2S1               20
+#define SCLK_I2S1_OUT           21
+#define SCLK_I2S2               22
+#define SCLK_I2S2_OUT           23
+#define SCLK_UART1              24
+#define SCLK_UART2              25
+#define SCLK_UART3              26
+#define SCLK_UART4              27
+#define SCLK_UART5              28
+#define SCLK_I2C0               29
+#define SCLK_I2C1               30
+#define SCLK_I2C2               31
+#define SCLK_I2C3               32
+#define SCLK_I2C4               33
+#define SCLK_PWM0               34
+#define SCLK_PWM1               35
+#define SCLK_SPI0               36
+#define SCLK_SPI1               37
+#define SCLK_TIMER0             38
+#define SCLK_TIMER1             39
+#define SCLK_TIMER2             40
+#define SCLK_TIMER3             41
+#define SCLK_TIMER4             42
+#define SCLK_TIMER5             43
+#define SCLK_TSADC              44
+#define SCLK_SARADC             45
+#define SCLK_OTP                46
+#define SCLK_OTP_USR            47
+#define SCLK_CRYPTO             48
+#define SCLK_CRYPTO_APK         49
+#define SCLK_DDRC               50
+#define SCLK_ISP                51
+#define SCLK_CIF_OUT            52
+#define SCLK_RGA_CORE           53
+#define SCLK_VOPB_PWM           54
+#define SCLK_NANDC              55
+#define SCLK_SDIO               56
+#define SCLK_EMMC               57
+#define SCLK_SFC                58
+#define SCLK_SDMMC              59
+#define SCLK_OTG_ADP            60
+#define SCLK_GMAC_SRC           61
+#define SCLK_GMAC               62
+#define SCLK_GMAC_RX_TX         63
+#define SCLK_MAC_REF            64
+#define SCLK_MAC_REFOUT         65
+#define SCLK_MAC_OUT            66
+#define SCLK_SDMMC_DRV          67
+#define SCLK_SDMMC_SAMPLE       68
+#define SCLK_SDIO_DRV           69
+#define SCLK_SDIO_SAMPLE        70
+#define SCLK_EMMC_DRV           71
+#define SCLK_EMMC_SAMPLE        72
+#define SCLK_GPU                73
+#define SCLK_PVTM               74
+#define SCLK_CORE_VPU           75
+#define SCLK_GMAC_RMII          76
+#define SCLK_UART2_SRC          77
+#define SCLK_NANDC_DIV          78
+#define SCLK_NANDC_DIV50        79
+#define SCLK_SDIO_DIV           80
+#define SCLK_SDIO_DIV50         81
+#define SCLK_EMMC_DIV           82
+#define SCLK_EMMC_DIV50         83
+#define SCLK_DDRCLK             84
+#define SCLK_UART1_SRC          85
+
+/* dclk gates */
+#define DCLK_VOPB               150
+#define DCLK_VOPL               151
+
+/* aclk gates */
+#define ACLK_GPU                170
+#define ACLK_BUS_PRE            171
+#define ACLK_CRYPTO             172
+#define ACLK_VI_PRE             173
+#define ACLK_VO_PRE             174
+#define ACLK_VPU                175
+#define ACLK_PERI_PRE           176
+#define ACLK_GMAC               178
+#define ACLK_CIF                179
+#define ACLK_ISP                180
+#define ACLK_VOPB               181
+#define ACLK_VOPL               182
+#define ACLK_RGA                183
+#define ACLK_GIC                184
+#define ACLK_DCF                186
+#define ACLK_DMAC               187
+#define ACLK_BUS_SRC            188
+#define ACLK_PERI_SRC           189
+
+/* hclk gates */
+#define HCLK_BUS_PRE            240
+#define HCLK_CRYPTO             241
+#define HCLK_VI_PRE             242
+#define HCLK_VO_PRE             243
+#define HCLK_VPU                244
+#define HCLK_PERI_PRE           245
+#define HCLK_MMC_NAND           246
+#define HCLK_SDMMC              247
+#define HCLK_USB                248
+#define HCLK_CIF                249
+#define HCLK_ISP                250
+#define HCLK_VOPB               251
+#define HCLK_VOPL               252
+#define HCLK_RGA                253
+#define HCLK_NANDC              254
+#define HCLK_SDIO               255
+#define HCLK_EMMC               256
+#define HCLK_SFC                257
+#define HCLK_OTG                258
+#define HCLK_HOST               259
+#define HCLK_HOST_ARB           260
+#define HCLK_PDM                261
+#define HCLK_I2S0               262
+#define HCLK_I2S1               263
+#define HCLK_I2S2               264
+
+/* pclk gates */
+#define PCLK_BUS_PRE            320
+#define PCLK_DDR                321
+#define PCLK_VO_PRE             322
+#define PCLK_GMAC               323
+#define PCLK_MIPI_DSI           324
+#define PCLK_MIPIDSIPHY         325
+#define PCLK_MIPICSIPHY         326
+#define PCLK_USB_GRF            327
+#define PCLK_DCF                328
+#define PCLK_UART1              329
+#define PCLK_UART2              330
+#define PCLK_UART3              331
+#define PCLK_UART4              332
+#define PCLK_UART5              333
+#define PCLK_I2C0               334
+#define PCLK_I2C1               335
+#define PCLK_I2C2               336
+#define PCLK_I2C3               337
+#define PCLK_I2C4               338
+#define PCLK_PWM0               339
+#define PCLK_PWM1               340
+#define PCLK_SPI0               341
+#define PCLK_SPI1               342
+#define PCLK_SARADC             343
+#define PCLK_TSADC              344
+#define PCLK_TIMER              345
+#define PCLK_OTP_NS             346
+#define PCLK_WDT_NS             347
+#define PCLK_GPIO1              348
+#define PCLK_GPIO2              349
+#define PCLK_GPIO3              350
+#define PCLK_ISP                351
+#define PCLK_CIF                352
+#define PCLK_OTP_PHY            353
+
+#define CLK_NR_CLKS             (PCLK_OTP_PHY + 1)
+
+/* pmu-clocks indices */
+
+#define PLL_GPLL                1
+
+#define SCLK_RTC32K_PMU         4
+#define SCLK_WIFI_PMU           5
+#define SCLK_UART0_PMU          6
+#define SCLK_PVTM_PMU           7
+#define PCLK_PMU_PRE            8
+#define SCLK_REF24M_PMU         9
+#define SCLK_USBPHY_REF         10
+#define SCLK_MIPIDSIPHY_REF     11
+
+#define XIN24M_DIV              12
+
+#define PCLK_GPIO0_PMU          20
+#define PCLK_UART0_PMU          21
+
+#define CLKPMU_NR_CLKS          (PCLK_UART0_PMU + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0_PO           0
+#define SRST_CORE1_PO           1
+#define SRST_CORE2_PO           2
+#define SRST_CORE3_PO           3
+#define SRST_CORE0              4
+#define SRST_CORE1              5
+#define SRST_CORE2              6
+#define SRST_CORE3              7
+#define SRST_CORE0_DBG          8
+#define SRST_CORE1_DBG          9
+#define SRST_CORE2_DBG          10
+#define SRST_CORE3_DBG          11
+#define SRST_TOPDBG             12