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-rw-r--r--arch/arm/kvm/hyp/Makefile1
-rw-r--r--arch/arm64/kvm/hyp/Makefile1
-rw-r--r--virt/kvm/arm/aarch32.c121
-rw-r--r--virt/kvm/arm/hyp/aarch32.c136
4 files changed, 138 insertions, 121 deletions
diff --git a/arch/arm/kvm/hyp/Makefile b/arch/arm/kvm/hyp/Makefile
index d2b5ec9c4b92..ba88b1eca93c 100644
--- a/arch/arm/kvm/hyp/Makefile
+++ b/arch/arm/kvm/hyp/Makefile
@@ -11,6 +11,7 @@ CFLAGS_ARMV7VE :=$(call cc-option, -march=armv7ve)
11 11
12obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v3-sr.o 12obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v3-sr.o
13obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/timer-sr.o 13obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/timer-sr.o
14obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/aarch32.o
14 15
15obj-$(CONFIG_KVM_ARM_HOST) += tlb.o 16obj-$(CONFIG_KVM_ARM_HOST) += tlb.o
16obj-$(CONFIG_KVM_ARM_HOST) += cp15-sr.o 17obj-$(CONFIG_KVM_ARM_HOST) += cp15-sr.o
diff --git a/arch/arm64/kvm/hyp/Makefile b/arch/arm64/kvm/hyp/Makefile
index 82d1904328ad..ea710f674cb6 100644
--- a/arch/arm64/kvm/hyp/Makefile
+++ b/arch/arm64/kvm/hyp/Makefile
@@ -10,6 +10,7 @@ KVM=../../../../virt/kvm
10 10
11obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v3-sr.o 11obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v3-sr.o
12obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/timer-sr.o 12obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/timer-sr.o
13obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/aarch32.o
13 14
14obj-$(CONFIG_KVM_ARM_HOST) += vgic-v2-cpuif-proxy.o 15obj-$(CONFIG_KVM_ARM_HOST) += vgic-v2-cpuif-proxy.o
15obj-$(CONFIG_KVM_ARM_HOST) += sysreg-sr.o 16obj-$(CONFIG_KVM_ARM_HOST) += sysreg-sr.o
diff --git a/virt/kvm/arm/aarch32.c b/virt/kvm/arm/aarch32.c
index 5abbe9b3c652..6880236974b8 100644
--- a/virt/kvm/arm/aarch32.c
+++ b/virt/kvm/arm/aarch32.c
@@ -26,127 +26,6 @@
26#include <asm/kvm_hyp.h> 26#include <asm/kvm_hyp.h>
27 27
28/* 28/*
29 * stolen from arch/arm/kernel/opcodes.c
30 *
31 * condition code lookup table
32 * index into the table is test code: EQ, NE, ... LT, GT, AL, NV
33 *
34 * bit position in short is condition code: NZCV
35 */
36static const unsigned short cc_map[16] = {
37 0xF0F0, /* EQ == Z set */
38 0x0F0F, /* NE */
39 0xCCCC, /* CS == C set */
40 0x3333, /* CC */
41 0xFF00, /* MI == N set */
42 0x00FF, /* PL */
43 0xAAAA, /* VS == V set */
44 0x5555, /* VC */
45 0x0C0C, /* HI == C set && Z clear */
46 0xF3F3, /* LS == C clear || Z set */
47 0xAA55, /* GE == (N==V) */
48 0x55AA, /* LT == (N!=V) */
49 0x0A05, /* GT == (!Z && (N==V)) */
50 0xF5FA, /* LE == (Z || (N!=V)) */
51 0xFFFF, /* AL always */
52 0 /* NV */
53};
54
55/*
56 * Check if a trapped instruction should have been executed or not.
57 */
58bool __hyp_text kvm_condition_valid32(const struct kvm_vcpu *vcpu)
59{
60 unsigned long cpsr;
61 u32 cpsr_cond;
62 int cond;
63
64 /* Top two bits non-zero? Unconditional. */
65 if (kvm_vcpu_get_hsr(vcpu) >> 30)
66 return true;
67
68 /* Is condition field valid? */
69 cond = kvm_vcpu_get_condition(vcpu);
70 if (cond == 0xE)
71 return true;
72
73 cpsr = *vcpu_cpsr(vcpu);
74
75 if (cond < 0) {
76 /* This can happen in Thumb mode: examine IT state. */
77 unsigned long it;
78
79 it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3);
80
81 /* it == 0 => unconditional. */
82 if (it == 0)
83 return true;
84
85 /* The cond for this insn works out as the top 4 bits. */
86 cond = (it >> 4);
87 }
88
89 cpsr_cond = cpsr >> 28;
90
91 if (!((cc_map[cond] >> cpsr_cond) & 1))
92 return false;
93
94 return true;
95}
96
97/**
98 * adjust_itstate - adjust ITSTATE when emulating instructions in IT-block
99 * @vcpu: The VCPU pointer
100 *
101 * When exceptions occur while instructions are executed in Thumb IF-THEN
102 * blocks, the ITSTATE field of the CPSR is not advanced (updated), so we have
103 * to do this little bit of work manually. The fields map like this:
104 *
105 * IT[7:0] -> CPSR[26:25],CPSR[15:10]
106 */
107static void __hyp_text kvm_adjust_itstate(struct kvm_vcpu *vcpu)
108{
109 unsigned long itbits, cond;
110 unsigned long cpsr = *vcpu_cpsr(vcpu);
111 bool is_arm = !(cpsr & PSR_AA32_T_BIT);
112
113 if (is_arm || !(cpsr & PSR_AA32_IT_MASK))
114 return;
115
116 cond = (cpsr & 0xe000) >> 13;
117 itbits = (cpsr & 0x1c00) >> (10 - 2);
118 itbits |= (cpsr & (0x3 << 25)) >> 25;
119
120 /* Perform ITAdvance (see page A2-52 in ARM DDI 0406C) */
121 if ((itbits & 0x7) == 0)
122 itbits = cond = 0;
123 else
124 itbits = (itbits << 1) & 0x1f;
125
126 cpsr &= ~PSR_AA32_IT_MASK;
127 cpsr |= cond << 13;
128 cpsr |= (itbits & 0x1c) << (10 - 2);
129 cpsr |= (itbits & 0x3) << 25;
130 *vcpu_cpsr(vcpu) = cpsr;
131}
132
133/**
134 * kvm_skip_instr - skip a trapped instruction and proceed to the next
135 * @vcpu: The vcpu pointer
136 */
137void __hyp_text kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr)
138{
139 bool is_thumb;
140
141 is_thumb = !!(*vcpu_cpsr(vcpu) & PSR_AA32_T_BIT);
142 if (is_thumb && !is_wide_instr)
143 *vcpu_pc(vcpu) += 2;
144 else
145 *vcpu_pc(vcpu) += 4;
146 kvm_adjust_itstate(vcpu);
147}
148
149/*
150 * Table taken from ARMv8 ARM DDI0487B-B, table G1-10. 29 * Table taken from ARMv8 ARM DDI0487B-B, table G1-10.
151 */ 30 */
152static const u8 return_offsets[8][2] = { 31static const u8 return_offsets[8][2] = {
diff --git a/virt/kvm/arm/hyp/aarch32.c b/virt/kvm/arm/hyp/aarch32.c
new file mode 100644
index 000000000000..d31f267961e7
--- /dev/null
+++ b/virt/kvm/arm/hyp/aarch32.c
@@ -0,0 +1,136 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Hyp portion of the (not much of an) Emulation layer for 32bit guests.
4 *
5 * Copyright (C) 2012,2013 - ARM Ltd
6 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 *
8 * based on arch/arm/kvm/emulate.c
9 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
10 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
11 */
12
13#include <linux/kvm_host.h>
14#include <asm/kvm_emulate.h>
15#include <asm/kvm_hyp.h>
16
17/*
18 * stolen from arch/arm/kernel/opcodes.c
19 *
20 * condition code lookup table
21 * index into the table is test code: EQ, NE, ... LT, GT, AL, NV
22 *
23 * bit position in short is condition code: NZCV
24 */
25static const unsigned short cc_map[16] = {
26 0xF0F0, /* EQ == Z set */
27 0x0F0F, /* NE */
28 0xCCCC, /* CS == C set */
29 0x3333, /* CC */
30 0xFF00, /* MI == N set */
31 0x00FF, /* PL */
32 0xAAAA, /* VS == V set */
33 0x5555, /* VC */
34 0x0C0C, /* HI == C set && Z clear */
35 0xF3F3, /* LS == C clear || Z set */
36 0xAA55, /* GE == (N==V) */
37 0x55AA, /* LT == (N!=V) */
38 0x0A05, /* GT == (!Z && (N==V)) */
39 0xF5FA, /* LE == (Z || (N!=V)) */
40 0xFFFF, /* AL always */
41 0 /* NV */
42};
43
44/*
45 * Check if a trapped instruction should have been executed or not.
46 */
47bool __hyp_text kvm_condition_valid32(const struct kvm_vcpu *vcpu)
48{
49 unsigned long cpsr;
50 u32 cpsr_cond;
51 int cond;
52
53 /* Top two bits non-zero? Unconditional. */
54 if (kvm_vcpu_get_hsr(vcpu) >> 30)
55 return true;
56
57 /* Is condition field valid? */
58 cond = kvm_vcpu_get_condition(vcpu);
59 if (cond == 0xE)
60 return true;
61
62 cpsr = *vcpu_cpsr(vcpu);
63
64 if (cond < 0) {
65 /* This can happen in Thumb mode: examine IT state. */
66 unsigned long it;
67
68 it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3);
69
70 /* it == 0 => unconditional. */
71 if (it == 0)
72 return true;
73
74 /* The cond for this insn works out as the top 4 bits. */
75 cond = (it >> 4);
76 }
77
78 cpsr_cond = cpsr >> 28;
79
80 if (!((cc_map[cond] >> cpsr_cond) & 1))
81 return false;
82
83 return true;
84}
85
86/**
87 * adjust_itstate - adjust ITSTATE when emulating instructions in IT-block
88 * @vcpu: The VCPU pointer
89 *
90 * When exceptions occur while instructions are executed in Thumb IF-THEN
91 * blocks, the ITSTATE field of the CPSR is not advanced (updated), so we have
92 * to do this little bit of work manually. The fields map like this:
93 *
94 * IT[7:0] -> CPSR[26:25],CPSR[15:10]
95 */
96static void __hyp_text kvm_adjust_itstate(struct kvm_vcpu *vcpu)
97{
98 unsigned long itbits, cond;
99 unsigned long cpsr = *vcpu_cpsr(vcpu);
100 bool is_arm = !(cpsr & PSR_AA32_T_BIT);
101
102 if (is_arm || !(cpsr & PSR_AA32_IT_MASK))
103 return;
104
105 cond = (cpsr & 0xe000) >> 13;
106 itbits = (cpsr & 0x1c00) >> (10 - 2);
107 itbits |= (cpsr & (0x3 << 25)) >> 25;
108
109 /* Perform ITAdvance (see page A2-52 in ARM DDI 0406C) */
110 if ((itbits & 0x7) == 0)
111 itbits = cond = 0;
112 else
113 itbits = (itbits << 1) & 0x1f;
114
115 cpsr &= ~PSR_AA32_IT_MASK;
116 cpsr |= cond << 13;
117 cpsr |= (itbits & 0x1c) << (10 - 2);
118 cpsr |= (itbits & 0x3) << 25;
119 *vcpu_cpsr(vcpu) = cpsr;
120}
121
122/**
123 * kvm_skip_instr - skip a trapped instruction and proceed to the next
124 * @vcpu: The vcpu pointer
125 */
126void __hyp_text kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr)
127{
128 bool is_thumb;
129
130 is_thumb = !!(*vcpu_cpsr(vcpu) & PSR_AA32_T_BIT);
131 if (is_thumb && !is_wide_instr)
132 *vcpu_pc(vcpu) += 2;
133 else
134 *vcpu_pc(vcpu) += 4;
135 kvm_adjust_itstate(vcpu);
136}
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-27 12:45:20 -0500