1 files changed, 5 insertions, 3 deletions

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 404df26b7de8..5c0ea39311fe 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -155,7 +155,8 @@ x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
                 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
 
                 /* SSBD controlled in MSR_SPEC_CTRL */
-                if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
+                if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
+                    static_cpu_has(X86_FEATURE_AMD_SSBD))
                         hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
 
                 if (hostval != guestval) {
@@ -533,9 +534,10 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
                  * use a completely different MSR and bit dependent on family.
                  */
-                if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
+                if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
+                    !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
                         x86_amd_ssb_disable();
-                else {
+                } else {
                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
                         x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);