aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/mach-prima2/Makefile1
-rw-r--r--arch/arm/mach-prima2/common.c10
-rw-r--r--arch/arm/mach-prima2/irq.c129
-rw-r--r--drivers/irqchip/Makefile1
-rw-r--r--drivers/irqchip/irq-sirfsoc.c126
5 files changed, 129 insertions, 138 deletions
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index bfe360cbd177..5fdff7e32290 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -4,7 +4,6 @@ obj-y += rtciobrg.o
4obj-$(CONFIG_DEBUG_LL) += lluart.o 4obj-$(CONFIG_DEBUG_LL) += lluart.o
5obj-$(CONFIG_CACHE_L2X0) += l2x0.o 5obj-$(CONFIG_CACHE_L2X0) += l2x0.o
6obj-$(CONFIG_SUSPEND) += pm.o sleep.o 6obj-$(CONFIG_SUSPEND) += pm.o sleep.o
7obj-$(CONFIG_SIRF_IRQ) += irq.o
8obj-$(CONFIG_SMP) += platsmp.o headsmp.o 7obj-$(CONFIG_SMP) += platsmp.o headsmp.o
9obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 8obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
10obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o 9obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 72efb4ff2803..15c14dfb47a0 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -46,11 +46,8 @@ static const char *atlas6_dt_match[] __initdata = {
46DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") 46DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
47 /* Maintainer: Barry Song <baohua.song@csr.com> */ 47 /* Maintainer: Barry Song <baohua.song@csr.com> */
48 .map_io = sirfsoc_map_io, 48 .map_io = sirfsoc_map_io,
49 .init_irq = sirfsoc_of_irq_init, 49 .init_irq = irqchip_init,
50 .init_time = sirfsoc_prima2_timer_init, 50 .init_time = sirfsoc_prima2_timer_init,
51#ifdef CONFIG_MULTI_IRQ_HANDLER
52 .handle_irq = sirfsoc_handle_irq,
53#endif
54 .init_machine = sirfsoc_mach_init, 51 .init_machine = sirfsoc_mach_init,
55 .init_late = sirfsoc_init_late, 52 .init_late = sirfsoc_init_late,
56 .dt_compat = atlas6_dt_match, 53 .dt_compat = atlas6_dt_match,
@@ -67,11 +64,8 @@ static const char *prima2_dt_match[] __initdata = {
67DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") 64DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
68 /* Maintainer: Barry Song <baohua.song@csr.com> */ 65 /* Maintainer: Barry Song <baohua.song@csr.com> */
69 .map_io = sirfsoc_map_io, 66 .map_io = sirfsoc_map_io,
70 .init_irq = sirfsoc_of_irq_init, 67 .init_irq = irqchip_init,
71 .init_time = sirfsoc_prima2_timer_init, 68 .init_time = sirfsoc_prima2_timer_init,
72#ifdef CONFIG_MULTI_IRQ_HANDLER
73 .handle_irq = sirfsoc_handle_irq,
74#endif
75 .dma_zone_size = SZ_256M, 69 .dma_zone_size = SZ_256M,
76 .init_machine = sirfsoc_mach_init, 70 .init_machine = sirfsoc_mach_init,
77 .init_late = sirfsoc_init_late, 71 .init_late = sirfsoc_init_late,
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
deleted file mode 100644
index 6c0f3e9c43fb..000000000000
--- a/arch/arm/mach-prima2/irq.c
+++ /dev/null
@@ -1,129 +0,0 @@
1/*
2 * interrupt controller support for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12#include <linux/of.h>
13#include <linux/of_address.h>
14#include <linux/irqdomain.h>
15#include <linux/syscore_ops.h>
16#include <asm/mach/irq.h>
17#include <asm/exception.h>
18#include <mach/hardware.h>
19
20#define SIRFSOC_INT_RISC_MASK0 0x0018
21#define SIRFSOC_INT_RISC_MASK1 0x001C
22#define SIRFSOC_INT_RISC_LEVEL0 0x0020
23#define SIRFSOC_INT_RISC_LEVEL1 0x0024
24#define SIRFSOC_INIT_IRQ_ID 0x0038
25
26void __iomem *sirfsoc_intc_base;
27
28static __init void
29sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
30{
31 struct irq_chip_generic *gc;
32 struct irq_chip_type *ct;
33
34 gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
35 ct = gc->chip_types;
36
37 ct->chip.irq_mask = irq_gc_mask_clr_bit;
38 ct->chip.irq_unmask = irq_gc_mask_set_bit;
39 ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
40
41 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
42}
43
44static __init void sirfsoc_irq_init(void)
45{
46 sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
47 sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32,
48 SIRFSOC_INTENAL_IRQ_END + 1 - 32);
49
50 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
51 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
52
53 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
54 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
55}
56
57asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
58{
59 u32 irqstat, irqnr;
60
61 irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID);
62 irqnr = irqstat & 0xff;
63
64 handle_IRQ(irqnr, regs);
65}
66
67static struct of_device_id intc_ids[] = {
68 { .compatible = "sirf,prima2-intc" },
69 {},
70};
71
72void __init sirfsoc_of_irq_init(void)
73{
74 struct device_node *np;
75
76 np = of_find_matching_node(NULL, intc_ids);
77 if (!np)
78 return;
79
80 sirfsoc_intc_base = of_iomap(np, 0);
81 if (!sirfsoc_intc_base)
82 panic("unable to map intc cpu registers\n");
83
84 irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0,
85 &irq_domain_simple_ops, NULL);
86
87 of_node_put(np);
88
89 sirfsoc_irq_init();
90}
91
92struct sirfsoc_irq_status {
93 u32 mask0;
94 u32 mask1;
95 u32 level0;
96 u32 level1;
97};
98
99static struct sirfsoc_irq_status sirfsoc_irq_st;
100
101static int sirfsoc_irq_suspend(void)
102{
103 sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
104 sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
105 sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
106 sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
107
108 return 0;
109}
110
111static void sirfsoc_irq_resume(void)
112{
113 writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
114 writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
115 writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
116 writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
117}
118
119static struct syscore_ops sirfsoc_irq_syscore_ops = {
120 .suspend = sirfsoc_irq_suspend,
121 .resume = sirfsoc_irq_resume,
122};
123
124static int __init sirfsoc_irq_pm_init(void)
125{
126 register_syscore_ops(&sirfsoc_irq_syscore_ops);
127 return 0;
128}
129device_initcall(sirfsoc_irq_pm_init);
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 98e3b87bdf1b..5cb6bd24d8bf 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o
8obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o 8obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
9obj-$(CONFIG_ARM_GIC) += irq-gic.o 9obj-$(CONFIG_ARM_GIC) += irq-gic.o
10obj-$(CONFIG_ARM_VIC) += irq-vic.o 10obj-$(CONFIG_ARM_VIC) += irq-vic.o
11obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o
11obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o 12obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
diff --git a/drivers/irqchip/irq-sirfsoc.c b/drivers/irqchip/irq-sirfsoc.c
new file mode 100644
index 000000000000..69ea44ebcf61
--- /dev/null
+++ b/drivers/irqchip/irq-sirfsoc.c
@@ -0,0 +1,126 @@
1/*
2 * interrupt controller support for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12#include <linux/of.h>
13#include <linux/of_address.h>
14#include <linux/irqdomain.h>
15#include <linux/syscore_ops.h>
16#include <asm/mach/irq.h>
17#include <asm/exception.h>
18#include "irqchip.h"
19
20#define SIRFSOC_INT_RISC_MASK0 0x0018
21#define SIRFSOC_INT_RISC_MASK1 0x001C
22#define SIRFSOC_INT_RISC_LEVEL0 0x0020
23#define SIRFSOC_INT_RISC_LEVEL1 0x0024
24#define SIRFSOC_INIT_IRQ_ID 0x0038
25
26#define SIRFSOC_NUM_IRQS 128
27
28static struct irq_domain *sirfsoc_irqdomain;
29
30static __init void
31sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
32{
33 struct irq_chip_generic *gc;
34 struct irq_chip_type *ct;
35
36 gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
37 ct = gc->chip_types;
38
39 ct->chip.irq_mask = irq_gc_mask_clr_bit;
40 ct->chip.irq_unmask = irq_gc_mask_set_bit;
41 ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
42
43 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
44}
45
46static asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
47{
48 void __iomem *base = sirfsoc_irqdomain->host_data;
49 u32 irqstat, irqnr;
50
51 irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
52 irqnr = irq_find_mapping(sirfsoc_irqdomain, irqstat & 0xff);
53
54 handle_IRQ(irqnr, regs);
55}
56
57static int __init sirfsoc_irq_init(struct device_node *np, struct device_node *parent)
58{
59 void __iomem *base = of_iomap(np, 0);
60 if (!base)
61 panic("unable to map intc cpu registers\n");
62
63 /* using legacy because irqchip_generic does not work with linear */
64 sirfsoc_irqdomain = irq_domain_add_legacy(np, SIRFSOC_NUM_IRQS, 0, 0,
65 &irq_domain_simple_ops, base);
66
67 sirfsoc_alloc_gc(base, 0, 32);
68 sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32);
69
70 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
71 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);
72
73 writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
74 writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);
75
76 set_handle_irq(sirfsoc_handle_irq);
77
78 return 0;
79}
80IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);
81
82struct sirfsoc_irq_status {
83 u32 mask0;
84 u32 mask1;
85 u32 level0;
86 u32 level1;
87};
88
89static struct sirfsoc_irq_status sirfsoc_irq_st;
90
91static int sirfsoc_irq_suspend(void)
92{
93 void __iomem *base = sirfsoc_irqdomain->host_data;
94
95 sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
96 sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
97 sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
98 sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);
99
100 return 0;
101}
102
103static void sirfsoc_irq_resume(void)
104{
105 void __iomem *base = sirfsoc_irqdomain->host_data;
106
107 writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
108 writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
109 writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
110 writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
111}
112
113static struct syscore_ops sirfsoc_irq_syscore_ops = {
114 .suspend = sirfsoc_irq_suspend,
115 .resume = sirfsoc_irq_resume,
116};
117
118static int __init sirfsoc_irq_pm_init(void)
119{
120 if (!sirfsoc_irqdomain)
121 return 0;
122
123 register_syscore_ops(&sirfsoc_irq_syscore_ops);
124 return 0;
125}
126device_initcall(sirfsoc_irq_pm_init);
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-26 16:03:53 -0400