aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--arch/arm/mach-omap2/Kconfig21
-rw-r--r--arch/arm/mach-omap2/common.c1
-rw-r--r--arch/arm/mach-omap2/common.h3
-rw-r--r--arch/arm/mach-omap2/io.c2
-rw-r--r--arch/arm/mach-omap2/omap-secure.h7
-rw-r--r--arch/arm/mach-omap2/omap4-common.c69
-rw-r--r--arch/arm/mach-omap2/sleep44xx.S2
7 files changed, 0 insertions, 105 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 2b8e47788062..c7f4d9a6b38c 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -278,27 +278,6 @@ config OMAP3_SDRC_AC_TIMING
278 wish to say no. Selecting yes without understanding what is 278 wish to say no. Selecting yes without understanding what is
279 going on could result in system crashes; 279 going on could result in system crashes;
280 280
281config OMAP4_ERRATA_I688
282 bool "OMAP4 errata: Async Bridge Corruption"
283 depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM
284 select ARCH_HAS_BARRIERS
285 help
286 If a data is stalled inside asynchronous bridge because of back
287 pressure, it may be accepted multiple times, creating pointer
288 misalignment that will corrupt next transfers on that data path
289 until next reset of the system (No recovery procedure once the
290 issue is hit, the path remains consistently broken). Async bridge
291 can be found on path between MPU to EMIF and MPU to L3 interconnect.
292 This situation can happen only when the idle is initiated by a
293 Master Request Disconnection (which is trigged by software when
294 executing WFI on CPU).
295 The work-around for this errata needs all the initiators connected
296 through async bridge must ensure that data path is properly drained
297 before issuing WFI. This condition will be met if one Strongly ordered
298 access is performed to the target right before executing the WFI.
299 In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
300 IO barrier ensure that there is no synchronisation loss on initiators
301 operating on both interconnect port simultaneously.
302endmenu 281endmenu
303 282
304endif 283endif
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 484cdadfb187..eae6a0e87c90 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -30,5 +30,4 @@ int __weak omap_secure_ram_reserve_memblock(void)
30void __init omap_reserve(void) 30void __init omap_reserve(void)
31{ 31{
32 omap_secure_ram_reserve_memblock(); 32 omap_secure_ram_reserve_memblock();
33 omap_barrier_reserve_memblock();
34} 33}
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 46e24581d624..cf3cf22ecd42 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -200,9 +200,6 @@ void __init omap4_map_io(void);
200void __init omap5_map_io(void); 200void __init omap5_map_io(void);
201void __init ti81xx_map_io(void); 201void __init ti81xx_map_io(void);
202 202
203/* omap_barriers_init() is OMAP4 only */
204void omap_barriers_init(void);
205
206/** 203/**
207 * omap_test_timeout - busy-loop, testing a condition 204 * omap_test_timeout - busy-loop, testing a condition
208 * @cond: condition to test until it evaluates to true 205 * @cond: condition to test until it evaluates to true
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index c4871c55bd8b..1eeff6be260d 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -306,7 +306,6 @@ void __init am33xx_map_io(void)
306void __init omap4_map_io(void) 306void __init omap4_map_io(void)
307{ 307{
308 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); 308 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
309 omap_barriers_init();
310} 309}
311#endif 310#endif
312 311
@@ -314,7 +313,6 @@ void __init omap4_map_io(void)
314void __init omap5_map_io(void) 313void __init omap5_map_io(void)
315{ 314{
316 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); 315 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
317 omap_barriers_init();
318} 316}
319#endif 317#endif
320/* 318/*
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index dec2b05d184b..af2851fbcdf0 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -70,13 +70,6 @@ extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
70extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits); 70extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
71extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag); 71extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);
72 72
73#ifdef CONFIG_OMAP4_ERRATA_I688
74extern int omap_barrier_reserve_memblock(void);
75#else
76static inline void omap_barrier_reserve_memblock(void)
77{ }
78#endif
79
80#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 73#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
81void set_cntfreq(void); 74void set_cntfreq(void);
82#else 75#else
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index cee0fe1ee6ff..afaac9e25764 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -52,75 +52,6 @@ static void __iomem *twd_base;
52 52
53#define IRQ_LOCALTIMER 29 53#define IRQ_LOCALTIMER 29
54 54
55#ifdef CONFIG_OMAP4_ERRATA_I688
56/* Used to implement memory barrier on DRAM path */
57#define OMAP4_DRAM_BARRIER_VA 0xfe600000
58
59void __iomem *dram_sync, *sram_sync;
60
61static phys_addr_t paddr;
62static u32 size;
63
64void omap_bus_sync(void)
65{
66 if (dram_sync && sram_sync) {
67 writel_relaxed(readl_relaxed(dram_sync), dram_sync);
68 writel_relaxed(readl_relaxed(sram_sync), sram_sync);
69 isb();
70 }
71}
72EXPORT_SYMBOL(omap_bus_sync);
73
74static int __init omap4_sram_init(void)
75{
76 struct device_node *np;
77 struct gen_pool *sram_pool;
78
79 np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
80 if (!np)
81 pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
82 __func__);
83 sram_pool = of_get_named_gen_pool(np, "sram", 0);
84 if (!sram_pool)
85 pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
86 __func__);
87 else
88 sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
89
90 return 0;
91}
92omap_arch_initcall(omap4_sram_init);
93
94/* Steal one page physical memory for barrier implementation */
95int __init omap_barrier_reserve_memblock(void)
96{
97
98 size = ALIGN(PAGE_SIZE, SZ_1M);
99 paddr = arm_memblock_steal(size, SZ_1M);
100
101 return 0;
102}
103
104void __init omap_barriers_init(void)
105{
106 struct map_desc dram_io_desc[1];
107
108 dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
109 dram_io_desc[0].pfn = __phys_to_pfn(paddr);
110 dram_io_desc[0].length = size;
111 dram_io_desc[0].type = MT_MEMORY_RW_SO;
112 iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
113 dram_sync = (void __iomem *) dram_io_desc[0].virtual;
114
115 pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
116 (long long) paddr, dram_io_desc[0].virtual);
117
118}
119#else
120void __init omap_barriers_init(void)
121{}
122#endif
123
124void gic_dist_disable(void) 55void gic_dist_disable(void)
125{ 56{
126 if (gic_dist_base_addr) 57 if (gic_dist_base_addr)
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index b84a0122d823..ad1bb9431e94 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -333,11 +333,9 @@ ENDPROC(omap4_cpu_resume)
333 333
334#endif /* defined(CONFIG_SMP) && defined(CONFIG_PM) */ 334#endif /* defined(CONFIG_SMP) && defined(CONFIG_PM) */
335 335
336#ifndef CONFIG_OMAP4_ERRATA_I688
337ENTRY(omap_bus_sync) 336ENTRY(omap_bus_sync)
338 ret lr 337 ret lr
339ENDPROC(omap_bus_sync) 338ENDPROC(omap_bus_sync)
340#endif
341 339
342ENTRY(omap_do_wfi) 340ENTRY(omap_do_wfi)
343 stmfd sp!, {lr} 341 stmfd sp!, {lr}