diff options
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 21 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 12 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/si_dpm.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/pp_power_source.h | 36 |
10 files changed, 27 insertions, 64 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h index dd6203a0a6b7..9acfbee91c40 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | |||
@@ -402,7 +402,6 @@ struct amdgpu_dpm { | |||
402 | u32 tdp_adjustment; | 402 | u32 tdp_adjustment; |
403 | u16 load_line_slope; | 403 | u16 load_line_slope; |
404 | bool power_control; | 404 | bool power_control; |
405 | bool ac_power; | ||
406 | /* special states active */ | 405 | /* special states active */ |
407 | bool thermal_active; | 406 | bool thermal_active; |
408 | bool uvd_active; | 407 | bool uvd_active; |
@@ -439,6 +438,7 @@ struct amdgpu_pm { | |||
439 | struct amd_pp_display_configuration pm_display_cfg;/* set by dc */ | 438 | struct amd_pp_display_configuration pm_display_cfg;/* set by dc */ |
440 | uint32_t smu_prv_buffer_size; | 439 | uint32_t smu_prv_buffer_size; |
441 | struct amdgpu_bo *smu_prv_buffer; | 440 | struct amdgpu_bo *smu_prv_buffer; |
441 | bool ac_power; | ||
442 | }; | 442 | }; |
443 | 443 | ||
444 | #define R600_SSTU_DFLT 0 | 444 | #define R600_SSTU_DFLT 0 |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index f667cb9eb614..113edffb5960 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | |||
@@ -68,11 +68,11 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) | |||
68 | if (adev->pm.dpm_enabled) { | 68 | if (adev->pm.dpm_enabled) { |
69 | mutex_lock(&adev->pm.mutex); | 69 | mutex_lock(&adev->pm.mutex); |
70 | if (power_supply_is_system_supplied() > 0) | 70 | if (power_supply_is_system_supplied() > 0) |
71 | adev->pm.dpm.ac_power = true; | 71 | adev->pm.ac_power = true; |
72 | else | 72 | else |
73 | adev->pm.dpm.ac_power = false; | 73 | adev->pm.ac_power = false; |
74 | if (adev->powerplay.pp_funcs->enable_bapm) | 74 | if (adev->powerplay.pp_funcs->enable_bapm) |
75 | amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power); | 75 | amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); |
76 | mutex_unlock(&adev->pm.mutex); | 76 | mutex_unlock(&adev->pm.mutex); |
77 | } | 77 | } |
78 | } | 78 | } |
@@ -1907,6 +1907,14 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) | |||
1907 | amdgpu_fence_wait_empty(ring); | 1907 | amdgpu_fence_wait_empty(ring); |
1908 | } | 1908 | } |
1909 | 1909 | ||
1910 | mutex_lock(&adev->pm.mutex); | ||
1911 | /* update battery/ac status */ | ||
1912 | if (power_supply_is_system_supplied() > 0) | ||
1913 | adev->pm.ac_power = true; | ||
1914 | else | ||
1915 | adev->pm.ac_power = false; | ||
1916 | mutex_unlock(&adev->pm.mutex); | ||
1917 | |||
1910 | if (adev->powerplay.pp_funcs->dispatch_tasks) { | 1918 | if (adev->powerplay.pp_funcs->dispatch_tasks) { |
1911 | if (!amdgpu_device_has_dc_support(adev)) { | 1919 | if (!amdgpu_device_has_dc_support(adev)) { |
1912 | mutex_lock(&adev->pm.mutex); | 1920 | mutex_lock(&adev->pm.mutex); |
@@ -1927,14 +1935,7 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) | |||
1927 | } else { | 1935 | } else { |
1928 | mutex_lock(&adev->pm.mutex); | 1936 | mutex_lock(&adev->pm.mutex); |
1929 | amdgpu_dpm_get_active_displays(adev); | 1937 | amdgpu_dpm_get_active_displays(adev); |
1930 | /* update battery/ac status */ | ||
1931 | if (power_supply_is_system_supplied() > 0) | ||
1932 | adev->pm.dpm.ac_power = true; | ||
1933 | else | ||
1934 | adev->pm.dpm.ac_power = false; | ||
1935 | |||
1936 | amdgpu_dpm_change_power_state_locked(adev); | 1938 | amdgpu_dpm_change_power_state_locked(adev); |
1937 | |||
1938 | mutex_unlock(&adev->pm.mutex); | 1939 | mutex_unlock(&adev->pm.mutex); |
1939 | } | 1940 | } |
1940 | } | 1941 | } |
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index a266dcf5daed..b6248c0578a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c | |||
@@ -951,12 +951,12 @@ static void ci_apply_state_adjust_rules(struct amdgpu_device *adev, | |||
951 | else | 951 | else |
952 | pi->battery_state = false; | 952 | pi->battery_state = false; |
953 | 953 | ||
954 | if (adev->pm.dpm.ac_power) | 954 | if (adev->pm.ac_power) |
955 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; | 955 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; |
956 | else | 956 | else |
957 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; | 957 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; |
958 | 958 | ||
959 | if (adev->pm.dpm.ac_power == false) { | 959 | if (adev->pm.ac_power == false) { |
960 | for (i = 0; i < ps->performance_level_count; i++) { | 960 | for (i = 0; i < ps->performance_level_count; i++) { |
961 | if (ps->performance_levels[i].mclk > max_limits->mclk) | 961 | if (ps->performance_levels[i].mclk > max_limits->mclk) |
962 | ps->performance_levels[i].mclk = max_limits->mclk; | 962 | ps->performance_levels[i].mclk = max_limits->mclk; |
@@ -4078,7 +4078,7 @@ static int ci_enable_uvd_dpm(struct amdgpu_device *adev, bool enable) | |||
4078 | const struct amdgpu_clock_and_voltage_limits *max_limits; | 4078 | const struct amdgpu_clock_and_voltage_limits *max_limits; |
4079 | int i; | 4079 | int i; |
4080 | 4080 | ||
4081 | if (adev->pm.dpm.ac_power) | 4081 | if (adev->pm.ac_power) |
4082 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; | 4082 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; |
4083 | else | 4083 | else |
4084 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; | 4084 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; |
@@ -4127,7 +4127,7 @@ static int ci_enable_vce_dpm(struct amdgpu_device *adev, bool enable) | |||
4127 | const struct amdgpu_clock_and_voltage_limits *max_limits; | 4127 | const struct amdgpu_clock_and_voltage_limits *max_limits; |
4128 | int i; | 4128 | int i; |
4129 | 4129 | ||
4130 | if (adev->pm.dpm.ac_power) | 4130 | if (adev->pm.ac_power) |
4131 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; | 4131 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; |
4132 | else | 4132 | else |
4133 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; | 4133 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; |
@@ -4160,7 +4160,7 @@ static int ci_enable_samu_dpm(struct amdgpu_device *adev, bool enable) | |||
4160 | const struct amdgpu_clock_and_voltage_limits *max_limits; | 4160 | const struct amdgpu_clock_and_voltage_limits *max_limits; |
4161 | int i; | 4161 | int i; |
4162 | 4162 | ||
4163 | if (adev->pm.dpm.ac_power) | 4163 | if (adev->pm.ac_power) |
4164 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; | 4164 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; |
4165 | else | 4165 | else |
4166 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; | 4166 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; |
@@ -4191,7 +4191,7 @@ static int ci_enable_acp_dpm(struct amdgpu_device *adev, bool enable) | |||
4191 | const struct amdgpu_clock_and_voltage_limits *max_limits; | 4191 | const struct amdgpu_clock_and_voltage_limits *max_limits; |
4192 | int i; | 4192 | int i; |
4193 | 4193 | ||
4194 | if (adev->pm.dpm.ac_power) | 4194 | if (adev->pm.ac_power) |
4195 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; | 4195 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; |
4196 | else | 4196 | else |
4197 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; | 4197 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; |
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c index 17f7f074cedc..d79e6f5234da 100644 --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c | |||
@@ -1921,7 +1921,7 @@ static int kv_dpm_set_power_state(void *handle) | |||
1921 | int ret; | 1921 | int ret; |
1922 | 1922 | ||
1923 | if (pi->bapm_enable) { | 1923 | if (pi->bapm_enable) { |
1924 | ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.dpm.ac_power); | 1924 | ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.ac_power); |
1925 | if (ret) { | 1925 | if (ret) { |
1926 | DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n"); | 1926 | DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n"); |
1927 | return ret; | 1927 | return ret; |
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c index b12d7c9d42a0..9567dd0a01bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c | |||
@@ -3480,7 +3480,7 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, | |||
3480 | disable_sclk_switching = true; | 3480 | disable_sclk_switching = true; |
3481 | } | 3481 | } |
3482 | 3482 | ||
3483 | if (adev->pm.dpm.ac_power) | 3483 | if (adev->pm.ac_power) |
3484 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; | 3484 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; |
3485 | else | 3485 | else |
3486 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; | 3486 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; |
@@ -3489,7 +3489,7 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, | |||
3489 | if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) | 3489 | if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) |
3490 | ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; | 3490 | ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; |
3491 | } | 3491 | } |
3492 | if (adev->pm.dpm.ac_power == false) { | 3492 | if (adev->pm.ac_power == false) { |
3493 | for (i = 0; i < ps->performance_level_count; i++) { | 3493 | for (i = 0; i < ps->performance_level_count; i++) { |
3494 | if (ps->performance_levels[i].mclk > max_limits->mclk) | 3494 | if (ps->performance_levels[i].mclk > max_limits->mclk) |
3495 | ps->performance_levels[i].mclk = max_limits->mclk; | 3495 | ps->performance_levels[i].mclk = max_limits->mclk; |
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index 4ef77cebc628..9b675d9bd162 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | |||
@@ -81,7 +81,6 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr) | |||
81 | return -EINVAL; | 81 | return -EINVAL; |
82 | 82 | ||
83 | hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT; | 83 | hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT; |
84 | hwmgr->power_source = PP_PowerSource_AC; | ||
85 | hwmgr->pp_table_version = PP_TABLE_V1; | 84 | hwmgr->pp_table_version = PP_TABLE_V1; |
86 | hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; | 85 | hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; |
87 | hwmgr->request_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; | 86 | hwmgr->request_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; |
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index 24d20d9c74b4..b89d6fb8559b 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | |||
@@ -2877,7 +2877,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, | |||
2877 | struct pp_power_state *request_ps, | 2877 | struct pp_power_state *request_ps, |
2878 | const struct pp_power_state *current_ps) | 2878 | const struct pp_power_state *current_ps) |
2879 | { | 2879 | { |
2880 | 2880 | struct amdgpu_device *adev = hwmgr->adev; | |
2881 | struct smu7_power_state *smu7_ps = | 2881 | struct smu7_power_state *smu7_ps = |
2882 | cast_phw_smu7_power_state(&request_ps->hardware); | 2882 | cast_phw_smu7_power_state(&request_ps->hardware); |
2883 | uint32_t sclk; | 2883 | uint32_t sclk; |
@@ -2900,12 +2900,12 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, | |||
2900 | "VI should always have 2 performance levels", | 2900 | "VI should always have 2 performance levels", |
2901 | ); | 2901 | ); |
2902 | 2902 | ||
2903 | max_limits = (PP_PowerSource_AC == hwmgr->power_source) ? | 2903 | max_limits = adev->pm.ac_power ? |
2904 | &(hwmgr->dyn_state.max_clock_voltage_on_ac) : | 2904 | &(hwmgr->dyn_state.max_clock_voltage_on_ac) : |
2905 | &(hwmgr->dyn_state.max_clock_voltage_on_dc); | 2905 | &(hwmgr->dyn_state.max_clock_voltage_on_dc); |
2906 | 2906 | ||
2907 | /* Cap clock DPM tables at DC MAX if it is in DC. */ | 2907 | /* Cap clock DPM tables at DC MAX if it is in DC. */ |
2908 | if (PP_PowerSource_DC == hwmgr->power_source) { | 2908 | if (!adev->pm.ac_power) { |
2909 | for (i = 0; i < smu7_ps->performance_level_count; i++) { | 2909 | for (i = 0; i < smu7_ps->performance_level_count; i++) { |
2910 | if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk) | 2910 | if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk) |
2911 | smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; | 2911 | smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; |
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index 66fd1a43e346..3b8d36df52e9 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | |||
@@ -3102,6 +3102,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, | |||
3102 | struct pp_power_state *request_ps, | 3102 | struct pp_power_state *request_ps, |
3103 | const struct pp_power_state *current_ps) | 3103 | const struct pp_power_state *current_ps) |
3104 | { | 3104 | { |
3105 | struct amdgpu_device *adev = hwmgr->adev; | ||
3105 | struct vega10_power_state *vega10_ps = | 3106 | struct vega10_power_state *vega10_ps = |
3106 | cast_phw_vega10_power_state(&request_ps->hardware); | 3107 | cast_phw_vega10_power_state(&request_ps->hardware); |
3107 | uint32_t sclk; | 3108 | uint32_t sclk; |
@@ -3127,12 +3128,12 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, | |||
3127 | if (vega10_ps->performance_level_count != 2) | 3128 | if (vega10_ps->performance_level_count != 2) |
3128 | pr_info("VI should always have 2 performance levels"); | 3129 | pr_info("VI should always have 2 performance levels"); |
3129 | 3130 | ||
3130 | max_limits = (PP_PowerSource_AC == hwmgr->power_source) ? | 3131 | max_limits = adev->pm.ac_power ? |
3131 | &(hwmgr->dyn_state.max_clock_voltage_on_ac) : | 3132 | &(hwmgr->dyn_state.max_clock_voltage_on_ac) : |
3132 | &(hwmgr->dyn_state.max_clock_voltage_on_dc); | 3133 | &(hwmgr->dyn_state.max_clock_voltage_on_dc); |
3133 | 3134 | ||
3134 | /* Cap clock DPM tables at DC MAX if it is in DC. */ | 3135 | /* Cap clock DPM tables at DC MAX if it is in DC. */ |
3135 | if (PP_PowerSource_DC == hwmgr->power_source) { | 3136 | if (!adev->pm.ac_power) { |
3136 | for (i = 0; i < vega10_ps->performance_level_count; i++) { | 3137 | for (i = 0; i < vega10_ps->performance_level_count; i++) { |
3137 | if (vega10_ps->performance_levels[i].mem_clock > | 3138 | if (vega10_ps->performance_levels[i].mem_clock > |
3138 | max_limits->mclk) | 3139 | max_limits->mclk) |
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h index b99fb8ac822c..40c98ca5feb7 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | |||
@@ -26,7 +26,6 @@ | |||
26 | #include <linux/seq_file.h> | 26 | #include <linux/seq_file.h> |
27 | #include "amd_powerplay.h" | 27 | #include "amd_powerplay.h" |
28 | #include "hardwaremanager.h" | 28 | #include "hardwaremanager.h" |
29 | #include "pp_power_source.h" | ||
30 | #include "hwmgr_ppt.h" | 29 | #include "hwmgr_ppt.h" |
31 | #include "ppatomctrl.h" | 30 | #include "ppatomctrl.h" |
32 | #include "hwmgr_ppt.h" | 31 | #include "hwmgr_ppt.h" |
@@ -741,7 +740,6 @@ struct pp_hwmgr { | |||
741 | const struct pp_table_func *pptable_func; | 740 | const struct pp_table_func *pptable_func; |
742 | 741 | ||
743 | struct pp_power_state *ps; | 742 | struct pp_power_state *ps; |
744 | enum pp_power_source power_source; | ||
745 | uint32_t num_ps; | 743 | uint32_t num_ps; |
746 | struct pp_thermal_controller_info thermal_controller; | 744 | struct pp_thermal_controller_info thermal_controller; |
747 | bool fan_ctrl_is_in_default_mode; | 745 | bool fan_ctrl_is_in_default_mode; |
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_power_source.h b/drivers/gpu/drm/amd/powerplay/inc/pp_power_source.h deleted file mode 100644 index b43315cc5d58..000000000000 --- a/drivers/gpu/drm/amd/powerplay/inc/pp_power_source.h +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2015 Advanced Micro Devices, Inc. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | */ | ||
23 | |||
24 | #ifndef PP_POWERSOURCE_H | ||
25 | #define PP_POWERSOURCE_H | ||
26 | |||
27 | enum pp_power_source { | ||
28 | PP_PowerSource_AC = 0, | ||
29 | PP_PowerSource_DC, | ||
30 | PP_PowerSource_LimitedPower, | ||
31 | PP_PowerSource_LimitedPower_2, | ||
32 | PP_PowerSource_Max | ||
33 | }; | ||
34 | |||
35 | |||
36 | #endif | ||