1 files changed, 9 insertions, 12 deletions

diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c
index adf4d5efced6..7683de9fb9ee 100644
--- a/drivers/dma/dma-jz4780.c
+++ b/drivers/dma/dma-jz4780.c
@@ -95,17 +95,12 @@
  * @dtc: transfer count (number of blocks of the transfer size specified in DCM
  * to transfer) in the low 24 bits, offset of the next descriptor from the
  * descriptor base address in the upper 8 bits.
- * @sd: target/source stride difference (in stride transfer mode).
- * @drt: request type
  */
 struct jz4780_dma_hwdesc {
         uint32_t dcm;
         uint32_t dsa;
         uint32_t dta;
         uint32_t dtc;
-        uint32_t sd;
-        uint32_t drt;
-        uint32_t reserved[2];
 };
 
 /* Size of allocations for hardware descriptor blocks. */
@@ -281,7 +276,6 @@ static int jz4780_dma_setup_hwdesc(struct jz4780_dma_chan *jzchan,
                 desc->dcm = JZ_DMA_DCM_SAI;
                 desc->dsa = addr;
                 desc->dta = config->dst_addr;
-                desc->drt = jzchan->transfer_type;
 
                 width = config->dst_addr_width;
                 maxburst = config->dst_maxburst;
@@ -289,7 +283,6 @@ static int jz4780_dma_setup_hwdesc(struct jz4780_dma_chan *jzchan,
                 desc->dcm = JZ_DMA_DCM_DAI;
                 desc->dsa = config->src_addr;
                 desc->dta = addr;
-                desc->drt = jzchan->transfer_type;
 
                 width = config->src_addr_width;
                 maxburst = config->src_maxburst;
@@ -434,9 +427,10 @@ static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_memcpy(
         tsz = jz4780_dma_transfer_size(dest | src | len,
                                        &jzchan->transfer_shift);
 
+        jzchan->transfer_type = JZ_DMA_DRT_AUTO;
+
         desc->desc[0].dsa = src;
         desc->desc[0].dta = dest;
-        desc->desc[0].drt = JZ_DMA_DRT_AUTO;
         desc->desc[0].dcm = JZ_DMA_DCM_TIE | JZ_DMA_DCM_SAI | JZ_DMA_DCM_DAI |
                             tsz << JZ_DMA_DCM_TSZ_SHIFT |
                             JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_SP_SHIFT |
@@ -491,9 +485,12 @@ static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan)
                         (jzchan->curr_hwdesc + 1) % jzchan->desc->count;
         }
 
-        /* Use 8-word descriptors. */
-        jz4780_dma_chn_writel(jzdma, jzchan->id,
-                              JZ_DMA_REG_DCS, JZ_DMA_DCS_DES8);
+        /* Use 4-word descriptors. */
+        jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
+
+        /* Set transfer type. */
+        jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DRT,
+                              jzchan->transfer_type);
 
         /* Write descriptor address and initiate descriptor fetch. */
         desc_phys = jzchan->desc->desc_phys +
@@ -503,7 +500,7 @@ static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan)
 
         /* Enable the channel. */
         jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS,
-                              JZ_DMA_DCS_DES8 | JZ_DMA_DCS_CTE);
+                              JZ_DMA_DCS_CTE);
 }
 
 static void jz4780_dma_issue_pending(struct dma_chan *chan)