1 files changed, 20 insertions, 6 deletions

diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 238ae3248ba5..4cf100ff2a37 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -40,16 +40,16 @@
  * Model specific counters:
  *      MSR_CORE_C1_RES: CORE C1 Residency Counter
  *                       perf code: 0x00
- *                       Available model: SLM,AMT
+ *                       Available model: SLM,AMT,GLM
  *                       Scope: Core (each processor core has a MSR)
  *      MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
  *                             perf code: 0x01
- *                             Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL
+ *                             Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM
  *                             Scope: Core
  *      MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
  *                             perf code: 0x02
  *                             Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- *                                              SKL,KNL
+ *                                              SKL,KNL,GLM
  *                             Scope: Core
  *      MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
  *                             perf code: 0x03
@@ -57,16 +57,17 @@
  *                             Scope: Core
  *      MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.
  *                             perf code: 0x00
- *                             Available model: SNB,IVB,HSW,BDW,SKL,KNL
+ *                             Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM
  *                             Scope: Package (physical package)
  *      MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.
  *                             perf code: 0x01
  *                             Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL
+ *                                              GLM
  *                             Scope: Package (physical package)
  *      MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.
  *                             perf code: 0x02
  *                             Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- *                                              SKL,KNL
+ *                                              SKL,KNL,GLM
  *                             Scope: Package (physical package)
  *      MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.
  *                             perf code: 0x03
@@ -82,7 +83,7 @@
  *                             Scope: Package (physical package)
  *      MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
  *                             perf code: 0x06
- *                             Available model: HSW ULT only
+ *                             Available model: HSW ULT, GLM
  *                             Scope: Package (physical package)
  *
  */
@@ -504,6 +505,17 @@ static const struct cstate_model knl_cstates __initconst = {
 };
 
 
+static const struct cstate_model glm_cstates __initconst = {
+        .core_events            = BIT(PERF_CSTATE_CORE_C1_RES) |
+                                  BIT(PERF_CSTATE_CORE_C3_RES) |
+                                  BIT(PERF_CSTATE_CORE_C6_RES),
+
+        .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
+                                  BIT(PERF_CSTATE_PKG_C3_RES) |
+                                  BIT(PERF_CSTATE_PKG_C6_RES) |
+                                  BIT(PERF_CSTATE_PKG_C10_RES),
+};
+
 
 #define X86_CSTATES_MODEL(model, states)                                \
         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long) &(states) }
@@ -546,6 +558,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 
         X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),
         X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),
+
+        X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT, glm_cstates),
         { },
 };
 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);