aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c6
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c20
-rw-r--r--drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c86
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c10
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_surface.c14
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h5
-rw-r--r--drivers/gpu/drm/amd/display/include/dal_asic_id.h9
-rw-r--r--drivers/gpu/drm/amd/display/modules/color/color_gamma.c72
-rw-r--r--drivers/gpu/drm/amd/include/atomfirmware.h170
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c52
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h1
-rw-r--r--drivers/gpu/drm/ttm/ttm_page_alloc.c11
-rw-r--r--drivers/gpu/drm/ttm/ttm_page_alloc_dma.c3
13 files changed, 364 insertions, 95 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 09d35051fdd6..3fabf9f97022 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -419,9 +419,11 @@ int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id)
419 419
420 if (other) { 420 if (other) {
421 signed long r; 421 signed long r;
422 r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT); 422 r = dma_fence_wait(other, true);
423 if (r < 0) { 423 if (r < 0) {
424 DRM_ERROR("Error (%ld) waiting for fence!\n", r); 424 if (r != -ERESTARTSYS)
425 DRM_ERROR("Error (%ld) waiting for fence!\n", r);
426
425 return r; 427 return r;
426 } 428 }
427 } 429 }
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index ace9ad578ca0..4304d9e408b8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -83,21 +83,22 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
83 enum i2c_mot_mode mot = (msg->request & DP_AUX_I2C_MOT) ? 83 enum i2c_mot_mode mot = (msg->request & DP_AUX_I2C_MOT) ?
84 I2C_MOT_TRUE : I2C_MOT_FALSE; 84 I2C_MOT_TRUE : I2C_MOT_FALSE;
85 enum ddc_result res; 85 enum ddc_result res;
86 ssize_t read_bytes; 86 uint32_t read_bytes = msg->size;
87 87
88 if (WARN_ON(msg->size > 16)) 88 if (WARN_ON(msg->size > 16))
89 return -E2BIG; 89 return -E2BIG;
90 90
91 switch (msg->request & ~DP_AUX_I2C_MOT) { 91 switch (msg->request & ~DP_AUX_I2C_MOT) {
92 case DP_AUX_NATIVE_READ: 92 case DP_AUX_NATIVE_READ:
93 read_bytes = dal_ddc_service_read_dpcd_data( 93 res = dal_ddc_service_read_dpcd_data(
94 TO_DM_AUX(aux)->ddc_service, 94 TO_DM_AUX(aux)->ddc_service,
95 false, 95 false,
96 I2C_MOT_UNDEF, 96 I2C_MOT_UNDEF,
97 msg->address, 97 msg->address,
98 msg->buffer, 98 msg->buffer,
99 msg->size); 99 msg->size,
100 return read_bytes; 100 &read_bytes);
101 break;
101 case DP_AUX_NATIVE_WRITE: 102 case DP_AUX_NATIVE_WRITE:
102 res = dal_ddc_service_write_dpcd_data( 103 res = dal_ddc_service_write_dpcd_data(
103 TO_DM_AUX(aux)->ddc_service, 104 TO_DM_AUX(aux)->ddc_service,
@@ -108,14 +109,15 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
108 msg->size); 109 msg->size);
109 break; 110 break;
110 case DP_AUX_I2C_READ: 111 case DP_AUX_I2C_READ:
111 read_bytes = dal_ddc_service_read_dpcd_data( 112 res = dal_ddc_service_read_dpcd_data(
112 TO_DM_AUX(aux)->ddc_service, 113 TO_DM_AUX(aux)->ddc_service,
113 true, 114 true,
114 mot, 115 mot,
115 msg->address, 116 msg->address,
116 msg->buffer, 117 msg->buffer,
117 msg->size); 118 msg->size,
118 return read_bytes; 119 &read_bytes);
120 break;
119 case DP_AUX_I2C_WRITE: 121 case DP_AUX_I2C_WRITE:
120 res = dal_ddc_service_write_dpcd_data( 122 res = dal_ddc_service_write_dpcd_data(
121 TO_DM_AUX(aux)->ddc_service, 123 TO_DM_AUX(aux)->ddc_service,
@@ -137,7 +139,9 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
137 r == DDC_RESULT_SUCESSFULL); 139 r == DDC_RESULT_SUCESSFULL);
138#endif 140#endif
139 141
140 return msg->size; 142 if (res != DDC_RESULT_SUCESSFULL)
143 return -EIO;
144 return read_bytes;
141} 145}
142 146
143static enum drm_connector_status 147static enum drm_connector_status
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 985fe8c22875..10a5807a7e8b 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -70,6 +70,10 @@ static enum bp_result get_firmware_info_v3_1(
70 struct bios_parser *bp, 70 struct bios_parser *bp,
71 struct dc_firmware_info *info); 71 struct dc_firmware_info *info);
72 72
73static enum bp_result get_firmware_info_v3_2(
74 struct bios_parser *bp,
75 struct dc_firmware_info *info);
76
73static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 77static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
74 struct atom_display_object_path_v2 *object); 78 struct atom_display_object_path_v2 *object);
75 79
@@ -1321,9 +1325,11 @@ static enum bp_result bios_parser_get_firmware_info(
1321 case 3: 1325 case 3:
1322 switch (revision.minor) { 1326 switch (revision.minor) {
1323 case 1: 1327 case 1:
1324 case 2:
1325 result = get_firmware_info_v3_1(bp, info); 1328 result = get_firmware_info_v3_1(bp, info);
1326 break; 1329 break;
1330 case 2:
1331 result = get_firmware_info_v3_2(bp, info);
1332 break;
1327 default: 1333 default:
1328 break; 1334 break;
1329 } 1335 }
@@ -1383,6 +1389,84 @@ static enum bp_result get_firmware_info_v3_1(
1383 return BP_RESULT_OK; 1389 return BP_RESULT_OK;
1384} 1390}
1385 1391
1392static enum bp_result get_firmware_info_v3_2(
1393 struct bios_parser *bp,
1394 struct dc_firmware_info *info)
1395{
1396 struct atom_firmware_info_v3_2 *firmware_info;
1397 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1398 struct atom_common_table_header *header;
1399 struct atom_data_revision revision;
1400 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1401 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1402
1403 if (!info)
1404 return BP_RESULT_BADINPUT;
1405
1406 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1407 DATA_TABLES(firmwareinfo));
1408
1409 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1410 DATA_TABLES(dce_info));
1411
1412 if (!firmware_info || !dce_info)
1413 return BP_RESULT_BADBIOSTABLE;
1414
1415 memset(info, 0, sizeof(*info));
1416
1417 header = GET_IMAGE(struct atom_common_table_header,
1418 DATA_TABLES(smu_info));
1419 get_atom_data_table_revision(header, &revision);
1420
1421 if (revision.minor == 2) {
1422 /* Vega12 */
1423 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1424 DATA_TABLES(smu_info));
1425
1426 if (!smu_info_v3_2)
1427 return BP_RESULT_BADBIOSTABLE;
1428
1429 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1430 } else if (revision.minor == 3) {
1431 /* Vega20 */
1432 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1433 DATA_TABLES(smu_info));
1434
1435 if (!smu_info_v3_3)
1436 return BP_RESULT_BADBIOSTABLE;
1437
1438 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1439 }
1440
1441 // We need to convert from 10KHz units into KHz units.
1442 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1443
1444 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1445 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1446 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1447 if (info->pll_info.crystal_frequency == 0) {
1448 if (revision.minor == 2)
1449 info->pll_info.crystal_frequency = 27000;
1450 else if (revision.minor == 3)
1451 info->pll_info.crystal_frequency = 100000;
1452 }
1453 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1454 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1455 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1456
1457 /* Get GPU PLL VCO Clock */
1458 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1459 if (revision.minor == 2)
1460 info->smu_gpu_pll_output_freq =
1461 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1462 else if (revision.minor == 3)
1463 info->smu_gpu_pll_output_freq =
1464 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1465 }
1466
1467 return BP_RESULT_OK;
1468}
1469
1386static enum bp_result bios_parser_get_encoder_cap_info( 1470static enum bp_result bios_parser_get_encoder_cap_info(
1387 struct dc_bios *dcb, 1471 struct dc_bios *dcb,
1388 struct graphics_object_id object_id, 1472 struct graphics_object_id object_id,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index 49c2face1e7a..ae48d603ebd6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -629,13 +629,14 @@ bool dal_ddc_service_query_ddc_data(
629 return ret; 629 return ret;
630} 630}
631 631
632ssize_t dal_ddc_service_read_dpcd_data( 632enum ddc_result dal_ddc_service_read_dpcd_data(
633 struct ddc_service *ddc, 633 struct ddc_service *ddc,
634 bool i2c, 634 bool i2c,
635 enum i2c_mot_mode mot, 635 enum i2c_mot_mode mot,
636 uint32_t address, 636 uint32_t address,
637 uint8_t *data, 637 uint8_t *data,
638 uint32_t len) 638 uint32_t len,
639 uint32_t *read)
639{ 640{
640 struct aux_payload read_payload = { 641 struct aux_payload read_payload = {
641 .i2c_over_aux = i2c, 642 .i2c_over_aux = i2c,
@@ -652,6 +653,8 @@ ssize_t dal_ddc_service_read_dpcd_data(
652 .mot = mot 653 .mot = mot
653 }; 654 };
654 655
656 *read = 0;
657
655 if (len > DEFAULT_AUX_MAX_DATA_SIZE) { 658 if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
656 BREAK_TO_DEBUGGER(); 659 BREAK_TO_DEBUGGER();
657 return DDC_RESULT_FAILED_INVALID_OPERATION; 660 return DDC_RESULT_FAILED_INVALID_OPERATION;
@@ -661,7 +664,8 @@ ssize_t dal_ddc_service_read_dpcd_data(
661 ddc->ctx->i2caux, 664 ddc->ctx->i2caux,
662 ddc->ddc_pin, 665 ddc->ddc_pin,
663 &command)) { 666 &command)) {
664 return (ssize_t)command.payloads->length; 667 *read = command.payloads->length;
668 return DDC_RESULT_SUCESSFULL;
665 } 669 }
666 670
667 return DDC_RESULT_FAILED_OPERATION; 671 return DDC_RESULT_FAILED_OPERATION;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
index ade5b8ee9c3c..132eef3826e2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
@@ -66,8 +66,8 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc)
66{ 66{
67 struct dc *core_dc = dc; 67 struct dc *core_dc = dc;
68 68
69 struct dc_plane_state *plane_state = kzalloc(sizeof(*plane_state), 69 struct dc_plane_state *plane_state = kvzalloc(sizeof(*plane_state),
70 GFP_KERNEL); 70 GFP_KERNEL);
71 71
72 if (NULL == plane_state) 72 if (NULL == plane_state)
73 return NULL; 73 return NULL;
@@ -120,7 +120,7 @@ static void dc_plane_state_free(struct kref *kref)
120{ 120{
121 struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount); 121 struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount);
122 destruct(plane_state); 122 destruct(plane_state);
123 kfree(plane_state); 123 kvfree(plane_state);
124} 124}
125 125
126void dc_plane_state_release(struct dc_plane_state *plane_state) 126void dc_plane_state_release(struct dc_plane_state *plane_state)
@@ -136,7 +136,7 @@ void dc_gamma_retain(struct dc_gamma *gamma)
136static void dc_gamma_free(struct kref *kref) 136static void dc_gamma_free(struct kref *kref)
137{ 137{
138 struct dc_gamma *gamma = container_of(kref, struct dc_gamma, refcount); 138 struct dc_gamma *gamma = container_of(kref, struct dc_gamma, refcount);
139 kfree(gamma); 139 kvfree(gamma);
140} 140}
141 141
142void dc_gamma_release(struct dc_gamma **gamma) 142void dc_gamma_release(struct dc_gamma **gamma)
@@ -147,7 +147,7 @@ void dc_gamma_release(struct dc_gamma **gamma)
147 147
148struct dc_gamma *dc_create_gamma(void) 148struct dc_gamma *dc_create_gamma(void)
149{ 149{
150 struct dc_gamma *gamma = kzalloc(sizeof(*gamma), GFP_KERNEL); 150 struct dc_gamma *gamma = kvzalloc(sizeof(*gamma), GFP_KERNEL);
151 151
152 if (gamma == NULL) 152 if (gamma == NULL)
153 goto alloc_fail; 153 goto alloc_fail;
@@ -167,7 +167,7 @@ void dc_transfer_func_retain(struct dc_transfer_func *tf)
167static void dc_transfer_func_free(struct kref *kref) 167static void dc_transfer_func_free(struct kref *kref)
168{ 168{
169 struct dc_transfer_func *tf = container_of(kref, struct dc_transfer_func, refcount); 169 struct dc_transfer_func *tf = container_of(kref, struct dc_transfer_func, refcount);
170 kfree(tf); 170 kvfree(tf);
171} 171}
172 172
173void dc_transfer_func_release(struct dc_transfer_func *tf) 173void dc_transfer_func_release(struct dc_transfer_func *tf)
@@ -177,7 +177,7 @@ void dc_transfer_func_release(struct dc_transfer_func *tf)
177 177
178struct dc_transfer_func *dc_create_transfer_func(void) 178struct dc_transfer_func *dc_create_transfer_func(void)
179{ 179{
180 struct dc_transfer_func *tf = kzalloc(sizeof(*tf), GFP_KERNEL); 180 struct dc_transfer_func *tf = kvzalloc(sizeof(*tf), GFP_KERNEL);
181 181
182 if (tf == NULL) 182 if (tf == NULL)
183 goto alloc_fail; 183 goto alloc_fail;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
index 090b7a8dd67b..30b3a08b91be 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
@@ -102,13 +102,14 @@ bool dal_ddc_service_query_ddc_data(
102 uint8_t *read_buf, 102 uint8_t *read_buf,
103 uint32_t read_size); 103 uint32_t read_size);
104 104
105ssize_t dal_ddc_service_read_dpcd_data( 105enum ddc_result dal_ddc_service_read_dpcd_data(
106 struct ddc_service *ddc, 106 struct ddc_service *ddc,
107 bool i2c, 107 bool i2c,
108 enum i2c_mot_mode mot, 108 enum i2c_mot_mode mot,
109 uint32_t address, 109 uint32_t address,
110 uint8_t *data, 110 uint8_t *data,
111 uint32_t len); 111 uint32_t len,
112 uint32_t *read);
112 113
113enum ddc_result dal_ddc_service_write_dpcd_data( 114enum ddc_result dal_ddc_service_write_dpcd_data(
114 struct ddc_service *ddc, 115 struct ddc_service *ddc,
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 9831cb5eaa7c..9b0a04f99ac8 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -113,9 +113,14 @@
113 113
114#define AI_GREENLAND_P_A0 1 114#define AI_GREENLAND_P_A0 1
115#define AI_GREENLAND_P_A1 2 115#define AI_GREENLAND_P_A1 2
116#define AI_UNKNOWN 0xFF
116 117
117#define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_UNKNOWN) 118#define AI_VEGA12_P_A0 20
118#define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_UNKNOWN) 119#define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_VEGA12_P_A0)
120#define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_VEGA12_P_A0)
121
122#define ASICREV_IS_VEGA12_P(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN))
123#define ASICREV_IS_VEGA12_p(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN))
119 124
120/* DCN1_0 */ 125/* DCN1_0 */
121#define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */ 126#define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index e7e374f56864..b3747a019deb 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -1093,19 +1093,19 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
1093 1093
1094 output_tf->type = TF_TYPE_DISTRIBUTED_POINTS; 1094 output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
1095 1095
1096 rgb_user = kzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS), 1096 rgb_user = kvzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
1097 GFP_KERNEL); 1097 GFP_KERNEL);
1098 if (!rgb_user) 1098 if (!rgb_user)
1099 goto rgb_user_alloc_fail; 1099 goto rgb_user_alloc_fail;
1100 rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS + _EXTRA_POINTS), 1100 rgb_regamma = kvzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS + _EXTRA_POINTS),
1101 GFP_KERNEL); 1101 GFP_KERNEL);
1102 if (!rgb_regamma) 1102 if (!rgb_regamma)
1103 goto rgb_regamma_alloc_fail; 1103 goto rgb_regamma_alloc_fail;
1104 axix_x = kzalloc(sizeof(*axix_x) * (ramp->num_entries + 3), 1104 axix_x = kvzalloc(sizeof(*axix_x) * (ramp->num_entries + 3),
1105 GFP_KERNEL); 1105 GFP_KERNEL);
1106 if (!axix_x) 1106 if (!axix_x)
1107 goto axix_x_alloc_fail; 1107 goto axix_x_alloc_fail;
1108 coeff = kzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL); 1108 coeff = kvzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
1109 if (!coeff) 1109 if (!coeff)
1110 goto coeff_alloc_fail; 1110 goto coeff_alloc_fail;
1111 1111
@@ -1157,13 +1157,13 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
1157 1157
1158 ret = true; 1158 ret = true;
1159 1159
1160 kfree(coeff); 1160 kvfree(coeff);
1161coeff_alloc_fail: 1161coeff_alloc_fail:
1162 kfree(axix_x); 1162 kvfree(axix_x);
1163axix_x_alloc_fail: 1163axix_x_alloc_fail:
1164 kfree(rgb_regamma); 1164 kvfree(rgb_regamma);
1165rgb_regamma_alloc_fail: 1165rgb_regamma_alloc_fail:
1166 kfree(rgb_user); 1166 kvfree(rgb_user);
1167rgb_user_alloc_fail: 1167rgb_user_alloc_fail:
1168 return ret; 1168 return ret;
1169} 1169}
@@ -1192,19 +1192,19 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf,
1192 1192
1193 input_tf->type = TF_TYPE_DISTRIBUTED_POINTS; 1193 input_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
1194 1194
1195 rgb_user = kzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS), 1195 rgb_user = kvzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
1196 GFP_KERNEL); 1196 GFP_KERNEL);
1197 if (!rgb_user) 1197 if (!rgb_user)
1198 goto rgb_user_alloc_fail; 1198 goto rgb_user_alloc_fail;
1199 curve = kzalloc(sizeof(*curve) * (MAX_HW_POINTS + _EXTRA_POINTS), 1199 curve = kvzalloc(sizeof(*curve) * (MAX_HW_POINTS + _EXTRA_POINTS),
1200 GFP_KERNEL); 1200 GFP_KERNEL);
1201 if (!curve) 1201 if (!curve)
1202 goto curve_alloc_fail; 1202 goto curve_alloc_fail;
1203 axix_x = kzalloc(sizeof(*axix_x) * (ramp->num_entries + _EXTRA_POINTS), 1203 axix_x = kvzalloc(sizeof(*axix_x) * (ramp->num_entries + _EXTRA_POINTS),
1204 GFP_KERNEL); 1204 GFP_KERNEL);
1205 if (!axix_x) 1205 if (!axix_x)
1206 goto axix_x_alloc_fail; 1206 goto axix_x_alloc_fail;
1207 coeff = kzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL); 1207 coeff = kvzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
1208 if (!coeff) 1208 if (!coeff)
1209 goto coeff_alloc_fail; 1209 goto coeff_alloc_fail;
1210 1210
@@ -1246,13 +1246,13 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf,
1246 1246
1247 ret = true; 1247 ret = true;
1248 1248
1249 kfree(coeff); 1249 kvfree(coeff);
1250coeff_alloc_fail: 1250coeff_alloc_fail:
1251 kfree(axix_x); 1251 kvfree(axix_x);
1252axix_x_alloc_fail: 1252axix_x_alloc_fail:
1253 kfree(curve); 1253 kvfree(curve);
1254curve_alloc_fail: 1254curve_alloc_fail:
1255 kfree(rgb_user); 1255 kvfree(rgb_user);
1256rgb_user_alloc_fail: 1256rgb_user_alloc_fail:
1257 1257
1258 return ret; 1258 return ret;
@@ -1281,8 +1281,9 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
1281 } 1281 }
1282 ret = true; 1282 ret = true;
1283 } else if (trans == TRANSFER_FUNCTION_PQ) { 1283 } else if (trans == TRANSFER_FUNCTION_PQ) {
1284 rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS + 1284 rgb_regamma = kvzalloc(sizeof(*rgb_regamma) *
1285 _EXTRA_POINTS), GFP_KERNEL); 1285 (MAX_HW_POINTS + _EXTRA_POINTS),
1286 GFP_KERNEL);
1286 if (!rgb_regamma) 1287 if (!rgb_regamma)
1287 goto rgb_regamma_alloc_fail; 1288 goto rgb_regamma_alloc_fail;
1288 points->end_exponent = 7; 1289 points->end_exponent = 7;
@@ -1302,11 +1303,12 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
1302 } 1303 }
1303 ret = true; 1304 ret = true;
1304 1305
1305 kfree(rgb_regamma); 1306 kvfree(rgb_regamma);
1306 } else if (trans == TRANSFER_FUNCTION_SRGB || 1307 } else if (trans == TRANSFER_FUNCTION_SRGB ||
1307 trans == TRANSFER_FUNCTION_BT709) { 1308 trans == TRANSFER_FUNCTION_BT709) {
1308 rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS + 1309 rgb_regamma = kvzalloc(sizeof(*rgb_regamma) *
1309 _EXTRA_POINTS), GFP_KERNEL); 1310 (MAX_HW_POINTS + _EXTRA_POINTS),
1311 GFP_KERNEL);
1310 if (!rgb_regamma) 1312 if (!rgb_regamma)
1311 goto rgb_regamma_alloc_fail; 1313 goto rgb_regamma_alloc_fail;
1312 points->end_exponent = 0; 1314 points->end_exponent = 0;
@@ -1324,7 +1326,7 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
1324 } 1326 }
1325 ret = true; 1327 ret = true;
1326 1328
1327 kfree(rgb_regamma); 1329 kvfree(rgb_regamma);
1328 } 1330 }
1329rgb_regamma_alloc_fail: 1331rgb_regamma_alloc_fail:
1330 return ret; 1332 return ret;
@@ -1348,8 +1350,9 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
1348 } 1350 }
1349 ret = true; 1351 ret = true;
1350 } else if (trans == TRANSFER_FUNCTION_PQ) { 1352 } else if (trans == TRANSFER_FUNCTION_PQ) {
1351 rgb_degamma = kzalloc(sizeof(*rgb_degamma) * (MAX_HW_POINTS + 1353 rgb_degamma = kvzalloc(sizeof(*rgb_degamma) *
1352 _EXTRA_POINTS), GFP_KERNEL); 1354 (MAX_HW_POINTS + _EXTRA_POINTS),
1355 GFP_KERNEL);
1353 if (!rgb_degamma) 1356 if (!rgb_degamma)
1354 goto rgb_degamma_alloc_fail; 1357 goto rgb_degamma_alloc_fail;
1355 1358
@@ -1364,11 +1367,12 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
1364 } 1367 }
1365 ret = true; 1368 ret = true;
1366 1369
1367 kfree(rgb_degamma); 1370 kvfree(rgb_degamma);
1368 } else if (trans == TRANSFER_FUNCTION_SRGB || 1371 } else if (trans == TRANSFER_FUNCTION_SRGB ||
1369 trans == TRANSFER_FUNCTION_BT709) { 1372 trans == TRANSFER_FUNCTION_BT709) {
1370 rgb_degamma = kzalloc(sizeof(*rgb_degamma) * (MAX_HW_POINTS + 1373 rgb_degamma = kvzalloc(sizeof(*rgb_degamma) *
1371 _EXTRA_POINTS), GFP_KERNEL); 1374 (MAX_HW_POINTS + _EXTRA_POINTS),
1375 GFP_KERNEL);
1372 if (!rgb_degamma) 1376 if (!rgb_degamma)
1373 goto rgb_degamma_alloc_fail; 1377 goto rgb_degamma_alloc_fail;
1374 1378
@@ -1382,7 +1386,7 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
1382 } 1386 }
1383 ret = true; 1387 ret = true;
1384 1388
1385 kfree(rgb_degamma); 1389 kvfree(rgb_degamma);
1386 } 1390 }
1387 points->end_exponent = 0; 1391 points->end_exponent = 0;
1388 points->x_point_at_y1_red = 1; 1392 points->x_point_at_y1_red = 1;
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index 0f5ad54d3fd3..de177ce8ca80 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -501,6 +501,32 @@ enum atom_cooling_solution_id{
501 LIQUID_COOLING = 0x01 501 LIQUID_COOLING = 0x01
502}; 502};
503 503
504struct atom_firmware_info_v3_2 {
505 struct atom_common_table_header table_header;
506 uint32_t firmware_revision;
507 uint32_t bootup_sclk_in10khz;
508 uint32_t bootup_mclk_in10khz;
509 uint32_t firmware_capability; // enum atombios_firmware_capability
510 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
511 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
512 uint16_t bootup_vddc_mv;
513 uint16_t bootup_vddci_mv;
514 uint16_t bootup_mvddc_mv;
515 uint16_t bootup_vddgfx_mv;
516 uint8_t mem_module_id;
517 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
518 uint8_t reserved1[2];
519 uint32_t mc_baseaddr_high;
520 uint32_t mc_baseaddr_low;
521 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
522 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
523 uint8_t board_i2c_feature_slave_addr;
524 uint8_t reserved3;
525 uint16_t bootup_mvddq_mv;
526 uint16_t bootup_mvpp_mv;
527 uint32_t zfbstartaddrin16mb;
528 uint32_t reserved2[3];
529};
504 530
505/* 531/*
506 *************************************************************************** 532 ***************************************************************************
@@ -1169,7 +1195,29 @@ struct atom_gfx_info_v2_2
1169 uint32_t rlc_gpu_timer_refclk; 1195 uint32_t rlc_gpu_timer_refclk;
1170}; 1196};
1171 1197
1172 1198struct atom_gfx_info_v2_3 {
1199 struct atom_common_table_header table_header;
1200 uint8_t gfxip_min_ver;
1201 uint8_t gfxip_max_ver;
1202 uint8_t max_shader_engines;
1203 uint8_t max_tile_pipes;
1204 uint8_t max_cu_per_sh;
1205 uint8_t max_sh_per_se;
1206 uint8_t max_backends_per_se;
1207 uint8_t max_texture_channel_caches;
1208 uint32_t regaddr_cp_dma_src_addr;
1209 uint32_t regaddr_cp_dma_src_addr_hi;
1210 uint32_t regaddr_cp_dma_dst_addr;
1211 uint32_t regaddr_cp_dma_dst_addr_hi;
1212 uint32_t regaddr_cp_dma_command;
1213 uint32_t regaddr_cp_status;
1214 uint32_t regaddr_rlc_gpu_clock_32;
1215 uint32_t rlc_gpu_timer_refclk;
1216 uint8_t active_cu_per_sh;
1217 uint8_t active_rb_per_se;
1218 uint16_t gcgoldenoffset;
1219 uint32_t rm21_sram_vmin_value;
1220};
1173 1221
1174/* 1222/*
1175 *************************************************************************** 1223 ***************************************************************************
@@ -1198,6 +1246,76 @@ struct atom_smu_info_v3_1
1198 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1246 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1199}; 1247};
1200 1248
1249struct atom_smu_info_v3_2 {
1250 struct atom_common_table_header table_header;
1251 uint8_t smuip_min_ver;
1252 uint8_t smuip_max_ver;
1253 uint8_t smu_rsd1;
1254 uint8_t gpuclk_ss_mode;
1255 uint16_t sclk_ss_percentage;
1256 uint16_t sclk_ss_rate_10hz;
1257 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1258 uint16_t gpuclk_ss_rate_10hz;
1259 uint32_t core_refclk_10khz;
1260 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1261 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1262 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1263 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1264 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1265 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1266 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1267 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1268 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1269 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1270 uint16_t smugoldenoffset;
1271 uint32_t gpupll_vco_freq_10khz;
1272 uint32_t bootup_smnclk_10khz;
1273 uint32_t bootup_socclk_10khz;
1274 uint32_t bootup_mp0clk_10khz;
1275 uint32_t bootup_mp1clk_10khz;
1276 uint32_t bootup_lclk_10khz;
1277 uint32_t bootup_dcefclk_10khz;
1278 uint32_t ctf_threshold_override_value;
1279 uint32_t reserved[5];
1280};
1281
1282struct atom_smu_info_v3_3 {
1283 struct atom_common_table_header table_header;
1284 uint8_t smuip_min_ver;
1285 uint8_t smuip_max_ver;
1286 uint8_t smu_rsd1;
1287 uint8_t gpuclk_ss_mode;
1288 uint16_t sclk_ss_percentage;
1289 uint16_t sclk_ss_rate_10hz;
1290 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1291 uint16_t gpuclk_ss_rate_10hz;
1292 uint32_t core_refclk_10khz;
1293 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1294 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1295 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1296 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1297 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1298 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1299 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1300 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1301 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1302 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1303 uint16_t smugoldenoffset;
1304 uint32_t gpupll_vco_freq_10khz;
1305 uint32_t bootup_smnclk_10khz;
1306 uint32_t bootup_socclk_10khz;
1307 uint32_t bootup_mp0clk_10khz;
1308 uint32_t bootup_mp1clk_10khz;
1309 uint32_t bootup_lclk_10khz;
1310 uint32_t bootup_dcefclk_10khz;
1311 uint32_t ctf_threshold_override_value;
1312 uint32_t syspll3_0_vco_freq_10khz;
1313 uint32_t syspll3_1_vco_freq_10khz;
1314 uint32_t bootup_fclk_10khz;
1315 uint32_t bootup_waflclk_10khz;
1316 uint32_t reserved[3];
1317};
1318
1201/* 1319/*
1202 *************************************************************************** 1320 ***************************************************************************
1203 Data Table smc_dpm_info structure 1321 Data Table smc_dpm_info structure
@@ -1283,7 +1401,6 @@ struct atom_smc_dpm_info_v4_1
1283 uint32_t boardreserved[10]; 1401 uint32_t boardreserved[10];
1284}; 1402};
1285 1403
1286
1287/* 1404/*
1288 *************************************************************************** 1405 ***************************************************************************
1289 Data Table asic_profiling_info structure 1406 Data Table asic_profiling_info structure
@@ -1864,6 +1981,55 @@ enum atom_smu9_syspll0_clock_id
1864 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK 1981 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
1865}; 1982};
1866 1983
1984enum atom_smu11_syspll_id {
1985 SMU11_SYSPLL0_ID = 0,
1986 SMU11_SYSPLL1_0_ID = 1,
1987 SMU11_SYSPLL1_1_ID = 2,
1988 SMU11_SYSPLL1_2_ID = 3,
1989 SMU11_SYSPLL2_ID = 4,
1990 SMU11_SYSPLL3_0_ID = 5,
1991 SMU11_SYSPLL3_1_ID = 6,
1992};
1993
1994
1995enum atom_smu11_syspll0_clock_id {
1996 SMU11_SYSPLL0_SOCCLK_ID = 0, // SOCCLK
1997 SMU11_SYSPLL0_MP0CLK_ID = 1, // MP0CLK
1998 SMU11_SYSPLL0_DCLK_ID = 2, // DCLK
1999 SMU11_SYSPLL0_VCLK_ID = 3, // VCLK
2000 SMU11_SYSPLL0_ECLK_ID = 4, // ECLK
2001 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
2002};
2003
2004
2005enum atom_smu11_syspll1_0_clock_id {
2006 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
2007};
2008
2009enum atom_smu11_syspll1_1_clock_id {
2010 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
2011};
2012
2013enum atom_smu11_syspll1_2_clock_id {
2014 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
2015};
2016
2017enum atom_smu11_syspll2_clock_id {
2018 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
2019};
2020
2021enum atom_smu11_syspll3_0_clock_id {
2022 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
2023 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK
2024 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK
2025};
2026
2027enum atom_smu11_syspll3_1_clock_id {
2028 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
2029 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK
2030 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
2031};
2032
1867struct atom_get_smu_clock_info_output_parameters_v3_1 2033struct atom_get_smu_clock_info_output_parameters_v3_1
1868{ 2034{
1869 union { 2035 union {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 26fbeafc3c96..18b5b2ff47fe 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -79,12 +79,13 @@
79#define PCIE_BUS_CLK 10000 79#define PCIE_BUS_CLK 10000
80#define TCLK (PCIE_BUS_CLK / 10) 80#define TCLK (PCIE_BUS_CLK / 10)
81 81
82static const struct profile_mode_setting smu7_profiling[5] = 82static const struct profile_mode_setting smu7_profiling[6] =
83 {{1, 0, 100, 30, 1, 0, 100, 10}, 83 {{1, 0, 100, 30, 1, 0, 100, 10},
84 {1, 10, 0, 30, 0, 0, 0, 0}, 84 {1, 10, 0, 30, 0, 0, 0, 0},
85 {0, 0, 0, 0, 1, 10, 16, 31}, 85 {0, 0, 0, 0, 1, 10, 16, 31},
86 {1, 0, 11, 50, 1, 0, 100, 10}, 86 {1, 0, 11, 50, 1, 0, 100, 10},
87 {1, 0, 5, 30, 0, 0, 0, 0}, 87 {1, 0, 5, 30, 0, 0, 0, 0},
88 {0, 0, 0, 0, 0, 0, 0, 0},
88 }; 89 };
89 90
90/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */ 91/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
@@ -4864,6 +4865,17 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
4864 len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting); 4865 len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting);
4865 4866
4866 for (i = 0; i < len; i++) { 4867 for (i = 0; i < len; i++) {
4868 if (i == hwmgr->power_profile_mode) {
4869 size += sprintf(buf + size, "%3d %14s %s: %8d %16d %16d %16d %16d %16d\n",
4870 i, profile_name[i], "*",
4871 data->current_profile_setting.sclk_up_hyst,
4872 data->current_profile_setting.sclk_down_hyst,
4873 data->current_profile_setting.sclk_activity,
4874 data->current_profile_setting.mclk_up_hyst,
4875 data->current_profile_setting.mclk_down_hyst,
4876 data->current_profile_setting.mclk_activity);
4877 continue;
4878 }
4867 if (smu7_profiling[i].bupdate_sclk) 4879 if (smu7_profiling[i].bupdate_sclk)
4868 size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ", 4880 size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ",
4869 i, profile_name[i], smu7_profiling[i].sclk_up_hyst, 4881 i, profile_name[i], smu7_profiling[i].sclk_up_hyst,
@@ -4883,24 +4895,6 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
4883 "-", "-", "-"); 4895 "-", "-", "-");
4884 } 4896 }
4885 4897
4886 size += sprintf(buf + size, "%3d %16s: %8d %16d %16d %16d %16d %16d\n",
4887 i, profile_name[i],
4888 data->custom_profile_setting.sclk_up_hyst,
4889 data->custom_profile_setting.sclk_down_hyst,
4890 data->custom_profile_setting.sclk_activity,
4891 data->custom_profile_setting.mclk_up_hyst,
4892 data->custom_profile_setting.mclk_down_hyst,
4893 data->custom_profile_setting.mclk_activity);
4894
4895 size += sprintf(buf + size, "%3s %16s: %8d %16d %16d %16d %16d %16d\n",
4896 "*", "CURRENT",
4897 data->current_profile_setting.sclk_up_hyst,
4898 data->current_profile_setting.sclk_down_hyst,
4899 data->current_profile_setting.sclk_activity,
4900 data->current_profile_setting.mclk_up_hyst,
4901 data->current_profile_setting.mclk_down_hyst,
4902 data->current_profile_setting.mclk_activity);
4903
4904 return size; 4898 return size;
4905} 4899}
4906 4900
@@ -4939,16 +4933,16 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint
4939 if (size < 8) 4933 if (size < 8)
4940 return -EINVAL; 4934 return -EINVAL;
4941 4935
4942 data->custom_profile_setting.bupdate_sclk = input[0]; 4936 tmp.bupdate_sclk = input[0];
4943 data->custom_profile_setting.sclk_up_hyst = input[1]; 4937 tmp.sclk_up_hyst = input[1];
4944 data->custom_profile_setting.sclk_down_hyst = input[2]; 4938 tmp.sclk_down_hyst = input[2];
4945 data->custom_profile_setting.sclk_activity = input[3]; 4939 tmp.sclk_activity = input[3];
4946 data->custom_profile_setting.bupdate_mclk = input[4]; 4940 tmp.bupdate_mclk = input[4];
4947 data->custom_profile_setting.mclk_up_hyst = input[5]; 4941 tmp.mclk_up_hyst = input[5];
4948 data->custom_profile_setting.mclk_down_hyst = input[6]; 4942 tmp.mclk_down_hyst = input[6];
4949 data->custom_profile_setting.mclk_activity = input[7]; 4943 tmp.mclk_activity = input[7];
4950 if (!smum_update_dpm_settings(hwmgr, &data->custom_profile_setting)) { 4944 if (!smum_update_dpm_settings(hwmgr, &tmp)) {
4951 memcpy(&data->current_profile_setting, &data->custom_profile_setting, sizeof(struct profile_mode_setting)); 4945 memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting));
4952 hwmgr->power_profile_mode = mode; 4946 hwmgr->power_profile_mode = mode;
4953 } 4947 }
4954 break; 4948 break;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index f40179c9ca97..b8d0bb378595 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -325,7 +325,6 @@ struct smu7_hwmgr {
325 uint16_t mem_latency_high; 325 uint16_t mem_latency_high;
326 uint16_t mem_latency_low; 326 uint16_t mem_latency_low;
327 uint32_t vr_config; 327 uint32_t vr_config;
328 struct profile_mode_setting custom_profile_setting;
329 struct profile_mode_setting current_profile_setting; 328 struct profile_mode_setting current_profile_setting;
330}; 329};
331 330
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index f0481b7b60c5..06c94e3a5f15 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -910,7 +910,8 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags,
910 while (npages >= HPAGE_PMD_NR) { 910 while (npages >= HPAGE_PMD_NR) {
911 gfp_t huge_flags = gfp_flags; 911 gfp_t huge_flags = gfp_flags;
912 912
913 huge_flags |= GFP_TRANSHUGE; 913 huge_flags |= GFP_TRANSHUGE_LIGHT | __GFP_NORETRY |
914 __GFP_KSWAPD_RECLAIM;
914 huge_flags &= ~__GFP_MOVABLE; 915 huge_flags &= ~__GFP_MOVABLE;
915 huge_flags &= ~__GFP_COMP; 916 huge_flags &= ~__GFP_COMP;
916 p = alloc_pages(huge_flags, HPAGE_PMD_ORDER); 917 p = alloc_pages(huge_flags, HPAGE_PMD_ORDER);
@@ -1027,11 +1028,15 @@ int ttm_page_alloc_init(struct ttm_mem_global *glob, unsigned max_pages)
1027 GFP_USER | GFP_DMA32, "uc dma", 0); 1028 GFP_USER | GFP_DMA32, "uc dma", 0);
1028 1029
1029 ttm_page_pool_init_locked(&_manager->wc_pool_huge, 1030 ttm_page_pool_init_locked(&_manager->wc_pool_huge,
1030 GFP_TRANSHUGE & ~(__GFP_MOVABLE | __GFP_COMP), 1031 (GFP_TRANSHUGE_LIGHT | __GFP_NORETRY |
1032 __GFP_KSWAPD_RECLAIM) &
1033 ~(__GFP_MOVABLE | __GFP_COMP),
1031 "wc huge", order); 1034 "wc huge", order);
1032 1035
1033 ttm_page_pool_init_locked(&_manager->uc_pool_huge, 1036 ttm_page_pool_init_locked(&_manager->uc_pool_huge,
1034 GFP_TRANSHUGE & ~(__GFP_MOVABLE | __GFP_COMP) 1037 (GFP_TRANSHUGE_LIGHT | __GFP_NORETRY |
1038 __GFP_KSWAPD_RECLAIM) &
1039 ~(__GFP_MOVABLE | __GFP_COMP)
1035 , "uc huge", order); 1040 , "uc huge", order);
1036 1041
1037 _manager->options.max_size = max_pages; 1042 _manager->options.max_size = max_pages;
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
index 8a25d1974385..f63d99c302e4 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
@@ -910,7 +910,8 @@ static gfp_t ttm_dma_pool_gfp_flags(struct ttm_dma_tt *ttm_dma, bool huge)
910 gfp_flags |= __GFP_ZERO; 910 gfp_flags |= __GFP_ZERO;
911 911
912 if (huge) { 912 if (huge) {
913 gfp_flags |= GFP_TRANSHUGE; 913 gfp_flags |= GFP_TRANSHUGE_LIGHT | __GFP_NORETRY |
914 __GFP_KSWAPD_RECLAIM;
914 gfp_flags &= ~__GFP_MOVABLE; 915 gfp_flags &= ~__GFP_MOVABLE;
915 gfp_flags &= ~__GFP_COMP; 916 gfp_flags &= ~__GFP_COMP;
916 } 917 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-29 02:48:02 -0500