1 files changed, 8 insertions, 0 deletions

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 2e9f84fdd9ce..4ce0aa5e8248 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -31,6 +31,7 @@
 #define PORT_LINK_MODE_1_LANES          (0x1 << 16)
 #define PORT_LINK_MODE_2_LANES          (0x3 << 16)
 #define PORT_LINK_MODE_4_LANES          (0x7 << 16)
+#define PORT_LINK_MODE_8_LANES          (0xf << 16)
 
 #define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
 #define PORT_LOGIC_SPEED_CHANGE         (0x1 << 17)
@@ -38,6 +39,7 @@
 #define PORT_LOGIC_LINK_WIDTH_1_LANES   (0x1 << 8)
 #define PORT_LOGIC_LINK_WIDTH_2_LANES   (0x2 << 8)
 #define PORT_LOGIC_LINK_WIDTH_4_LANES   (0x4 << 8)
+#define PORT_LOGIC_LINK_WIDTH_8_LANES   (0x8 << 8)
 
 #define PCIE_MSI_ADDR_LO                0x820
 #define PCIE_MSI_ADDR_HI                0x824
@@ -778,6 +780,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
         case 4:
                 val |= PORT_LINK_MODE_4_LANES;
                 break;
+        case 8:
+                val |= PORT_LINK_MODE_8_LANES;
+                break;
         }
         dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
 
@@ -794,6 +799,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
         case 4:
                 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
                 break;
+        case 8:
+                val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
+                break;
         }
         dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);