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-rw-r--r--arch/arm/Kconfig.debug7
-rw-r--r--arch/arm/mach-shmobile/Kconfig7
-rw-r--r--arch/arm/mach-shmobile/Makefile5
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c620
-rw-r--r--arch/arm/mach-shmobile/common.h1
-rw-r--r--arch/arm/mach-shmobile/entry-intc.S54
-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c672
-rw-r--r--arch/arm/mach-shmobile/pm-sh7372.c549
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c1016
-rw-r--r--arch/arm/mach-shmobile/sh7372.h84
-rw-r--r--arch/arm/mach-shmobile/sleep-sh7372.S98
11 files changed, 3 insertions, 3110 deletions
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 970de7518341..65634e01293d 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -821,12 +821,11 @@ choice
821 via SCIF2 on Renesas R-Car E2 (R8A7794). 821 via SCIF2 on Renesas R-Car E2 (R8A7794).
822 822
823 config DEBUG_RMOBILE_SCIFA0 823 config DEBUG_RMOBILE_SCIFA0
824 bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4/SH7372" 824 bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4"
825 depends on ARCH_R8A73A4 || ARCH_SH7372 825 depends on ARCH_R8A73A4
826 help 826 help
827 Say Y here if you want kernel low-level debugging support 827 Say Y here if you want kernel low-level debugging support
828 via SCIFA0 on Renesas R-Mobile APE6 (R8A73A4) or SH-Mobile 828 via SCIFA0 on Renesas R-Mobile APE6 (R8A73A4).
829 AP4 (SH7372).
830 829
831 config DEBUG_RMOBILE_SCIFA1 830 config DEBUG_RMOBILE_SCIFA1
832 bool "Kernel low-level debugging messages via SCIFA1 on R8A7740" 831 bool "Kernel low-level debugging messages via SCIFA1 on R8A7740"
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 0a0b7d6f1c09..a4ef122f85a0 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -92,13 +92,6 @@ if ARCH_SHMOBILE_LEGACY
92 92
93comment "Renesas ARM SoCs System Type" 93comment "Renesas ARM SoCs System Type"
94 94
95config ARCH_SH7372
96 bool "SH-Mobile AP4 (SH7372)"
97 select ARCH_RMOBILE
98 select ARCH_WANT_OPTIONAL_GPIOLIB
99 select ARM_CPU_SUSPEND if PM || CPU_IDLE
100 select SH_INTC
101
102config ARCH_SH73A0 95config ARCH_SH73A0
103 bool "SH-Mobile AG5 (R8A73A00)" 96 bool "SH-Mobile AG5 (R8A73A00)"
104 select ARCH_RMOBILE 97 select ARCH_RMOBILE
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 5ae3328c4761..beb3f1491e68 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -6,7 +6,6 @@
6obj-y := timer.o console.o 6obj-y := timer.o console.o
7 7
8# CPU objects 8# CPU objects
9obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o intc-sh7372.o pm-sh7372.o
10obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o intc-sh73a0.o pm-sh73a0.o 9obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o intc-sh73a0.o pm-sh73a0.o
11obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o 10obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o
12obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o pm-r8a7740.o 11obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o pm-r8a7740.o
@@ -21,7 +20,6 @@ obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
21# Clock objects 20# Clock objects
22ifndef CONFIG_COMMON_CLK 21ifndef CONFIG_COMMON_CLK
23obj-y += clock.o 22obj-y += clock.o
24obj-$(CONFIG_ARCH_SH7372) += clock-sh7372.o
25obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o 23obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o
26obj-$(CONFIG_ARCH_R8A73A4) += clock-r8a73a4.o 24obj-$(CONFIG_ARCH_R8A73A4) += clock-r8a73a4.o
27obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o 25obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o
@@ -51,9 +49,6 @@ obj-$(CONFIG_CPU_FREQ) += cpufreq.o
51obj-$(CONFIG_PM_RCAR) += pm-rcar.o 49obj-$(CONFIG_PM_RCAR) += pm-rcar.o
52obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o 50obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o
53 51
54# special sh7372 handling for IRQ objects and low level sleep code
55obj-$(CONFIG_ARCH_SH7372) += entry-intc.o sleep-sh7372.o
56
57# Board objects 52# Board objects
58ifdef CONFIG_ARCH_SHMOBILE_MULTI 53ifdef CONFIG_ARCH_SHMOBILE_MULTI
59obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o 54obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
deleted file mode 100644
index 3bc92f46060e..000000000000
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ /dev/null
@@ -1,620 +0,0 @@
1/*
2 * SH7372 clock framework support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/init.h>
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/sh_clk.h>
19#include <linux/clkdev.h>
20#include "clock.h"
21#include "common.h"
22
23/* SH7372 registers */
24#define FRQCRA IOMEM(0xe6150000)
25#define FRQCRB IOMEM(0xe6150004)
26#define FRQCRC IOMEM(0xe61500e0)
27#define FRQCRD IOMEM(0xe61500e4)
28#define VCLKCR1 IOMEM(0xe6150008)
29#define VCLKCR2 IOMEM(0xe615000c)
30#define VCLKCR3 IOMEM(0xe615001c)
31#define FMSICKCR IOMEM(0xe6150010)
32#define FMSOCKCR IOMEM(0xe6150014)
33#define FSIACKCR IOMEM(0xe6150018)
34#define FSIBCKCR IOMEM(0xe6150090)
35#define SUBCKCR IOMEM(0xe6150080)
36#define SPUCKCR IOMEM(0xe6150084)
37#define VOUCKCR IOMEM(0xe6150088)
38#define HDMICKCR IOMEM(0xe6150094)
39#define DSITCKCR IOMEM(0xe6150060)
40#define DSI0PCKCR IOMEM(0xe6150064)
41#define DSI1PCKCR IOMEM(0xe6150098)
42#define PLLC01CR IOMEM(0xe6150028)
43#define PLLC2CR IOMEM(0xe615002c)
44#define RMSTPCR0 IOMEM(0xe6150110)
45#define RMSTPCR1 IOMEM(0xe6150114)
46#define RMSTPCR2 IOMEM(0xe6150118)
47#define RMSTPCR3 IOMEM(0xe615011c)
48#define RMSTPCR4 IOMEM(0xe6150120)
49#define SMSTPCR0 IOMEM(0xe6150130)
50#define SMSTPCR1 IOMEM(0xe6150134)
51#define SMSTPCR2 IOMEM(0xe6150138)
52#define SMSTPCR3 IOMEM(0xe615013c)
53#define SMSTPCR4 IOMEM(0xe6150140)
54
55#define FSIDIVA 0xFE1F8000
56#define FSIDIVB 0xFE1F8008
57
58/* Platforms must set frequency on their DV_CLKI pin */
59struct clk sh7372_dv_clki_clk = {
60};
61
62/* Fixed 32 KHz root clock from EXTALR pin */
63static struct clk r_clk = {
64 .rate = 32768,
65};
66
67/*
68 * 26MHz default rate for the EXTAL1 root input clock.
69 * If needed, reset this with clk_set_rate() from the platform code.
70 */
71struct clk sh7372_extal1_clk = {
72 .rate = 26000000,
73};
74
75/*
76 * 48MHz default rate for the EXTAL2 root input clock.
77 * If needed, reset this with clk_set_rate() from the platform code.
78 */
79struct clk sh7372_extal2_clk = {
80 .rate = 48000000,
81};
82
83SH_CLK_RATIO(div2, 1, 2);
84
85SH_FIXED_RATIO_CLKg(sh7372_dv_clki_div2_clk, sh7372_dv_clki_clk, div2);
86SH_FIXED_RATIO_CLK(extal1_div2_clk, sh7372_extal1_clk, div2);
87SH_FIXED_RATIO_CLK(extal2_div2_clk, sh7372_extal2_clk, div2);
88SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_div2_clk, div2);
89
90/* PLLC0 and PLLC1 */
91static unsigned long pllc01_recalc(struct clk *clk)
92{
93 unsigned long mult = 1;
94
95 if (__raw_readl(PLLC01CR) & (1 << 14))
96 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2;
97
98 return clk->parent->rate * mult;
99}
100
101static struct sh_clk_ops pllc01_clk_ops = {
102 .recalc = pllc01_recalc,
103};
104
105static struct clk pllc0_clk = {
106 .ops = &pllc01_clk_ops,
107 .flags = CLK_ENABLE_ON_INIT,
108 .parent = &extal1_div2_clk,
109 .enable_reg = (void __iomem *)FRQCRC,
110};
111
112static struct clk pllc1_clk = {
113 .ops = &pllc01_clk_ops,
114 .flags = CLK_ENABLE_ON_INIT,
115 .parent = &extal1_div2_clk,
116 .enable_reg = (void __iomem *)FRQCRA,
117};
118
119/* Divide PLLC1 by two */
120SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
121
122/* PLLC2 */
123
124/* Indices are important - they are the actual src selecting values */
125static struct clk *pllc2_parent[] = {
126 [0] = &extal1_div2_clk,
127 [1] = &extal2_div2_clk,
128 [2] = &sh7372_dv_clki_div2_clk,
129};
130
131/* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */
132static struct cpufreq_frequency_table pllc2_freq_table[29];
133
134static void pllc2_table_rebuild(struct clk *clk)
135{
136 int i;
137
138 /* Initialise PLLC2 frequency table */
139 for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) {
140 pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2;
141 pllc2_freq_table[i].driver_data = i;
142 }
143
144 /* This is a special entry - switching PLL off makes it a repeater */
145 pllc2_freq_table[i].frequency = clk->parent->rate;
146 pllc2_freq_table[i].driver_data = i;
147
148 pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END;
149 pllc2_freq_table[i].driver_data = i;
150}
151
152static unsigned long pllc2_recalc(struct clk *clk)
153{
154 unsigned long mult = 1;
155
156 pllc2_table_rebuild(clk);
157
158 /*
159 * If the PLL is off, mult == 1, clk->rate will be updated in
160 * pllc2_enable().
161 */
162 if (__raw_readl(PLLC2CR) & (1 << 31))
163 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
164
165 return clk->parent->rate * mult;
166}
167
168static long pllc2_round_rate(struct clk *clk, unsigned long rate)
169{
170 return clk_rate_table_round(clk, clk->freq_table, rate);
171}
172
173static int pllc2_enable(struct clk *clk)
174{
175 int i;
176
177 __raw_writel(__raw_readl(PLLC2CR) | 0x80000000, PLLC2CR);
178
179 for (i = 0; i < 100; i++)
180 if (__raw_readl(PLLC2CR) & 0x80000000) {
181 clk->rate = pllc2_recalc(clk);
182 return 0;
183 }
184
185 pr_err("%s(): timeout!\n", __func__);
186
187 return -ETIMEDOUT;
188}
189
190static void pllc2_disable(struct clk *clk)
191{
192 __raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR);
193}
194
195static int pllc2_set_rate(struct clk *clk, unsigned long rate)
196{
197 unsigned long value;
198 int idx;
199
200 idx = clk_rate_table_find(clk, clk->freq_table, rate);
201 if (idx < 0)
202 return idx;
203
204 if (rate == clk->parent->rate)
205 return -EINVAL;
206
207 value = __raw_readl(PLLC2CR) & ~(0x3f << 24);
208
209 __raw_writel(value | ((idx + 19) << 24), PLLC2CR);
210
211 clk->rate = clk->freq_table[idx].frequency;
212
213 return 0;
214}
215
216static int pllc2_set_parent(struct clk *clk, struct clk *parent)
217{
218 u32 value;
219 int ret, i;
220
221 if (!clk->parent_table || !clk->parent_num)
222 return -EINVAL;
223
224 /* Search the parent */
225 for (i = 0; i < clk->parent_num; i++)
226 if (clk->parent_table[i] == parent)
227 break;
228
229 if (i == clk->parent_num)
230 return -ENODEV;
231
232 ret = clk_reparent(clk, parent);
233 if (ret < 0)
234 return ret;
235
236 value = __raw_readl(PLLC2CR) & ~(3 << 6);
237
238 __raw_writel(value | (i << 6), PLLC2CR);
239
240 /* Rebiuld the frequency table */
241 pllc2_table_rebuild(clk);
242
243 return 0;
244}
245
246static struct sh_clk_ops pllc2_clk_ops = {
247 .recalc = pllc2_recalc,
248 .round_rate = pllc2_round_rate,
249 .set_rate = pllc2_set_rate,
250 .enable = pllc2_enable,
251 .disable = pllc2_disable,
252 .set_parent = pllc2_set_parent,
253};
254
255struct clk sh7372_pllc2_clk = {
256 .ops = &pllc2_clk_ops,
257 .parent = &extal1_div2_clk,
258 .freq_table = pllc2_freq_table,
259 .nr_freqs = ARRAY_SIZE(pllc2_freq_table) - 1,
260 .parent_table = pllc2_parent,
261 .parent_num = ARRAY_SIZE(pllc2_parent),
262};
263
264/* External input clock (pin name: FSIACK/FSIBCK ) */
265static struct clk fsiack_clk = {
266};
267
268static struct clk fsibck_clk = {
269};
270
271static struct clk *main_clks[] = {
272 &sh7372_dv_clki_clk,
273 &r_clk,
274 &sh7372_extal1_clk,
275 &sh7372_extal2_clk,
276 &sh7372_dv_clki_div2_clk,
277 &extal1_div2_clk,
278 &extal2_div2_clk,
279 &extal2_div4_clk,
280 &pllc0_clk,
281 &pllc1_clk,
282 &pllc1_div2_clk,
283 &sh7372_pllc2_clk,
284 &fsiack_clk,
285 &fsibck_clk,
286};
287
288static void div4_kick(struct clk *clk)
289{
290 unsigned long value;
291
292 /* set KICK bit in FRQCRB to update hardware setting */
293 value = __raw_readl(FRQCRB);
294 value |= (1 << 31);
295 __raw_writel(value, FRQCRB);
296}
297
298static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
299 24, 32, 36, 48, 0, 72, 96, 0 };
300
301static struct clk_div_mult_table div4_div_mult_table = {
302 .divisors = divisors,
303 .nr_divisors = ARRAY_SIZE(divisors),
304};
305
306static struct clk_div4_table div4_table = {
307 .div_mult_table = &div4_div_mult_table,
308 .kick = div4_kick,
309};
310
311enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
312 DIV4_ZX, DIV4_HP,
313 DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
314 DIV4_DDRP, DIV4_NR };
315
316#define DIV4(_reg, _bit, _mask, _flags) \
317 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
318
319static struct clk div4_clks[DIV4_NR] = {
320 [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
321 [DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
322 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
323 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
324 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
325 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
326 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
327 [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
328 [DIV4_S] = DIV4(FRQCRC, 12, 0x6fff, 0),
329 [DIV4_ZB] = DIV4(FRQCRC, 8, 0x6fff, 0),
330 [DIV4_ZB3] = DIV4(FRQCRC, 4, 0x6fff, 0),
331 [DIV4_CP] = DIV4(FRQCRC, 0, 0x6fff, 0),
332 [DIV4_DDRP] = DIV4(FRQCRD, 0, 0x677c, 0),
333};
334
335enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
336 DIV6_SUB, DIV6_SPU,
337 DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
338 DIV6_NR };
339
340static struct clk div6_clks[DIV6_NR] = {
341 [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
342 [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
343 [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
344 [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
345 [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
346 [DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
347 [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
348 [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
349 [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
350 [DIV6_DSI0P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI0PCKCR, 0),
351 [DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
352};
353
354enum { DIV6_HDMI, DIV6_FSIA, DIV6_FSIB, DIV6_REPARENT_NR };
355
356/* Indices are important - they are the actual src selecting values */
357static struct clk *hdmi_parent[] = {
358 [0] = &pllc1_div2_clk,
359 [1] = &sh7372_pllc2_clk,
360 [2] = &sh7372_dv_clki_clk,
361 [3] = NULL, /* pllc2_div4 not implemented yet */
362};
363
364static struct clk *fsiackcr_parent[] = {
365 [0] = &pllc1_div2_clk,
366 [1] = &sh7372_pllc2_clk,
367 [2] = &fsiack_clk, /* external input for FSI A */
368 [3] = NULL, /* setting prohibited */
369};
370
371static struct clk *fsibckcr_parent[] = {
372 [0] = &pllc1_div2_clk,
373 [1] = &sh7372_pllc2_clk,
374 [2] = &fsibck_clk, /* external input for FSI B */
375 [3] = NULL, /* setting prohibited */
376};
377
378static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
379 [DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0,
380 hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
381 [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
382 fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
383 [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
384 fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
385};
386
387/* FSI DIV */
388enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
389
390static struct clk fsidivs[] = {
391 [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
392 [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
393};
394
395enum { MSTP001, MSTP000,
396 MSTP131, MSTP130,
397 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
398 MSTP118, MSTP117, MSTP116, MSTP113,
399 MSTP106, MSTP101, MSTP100,
400 MSTP223,
401 MSTP218, MSTP217, MSTP216, MSTP214, MSTP208, MSTP207,
402 MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
403 MSTP328, MSTP323, MSTP322, MSTP315, MSTP314, MSTP313, MSTP312,
404 MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP407, MSTP406,
405 MSTP405, MSTP404, MSTP403, MSTP400,
406 MSTP_NR };
407
408#define MSTP(_parent, _reg, _bit, _flags) \
409 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
410
411static struct clk mstp_clks[MSTP_NR] = {
412 [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
413 [MSTP000] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 0, 0), /* MSIOF0 */
414 [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
415 [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
416 [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
417 [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
418 [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */
419 [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */
420 [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
421 [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
422 [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
423 [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
424 [MSTP113] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 13, 0), /* MERAM */
425 [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
426 [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
427 [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
428 [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
429 [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
430 [MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
431 [MSTP216] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
432 [MSTP214] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
433 [MSTP208] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 8, 0), /* MSIOF1 */
434 [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
435 [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
436 [MSTP205] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 5, 0), /* MSIOF2 */
437 [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
438 [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
439 [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
440 [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
441 [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
442 [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
443 [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
444 [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
445 [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL*/
446 [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
447 [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
448 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
449 [MSTP423] = MSTP(&div4_clks[DIV4_B], SMSTPCR4, 23, 0), /* DSITX1 */
450 [MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
451 [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
452 [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
453 [MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
454 [MSTP407] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-DMAC1 */
455 [MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
456 [MSTP405] = MSTP(&r_clk, SMSTPCR4, 5, 0), /* CMT4 */
457 [MSTP404] = MSTP(&r_clk, SMSTPCR4, 4, 0), /* CMT3 */
458 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
459 [MSTP400] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* CMT2 */
460};
461
462static struct clk_lookup lookups[] = {
463 /* main clocks */
464 CLKDEV_CON_ID("dv_clki_div2_clk", &sh7372_dv_clki_div2_clk),
465 CLKDEV_CON_ID("r_clk", &r_clk),
466 CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
467 CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
468 CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk),
469 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
470 CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
471 CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
472 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
473 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
474 CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
475 CLKDEV_CON_ID("fsiack", &fsiack_clk),
476 CLKDEV_CON_ID("fsibck", &fsibck_clk),
477
478 /* DIV4 clocks */
479 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
480 CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
481 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
482 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
483 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
484 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
485 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
486 CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
487 CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
488 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
489 CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
490 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
491 CLKDEV_CON_ID("ddrp_clk", &div4_clks[DIV4_DDRP]),
492
493 /* DIV6 clocks */
494 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
495 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
496 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
497 CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
498 CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
499 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
500 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
501 CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
502 CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
503
504 /* MSTP32 clocks */
505 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
506 CLKDEV_DEV_ID("fff30000.i2c", &mstp_clks[MSTP001]), /* IIC2 */
507 CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[MSTP000]), /* MSIOF0 */
508 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
509 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
510 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
511 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
512 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */
513 CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
514 CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */
515 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
516 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
517 CLKDEV_DEV_ID("fff20000.i2c", &mstp_clks[MSTP116]), /* IIC0 */
518 CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[MSTP113]), /* MERAM */
519 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
520 CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
521 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
522 CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
523 CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
524 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* DMAC1 */
525 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* DMAC2 */
526 CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), /* DMAC3 */
527 CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), /* USB-DMAC0 */
528 CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[MSTP208]), /* MSIOF1 */
529 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
530 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
531 CLKDEV_DEV_ID("spi_sh_msiof.2", &mstp_clks[MSTP205]), /* MSIOF2 */
532 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
533 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
534 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
535 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
536 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
537 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
538 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
539 CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), /* IIC1 */
540 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
541 CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USB0 */
542 CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP322]), /* USB0 */
543 CLKDEV_DEV_ID("sh_flctl.0", &mstp_clks[MSTP315]), /* FLCTL */
544 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
545 CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
546 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
547 CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
548 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
549 CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMC */
550 CLKDEV_DEV_ID("sh-mipi-dsi.1", &mstp_clks[MSTP423]), /* DSITX1 */
551 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
552 CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), /* SDHI2 */
553 CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
554 CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
555 CLKDEV_DEV_ID("e6d20000.i2c", &mstp_clks[MSTP411]), /* IIC3 */
556 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
557 CLKDEV_DEV_ID("e6d30000.i2c", &mstp_clks[MSTP410]), /* IIC4 */
558 CLKDEV_DEV_ID("sh-dma-engine.4", &mstp_clks[MSTP407]), /* USB-DMAC1 */
559 CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
560 CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
561 CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
562 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
563
564 /* ICK */
565 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
566 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
567 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
568 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
569 CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1",
570 &div6_reparent_clks[DIV6_HDMI]),
571 CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
572 CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
573 CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
574 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]), /* TMU0 */
575 CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]),
576 CLKDEV_ICK_ID("fck", "sh-cmt-32-fast.4", &mstp_clks[MSTP405]), /* CMT4 */
577 CLKDEV_ICK_ID("fck", "sh-cmt-32-fast.3", &mstp_clks[MSTP404]), /* CMT3 */
578 CLKDEV_ICK_ID("fck", "sh-cmt-32-fast.2", &mstp_clks[MSTP400]), /* CMT2 */
579 CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
580 CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
581 CLKDEV_ICK_ID("xcka", "sh_fsi2", &fsiack_clk),
582 CLKDEV_ICK_ID("xckb", "sh_fsi2", &fsibck_clk),
583};
584
585void __init sh7372_clock_init(void)
586{
587 int k, ret = 0;
588
589 /* make sure MSTP bits on the RT/SH4AL-DSP side are off */
590 __raw_writel(0xe4ef8087, RMSTPCR0);
591 __raw_writel(0xffffffff, RMSTPCR1);
592 __raw_writel(0x37c7f7ff, RMSTPCR2);
593 __raw_writel(0xffffffff, RMSTPCR3);
594 __raw_writel(0xffe0fffd, RMSTPCR4);
595
596 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
597 ret = clk_register(main_clks[k]);
598
599 if (!ret)
600 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
601
602 if (!ret)
603 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
604
605 if (!ret)
606 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
607
608 if (!ret)
609 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
610
611 if (!ret)
612 ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
613
614 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
615
616 if (!ret)
617 shmobile_clk_init();
618 else
619 panic("failed to setup sh7372 clocks\n");
620}
diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index 309025efd4cf..8faf6e040d78 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -21,7 +21,6 @@ extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
21extern int shmobile_smp_scu_cpu_kill(unsigned int cpu); 21extern int shmobile_smp_scu_cpu_kill(unsigned int cpu);
22struct clk; 22struct clk;
23extern int shmobile_clk_init(void); 23extern int shmobile_clk_init(void);
24extern void shmobile_handle_irq_intc(struct pt_regs *);
25extern struct platform_suspend_ops shmobile_suspend_ops; 24extern struct platform_suspend_ops shmobile_suspend_ops;
26struct cpuidle_driver; 25struct cpuidle_driver;
27extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); 26extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
diff --git a/arch/arm/mach-shmobile/entry-intc.S b/arch/arm/mach-shmobile/entry-intc.S
deleted file mode 100644
index 1a1c00ca39a2..000000000000
--- a/arch/arm/mach-shmobile/entry-intc.S
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * ARM Interrupt demux handler using INTC
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <asm/entry-macro-multi.S>
13
14#define INTCA_BASE 0xe6980000
15#define INTFLGA_OFFS 0x00000018 /* accept pending interrupt */
16#define INTEVTA_OFFS 0x00000020 /* vector number of accepted interrupt */
17#define INTLVLA_OFFS 0x00000030 /* priority level of accepted interrupt */
18#define INTLVLB_OFFS 0x00000034 /* previous priority level */
19
20 .macro get_irqnr_preamble, base, tmp
21 ldr \base, =INTCA_BASE
22 .endm
23
24 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
25 /* The single INTFLGA read access below results in the following:
26 *
27 * 1. INTLVLB is updated with old priority value from INTLVLA
28 * 2. Highest priority interrupt is accepted
29 * 3. INTLVLA is updated to contain priority of accepted interrupt
30 * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
31 */
32 ldr \irqnr, [\base, #INTFLGA_OFFS]
33
34 /* Restore INTLVLA with the value saved in INTLVLB.
35 * This is required to support interrupt priorities properly.
36 */
37 ldrb \tmp, [\base, #INTLVLB_OFFS]
38 strb \tmp, [\base, #INTLVLA_OFFS]
39
40 /* Handle invalid vector number case */
41 cmp \irqnr, #0
42 beq 1000f
43
44 /* Convert vector to irq number, same as the evt2irq() macro */
45 lsr \irqnr, \irqnr, #0x5
46 subs \irqnr, \irqnr, #16
47
481000:
49 .endm
50
51 .macro test_for_ipi, irqnr, irqstat, base, tmp
52 .endm
53
54 arch_irq_handler shmobile_handle_irq_intc
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
deleted file mode 100644
index 1ccf49cb485f..000000000000
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ /dev/null
@@ -1,672 +0,0 @@
1/*
2 * sh7372 processor support - INTC hardware block
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/module.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21#include <asm/mach-types.h>
22#include <asm/mach/arch.h>
23#include "intc.h"
24#include "irqs.h"
25
26enum {
27 UNUSED_INTCA = 0,
28
29 /* interrupt sources INTCA */
30 DIRC,
31 CRYPT_STD,
32 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
33 AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX,
34 MFI_MFIM, MFI_MFIS,
35 BBIF1, BBIF2,
36 USBHSDMAC0_USHDMI,
37 _3DG_SGX540,
38 CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
39 KEYSC_KEY,
40 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
41 MSIOF2, MSIOF1,
42 SCIFA4, SCIFA5, SCIFB,
43 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
44 SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3,
45 SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2,
46 IRREM,
47 IRDA,
48 TPU0,
49 TTI20,
50 DDM,
51 SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3,
52 RWDT0,
53 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
54 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
55 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
56 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
57 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
58 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
59 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
60 HDMI,
61 SPU2_SPU0, SPU2_SPU1,
62 FSI, FMSI,
63 MIPI_HSI,
64 IPMMU_IPMMUD,
65 CEC_1, CEC_2,
66 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ,
67 MFIS2,
68 CPORTR2S,
69 CMT14, CMT15,
70 MMC_MMC_ERR, MMC_MMC_NOR,
71 IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
72 IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3,
73 USB0_USB0I1, USB0_USB0I0,
74 USB1_USB1I1, USB1_USB1I0,
75 USBHSDMAC1_USHDMI,
76
77 /* interrupt groups INTCA */
78 DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
79 AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2
80};
81
82static struct intc_vect intca_vectors[] __initdata = {
83 INTC_VECT(DIRC, 0x0560),
84 INTC_VECT(CRYPT_STD, 0x0700),
85 INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
86 INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
87 INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840),
88 INTC_VECT(AP_ARM_COMMRX, 0x0860),
89 INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
90 INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
91 INTC_VECT(USBHSDMAC0_USHDMI, 0x0a00),
92 INTC_VECT(_3DG_SGX540, 0x0a60),
93 INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
94 INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
95 INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
96 INTC_VECT(KEYSC_KEY, 0x0be0),
97 INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
98 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
99 INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
100 INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
101 INTC_VECT(SCIFB, 0x0d60),
102 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
103 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
104 INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20),
105 INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60),
106 INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0),
107 INTC_VECT(SDHI1_SDHI1I2, 0x0ec0),
108 INTC_VECT(IRREM, 0x0f60),
109 INTC_VECT(IRDA, 0x0480),
110 INTC_VECT(TPU0, 0x04a0),
111 INTC_VECT(TTI20, 0x1100),
112 INTC_VECT(DDM, 0x1140),
113 INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220),
114 INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260),
115 INTC_VECT(RWDT0, 0x1280),
116 INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020),
117 INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060),
118 INTC_VECT(DMAC1_2_DEI4, 0x2080), INTC_VECT(DMAC1_2_DEI5, 0x20a0),
119 INTC_VECT(DMAC1_2_DADERR, 0x20c0),
120 INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
121 INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
122 INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
123 INTC_VECT(DMAC2_2_DADERR, 0x21c0),
124 INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
125 INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
126 INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
127 INTC_VECT(DMAC3_2_DADERR, 0x22c0),
128 INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1320),
129 INTC_VECT(SHWYSTAT_COM, 0x1340),
130 INTC_VECT(HDMI, 0x17e0),
131 INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820),
132 INTC_VECT(FSI, 0x1840),
133 INTC_VECT(FMSI, 0x1860),
134 INTC_VECT(MIPI_HSI, 0x18e0),
135 INTC_VECT(IPMMU_IPMMUD, 0x1920),
136 INTC_VECT(CEC_1, 0x1940), INTC_VECT(CEC_2, 0x1960),
137 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
138 INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0),
139 INTC_VECT(AP_ARM_DMAIRQ, 0x19c0),
140 INTC_VECT(AP_ARM_DMASIRQ, 0x19e0),
141 INTC_VECT(MFIS2, 0x1a00),
142 INTC_VECT(CPORTR2S, 0x1a20),
143 INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60),
144 INTC_VECT(MMC_MMC_ERR, 0x1ac0), INTC_VECT(MMC_MMC_NOR, 0x1ae0),
145 INTC_VECT(IIC4_ALI4, 0x1b00), INTC_VECT(IIC4_TACKI4, 0x1b20),
146 INTC_VECT(IIC4_WAITI4, 0x1b40), INTC_VECT(IIC4_DTEI4, 0x1b60),
147 INTC_VECT(IIC3_ALI3, 0x1b80), INTC_VECT(IIC3_TACKI3, 0x1ba0),
148 INTC_VECT(IIC3_WAITI3, 0x1bc0), INTC_VECT(IIC3_DTEI3, 0x1be0),
149 INTC_VECT(USB0_USB0I1, 0x1c80), INTC_VECT(USB0_USB0I0, 0x1ca0),
150 INTC_VECT(USB1_USB1I1, 0x1cc0), INTC_VECT(USB1_USB1I0, 0x1ce0),
151 INTC_VECT(USBHSDMAC1_USHDMI, 0x1d00),
152};
153
154static struct intc_group intca_groups[] __initdata = {
155 INTC_GROUP(DMAC1_1, DMAC1_1_DEI0,
156 DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
157 INTC_GROUP(DMAC1_2, DMAC1_2_DEI4,
158 DMAC1_2_DEI5, DMAC1_2_DADERR),
159 INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
160 DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
161 INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
162 DMAC2_2_DEI5, DMAC2_2_DADERR),
163 INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
164 DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
165 INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
166 DMAC3_2_DEI5, DMAC3_2_DADERR),
167 INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX),
168 INTC_GROUP(AP_ARM2, AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
169 AP_ARM_DMAIRQ, AP_ARM_DMASIRQ),
170 INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
171 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
172 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
173 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
174 INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1,
175 SDHI0_SDHI0I2, SDHI0_SDHI0I3),
176 INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1,
177 SDHI1_SDHI1I2),
178 INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1,
179 SDHI2_SDHI2I2, SDHI2_SDHI2I3),
180 INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
181};
182
183static struct intc_mask_reg intca_mask_registers[] __initdata = {
184 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
185 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
186 AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
187 { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
188 { 0, CRYPT_STD, DIRC, 0,
189 DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
190 { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
191 { 0, 0, 0, 0,
192 BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
193 { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
194 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
195 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
196 { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
197 { DDM, 0, 0, 0,
198 0, 0, 0, 0 } },
199 { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
200 { KEYSC_KEY, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
201 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
202 { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
203 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
204 0, 0, MSIOF2, 0 } },
205 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
206 { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0,
207 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
208 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
209 { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0,
210 TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
211 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
212 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
213 CMT2, 0, 0, _3DG_SGX540 } },
214 { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
215 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
216 0, 0, 0, 0 } },
217 { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
218 { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
219 0, 0, IRREM, 0 } },
220 { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
221 { 0, 0, TPU0, 0,
222 0, 0, 0, 0 } },
223 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
224 { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0,
225 0, CMT3, 0, RWDT0 } },
226 { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
227 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
228 0, 0, 0, 0 } },
229 { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */
230 { 0, 0, 0, 0,
231 0, 0, 0, HDMI } },
232 { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */
233 { SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
234 0, 0, 0, MIPI_HSI } },
235 { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */
236 { 0, IPMMU_IPMMUD, CEC_1, CEC_2,
237 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
238 AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } },
239 { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */
240 { MFIS2, CPORTR2S, CMT14, CMT15,
241 0, 0, MMC_MMC_ERR, MMC_MMC_NOR } },
242 { 0xe69500a0, 0xe69500e0, 8, /* IMR8A3 / IMCR8A3 */
243 { IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
244 IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3 } },
245 { 0xe69500a4, 0xe69500e4, 8, /* IMR9A3 / IMCR9A3 */
246 { 0, 0, 0, 0,
247 USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } },
248 { 0xe69500a8, 0xe69500e8, 8, /* IMR10A3 / IMCR10A3 */
249 { USBHSDMAC1_USHDMI, 0, 0, 0,
250 0, 0, 0, 0 } },
251};
252
253static struct intc_prio_reg intca_prio_registers[] __initdata = {
254 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } },
255 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
256 { 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD,
257 CMT1_CMT11, AP_ARM1 } },
258 { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0,
259 CMT1_CMT12, 0 } },
260 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFI_MFIS,
261 MFI_MFIM, 0 } },
262 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC1_2,
263 _3DG_SGX540, CMT1_CMT10 } },
264 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
265 SCIFA2, SCIFA3 } },
266 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC0_USHDMI,
267 FLCTL, SDHI0 } },
268 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4,
269 0/* MSU */, IIC1 } },
270 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
271 0/* MSUG */, TTI20 } },
272 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } },
273 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, 0, 0, 0 } },
274 { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
275 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
276 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
277 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
278 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { 0, 0, 0, HDMI } },
279 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
280 { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, 0, 0, MIPI_HSI } },
281 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUD, 0,
282 CEC_1, CEC_2 } },
283 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
284 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
285 CMT14, CMT15 } },
286 { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, 0,
287 MMC_MMC_ERR, MMC_MMC_NOR } },
288 { 0xe6950040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4,
289 IIC4_WAITI4, IIC4_DTEI4 } },
290 { 0xe6950044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3,
291 IIC3_WAITI3, IIC3_DTEI3 } },
292 { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/,
293 0/*TXI*/, 0/*TEI*/} },
294 { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0,
295 USB1_USB1I1, USB1_USB1I0 } },
296 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
297};
298
299static DECLARE_INTC_DESC(intca_desc, "sh7372-intca",
300 intca_vectors, intca_groups,
301 intca_mask_registers, intca_prio_registers,
302 NULL);
303
304INTC_IRQ_PINS_16(intca_irq_pins_lo, 0xe6900000,
305 INTC_VECT, "sh7372-intca-irq-lo");
306
307INTC_IRQ_PINS_16H(intca_irq_pins_hi, 0xe6900000,
308 INTC_VECT, "sh7372-intca-irq-hi");
309
310enum {
311 UNUSED_INTCS = 0,
312 ENABLED_INTCS,
313
314 /* interrupt sources INTCS */
315
316 /* IRQ0S - IRQ31S */
317 VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
318 RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
319 CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2,
320 /* MFI */
321 /* BBIF2 */
322 VPU,
323 TSIF1,
324 /* 3DG */
325 _2DDMAC,
326 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
327 IPMMU_IPMMUR, IPMMU_IPMMUR2,
328 RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
329 /* KEYSC */
330 /* TTI20 */
331 MSIOF,
332 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
333 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
334 CMT0,
335 TSIF0,
336 /* CMT2 */
337 LMB,
338 CTI,
339 /* RWDT0 */
340 ICB,
341 JPU_JPEG,
342 LCDC,
343 LCRC,
344 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
345 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
346 ISP,
347 LCDC1,
348 CSIRX,
349 DSITX_DSITX0,
350 DSITX_DSITX1,
351 /* SPU2 */
352 /* FSI */
353 /* FMSI */
354 /* HDMI */
355 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
356 CMT4,
357 DSITX1_DSITX1_0,
358 DSITX1_DSITX1_1,
359 MFIS2_INTCS, /* Priority always enabled using ENABLED_INTCS */
360 CPORTS2R,
361 /* CEC */
362 JPU6E,
363
364 /* interrupt groups INTCS */
365 RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
366 RTDMAC2_1, RTDMAC2_2, TMU1, DSITX,
367};
368
369static struct intc_vect intcs_vectors[] = {
370 /* IRQ0S - IRQ31S */
371 INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720),
372 INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760),
373 INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
374 INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
375 INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0),
376 INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0),
377 /* MFI */
378 /* BBIF2 */
379 INTCS_VECT(VPU, 0x980),
380 INTCS_VECT(TSIF1, 0x9a0),
381 /* 3DG */
382 INTCS_VECT(_2DDMAC, 0xa00),
383 INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
384 INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
385 INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20),
386 INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
387 INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
388 /* KEYSC */
389 /* TTI20 */
390 INTCS_VECT(MSIOF, 0x0d20),
391 INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
392 INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
393 INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
394 INTCS_VECT(TMU_TUNI2, 0xec0),
395 INTCS_VECT(CMT0, 0xf00),
396 INTCS_VECT(TSIF0, 0xf20),
397 /* CMT2 */
398 INTCS_VECT(LMB, 0xf60),
399 INTCS_VECT(CTI, 0x400),
400 /* RWDT0 */
401 INTCS_VECT(ICB, 0x480),
402 INTCS_VECT(JPU_JPEG, 0x560),
403 INTCS_VECT(LCDC, 0x580),
404 INTCS_VECT(LCRC, 0x5a0),
405 INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
406 INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
407 INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13a0),
408 INTCS_VECT(RTDMAC2_2_DADERR, 0x13c0),
409 INTCS_VECT(ISP, 0x1720),
410 INTCS_VECT(LCDC1, 0x1780),
411 INTCS_VECT(CSIRX, 0x17a0),
412 INTCS_VECT(DSITX_DSITX0, 0x17c0),
413 INTCS_VECT(DSITX_DSITX1, 0x17e0),
414 /* SPU2 */
415 /* FSI */
416 /* FMSI */
417 /* HDMI */
418 INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920),
419 INTCS_VECT(TMU1_TUNI2, 0x1940),
420 INTCS_VECT(CMT4, 0x1980),
421 INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
422 INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
423 INTCS_VECT(MFIS2_INTCS, 0x1a00),
424 INTCS_VECT(CPORTS2R, 0x1a20),
425 /* CEC */
426 INTCS_VECT(JPU6E, 0x1a80),
427};
428
429static struct intc_group intcs_groups[] __initdata = {
430 INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
431 RTDMAC_1_DEI2, RTDMAC_1_DEI3),
432 INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
433 INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
434 INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
435 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
436 INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
437 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
438 INTC_GROUP(RTDMAC2_1, RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
439 RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
440 INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4,
441 RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
442 INTC_GROUP(TMU1, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0),
443 INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
444};
445
446static struct intc_mask_reg intcs_mask_registers[] = {
447 { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
448 { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
449 VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
450 { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
451 { 0, 0, 0, VPU,
452 0, 0, 0, 0 } },
453 { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
454 { 0, 0, 0, _2DDMAC,
455 0, 0, 0, ICB } },
456 { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
457 { 0, 0, 0, CTI,
458 JPU_JPEG, 0, LCRC, LCDC } },
459 { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
460 { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
461 RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
462 { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
463 { 0, 0, MSIOF, 0,
464 0, 0, 0, 0 } },
465 { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
466 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
467 0, 0, 0, 0 } },
468 { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
469 { 0, 0, 0, CMT0,
470 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
471 { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
472 { 0, 0, IPMMU_IPMMUR2, IPMMU_IPMMUR,
473 0, 0, 0, 0 } },
474 { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
475 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
476 0, TSIF1, LMB, TSIF0 } },
477 { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
478 { 0, RTDMAC2_2_DADERR, RTDMAC2_2_DEI5, RTDMAC2_2_DEI4,
479 RTDMAC2_1_DEI3, RTDMAC2_1_DEI2, RTDMAC2_1_DEI1, RTDMAC2_1_DEI0 } },
480 { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
481 { 0, ISP, 0, 0,
482 LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
483 { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
484 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
485 CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } },
486 { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
487 { MFIS2_INTCS, CPORTS2R, 0, 0,
488 JPU6E, 0, 0, 0 } },
489};
490
491/* Priority is needed for INTCA to receive the INTCS interrupt */
492static struct intc_prio_reg intcs_prio_registers[] = {
493 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC, ICB } },
494 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
495 { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, CEU, 0, VPU } },
496 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT0 } },
497 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
498 TMU_TUNI2, TSIF1 } },
499 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } },
500 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } },
501 { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } },
502 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } },
503 { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
504 { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC2_1, 0, 0, 0 } },
505 { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC2_2, 0, 0, 0 } },
506 { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { 0, ISP, 0, 0 } },
507 { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX, 0 } },
508 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
509 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0,
510 DSITX1_DSITX1_1, 0 } },
511 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { ENABLED_INTCS, CPORTS2R,
512 0, 0 } },
513 { 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } },
514};
515
516static struct resource intcs_resources[] __initdata = {
517 [0] = {
518 .start = 0xffd20000,
519 .end = 0xffd201ff,
520 .flags = IORESOURCE_MEM,
521 },
522 [1] = {
523 .start = 0xffd50000,
524 .end = 0xffd501ff,
525 .flags = IORESOURCE_MEM,
526 }
527};
528
529static struct intc_desc intcs_desc __initdata = {
530 .name = "sh7372-intcs",
531 .force_enable = ENABLED_INTCS,
532 .skip_syscore_suspend = true,
533 .resource = intcs_resources,
534 .num_resources = ARRAY_SIZE(intcs_resources),
535 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
536 intcs_prio_registers, NULL, NULL),
537};
538
539static void intcs_demux(unsigned int irq, struct irq_desc *desc)
540{
541 void __iomem *reg = (void *)irq_get_handler_data(irq);
542 unsigned int evtcodeas = ioread32(reg);
543
544 generic_handle_irq(intcs_evt2irq(evtcodeas));
545}
546
547static void __iomem *intcs_ffd2;
548static void __iomem *intcs_ffd5;
549
550void __init sh7372_init_irq(void)
551{
552 void __iomem *intevtsa;
553 int n;
554
555 intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE);
556 intevtsa = intcs_ffd2 + 0x100;
557 intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE);
558
559 register_intc_controller(&intca_desc);
560 register_intc_controller(&intca_irq_pins_lo_desc);
561 register_intc_controller(&intca_irq_pins_hi_desc);
562 register_intc_controller(&intcs_desc);
563
564 /* setup dummy cascade chip for INTCS */
565 n = evt2irq(0xf80);
566 irq_alloc_desc_at(n, numa_node_id());
567 irq_set_chip_and_handler_name(n, &dummy_irq_chip,
568 handle_level_irq, "level");
569 set_irq_flags(n, IRQF_VALID); /* yuck */
570
571 /* demux using INTEVTSA */
572 irq_set_handler_data(n, (void *)intevtsa);
573 irq_set_chained_handler(n, intcs_demux);
574
575 /* unmask INTCS in INTAMASK */
576 iowrite16(0, intcs_ffd2 + 0x104);
577}
578
579static unsigned short ffd2[0x200];
580static unsigned short ffd5[0x100];
581
582void sh7372_intcs_suspend(void)
583{
584 int k;
585
586 for (k = 0x00; k <= 0x30; k += 4)
587 ffd2[k] = __raw_readw(intcs_ffd2 + k);
588
589 for (k = 0x80; k <= 0xb0; k += 4)
590 ffd2[k] = __raw_readb(intcs_ffd2 + k);
591
592 for (k = 0x180; k <= 0x188; k += 4)
593 ffd2[k] = __raw_readb(intcs_ffd2 + k);
594
595 for (k = 0x00; k <= 0x3c; k += 4)
596 ffd5[k] = __raw_readw(intcs_ffd5 + k);
597
598 for (k = 0x80; k <= 0x9c; k += 4)
599 ffd5[k] = __raw_readb(intcs_ffd5 + k);
600}
601
602void sh7372_intcs_resume(void)
603{
604 int k;
605
606 for (k = 0x00; k <= 0x30; k += 4)
607 __raw_writew(ffd2[k], intcs_ffd2 + k);
608
609 for (k = 0x80; k <= 0xb0; k += 4)
610 __raw_writeb(ffd2[k], intcs_ffd2 + k);
611
612 for (k = 0x180; k <= 0x188; k += 4)
613 __raw_writeb(ffd2[k], intcs_ffd2 + k);
614
615 for (k = 0x00; k <= 0x3c; k += 4)
616 __raw_writew(ffd5[k], intcs_ffd5 + k);
617
618 for (k = 0x80; k <= 0x9c; k += 4)
619 __raw_writeb(ffd5[k], intcs_ffd5 + k);
620}
621
622#define E694_BASE IOMEM(0xe6940000)
623#define E695_BASE IOMEM(0xe6950000)
624
625static unsigned short e694[0x200];
626static unsigned short e695[0x200];
627
628void sh7372_intca_suspend(void)
629{
630 int k;
631
632 for (k = 0x00; k <= 0x38; k += 4)
633 e694[k] = __raw_readw(E694_BASE + k);
634
635 for (k = 0x80; k <= 0xb4; k += 4)
636 e694[k] = __raw_readb(E694_BASE + k);
637
638 for (k = 0x180; k <= 0x1b4; k += 4)
639 e694[k] = __raw_readb(E694_BASE + k);
640
641 for (k = 0x00; k <= 0x50; k += 4)
642 e695[k] = __raw_readw(E695_BASE + k);
643
644 for (k = 0x80; k <= 0xa8; k += 4)
645 e695[k] = __raw_readb(E695_BASE + k);
646
647 for (k = 0x180; k <= 0x1a8; k += 4)
648 e695[k] = __raw_readb(E695_BASE + k);
649}
650
651void sh7372_intca_resume(void)
652{
653 int k;
654
655 for (k = 0x00; k <= 0x38; k += 4)
656 __raw_writew(e694[k], E694_BASE + k);
657
658 for (k = 0x80; k <= 0xb4; k += 4)
659 __raw_writeb(e694[k], E694_BASE + k);
660
661 for (k = 0x180; k <= 0x1b4; k += 4)
662 __raw_writeb(e694[k], E694_BASE + k);
663
664 for (k = 0x00; k <= 0x50; k += 4)
665 __raw_writew(e695[k], E695_BASE + k);
666
667 for (k = 0x80; k <= 0xa8; k += 4)
668 __raw_writeb(e695[k], E695_BASE + k);
669
670 for (k = 0x180; k <= 0x1a8; k += 4)
671 __raw_writeb(e695[k], E695_BASE + k);
672}
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
deleted file mode 100644
index c0293ae4b013..000000000000
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ /dev/null
@@ -1,549 +0,0 @@
1/*
2 * sh7372 Power management support
3 *
4 * Copyright (C) 2011 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/pm.h>
12#include <linux/suspend.h>
13#include <linux/cpuidle.h>
14#include <linux/module.h>
15#include <linux/list.h>
16#include <linux/err.h>
17#include <linux/slab.h>
18#include <linux/pm_clock.h>
19#include <linux/platform_device.h>
20#include <linux/delay.h>
21#include <linux/irq.h>
22#include <linux/bitrev.h>
23#include <linux/console.h>
24
25#include <asm/cpuidle.h>
26#include <asm/io.h>
27#include <asm/tlbflush.h>
28#include <asm/suspend.h>
29
30#include "common.h"
31#include "pm-rmobile.h"
32#include "sh7372.h"
33
34/* DBG */
35#define DBGREG1 IOMEM(0xe6100020)
36#define DBGREG9 IOMEM(0xe6100040)
37
38/* CPGA */
39#define SYSTBCR IOMEM(0xe6150024)
40#define MSTPSR0 IOMEM(0xe6150030)
41#define MSTPSR1 IOMEM(0xe6150038)
42#define MSTPSR2 IOMEM(0xe6150040)
43#define MSTPSR3 IOMEM(0xe6150048)
44#define MSTPSR4 IOMEM(0xe615004c)
45#define PLLC01STPCR IOMEM(0xe61500c8)
46
47/* SYSC */
48#define SYSC_BASE IOMEM(0xe6180000)
49
50#define SBAR IOMEM(0xe6180020)
51#define WUPRMSK IOMEM(0xe6180028)
52#define WUPSMSK IOMEM(0xe618002c)
53#define WUPSMSK2 IOMEM(0xe6180048)
54#define WUPSFAC IOMEM(0xe6180098)
55#define IRQCR IOMEM(0xe618022c)
56#define IRQCR2 IOMEM(0xe6180238)
57#define IRQCR3 IOMEM(0xe6180244)
58#define IRQCR4 IOMEM(0xe6180248)
59#define PDNSEL IOMEM(0xe6180254)
60
61/* INTC */
62#define ICR1A IOMEM(0xe6900000)
63#define ICR2A IOMEM(0xe6900004)
64#define ICR3A IOMEM(0xe6900008)
65#define ICR4A IOMEM(0xe690000c)
66#define INTMSK00A IOMEM(0xe6900040)
67#define INTMSK10A IOMEM(0xe6900044)
68#define INTMSK20A IOMEM(0xe6900048)
69#define INTMSK30A IOMEM(0xe690004c)
70
71/* MFIS */
72/* FIXME: pointing where? */
73#define SMFRAM 0xe6a70000
74
75/* AP-System Core */
76#define APARMBAREA IOMEM(0xe6f10020)
77
78#ifdef CONFIG_PM
79
80#define PM_DOMAIN_ON_OFF_LATENCY_NS 250000
81
82static int sh7372_a4r_pd_suspend(void)
83{
84 sh7372_intcs_suspend();
85 __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
86 return 0;
87}
88
89static bool a4s_suspend_ready;
90
91static int sh7372_a4s_pd_suspend(void)
92{
93 /*
94 * The A4S domain contains the CPU core and therefore it should
95 * only be turned off if the CPU is not in use. This may happen
96 * during system suspend, when SYSC is going to be used for generating
97 * resume signals and a4s_suspend_ready is set to let
98 * sh7372_enter_suspend() know that it can turn A4S off.
99 */
100 a4s_suspend_ready = true;
101 return -EBUSY;
102}
103
104static void sh7372_a4s_pd_resume(void)
105{
106 a4s_suspend_ready = false;
107}
108
109static int sh7372_a3sp_pd_suspend(void)
110{
111 /*
112 * Serial consoles make use of SCIF hardware located in A3SP,
113 * keep such power domain on if "no_console_suspend" is set.
114 */
115 return console_suspend_enabled ? 0 : -EBUSY;
116}
117
118static struct rmobile_pm_domain sh7372_pm_domains[] = {
119 {
120 .genpd.name = "A4LC",
121 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
122 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
123 .base = SYSC_BASE,
124 .bit_shift = 1,
125 },
126 {
127 .genpd.name = "A4MP",
128 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
129 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
130 .base = SYSC_BASE,
131 .bit_shift = 2,
132 },
133 {
134 .genpd.name = "D4",
135 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
136 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
137 .base = SYSC_BASE,
138 .bit_shift = 3,
139 },
140 {
141 .genpd.name = "A4R",
142 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
143 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
144 .base = SYSC_BASE,
145 .bit_shift = 5,
146 .suspend = sh7372_a4r_pd_suspend,
147 .resume = sh7372_intcs_resume,
148 },
149 {
150 .genpd.name = "A3RV",
151 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
152 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
153 .base = SYSC_BASE,
154 .bit_shift = 6,
155 },
156 {
157 .genpd.name = "A3RI",
158 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
159 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
160 .base = SYSC_BASE,
161 .bit_shift = 8,
162 },
163 {
164 .genpd.name = "A4S",
165 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
166 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
167 .base = SYSC_BASE,
168 .bit_shift = 10,
169 .gov = &pm_domain_always_on_gov,
170 .no_debug = true,
171 .suspend = sh7372_a4s_pd_suspend,
172 .resume = sh7372_a4s_pd_resume,
173 },
174 {
175 .genpd.name = "A3SP",
176 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
177 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
178 .base = SYSC_BASE,
179 .bit_shift = 11,
180 .gov = &pm_domain_always_on_gov,
181 .no_debug = true,
182 .suspend = sh7372_a3sp_pd_suspend,
183 },
184 {
185 .genpd.name = "A3SG",
186 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
187 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
188 .base = SYSC_BASE,
189 .bit_shift = 13,
190 },
191};
192
193void __init sh7372_init_pm_domains(void)
194{
195 rmobile_init_domains(sh7372_pm_domains, ARRAY_SIZE(sh7372_pm_domains));
196 pm_genpd_add_subdomain_names("A4LC", "A3RV");
197 pm_genpd_add_subdomain_names("A4R", "A4LC");
198 pm_genpd_add_subdomain_names("A4S", "A3SG");
199 pm_genpd_add_subdomain_names("A4S", "A3SP");
200}
201
202#endif /* CONFIG_PM */
203
204#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
205static void sh7372_set_reset_vector(unsigned long address)
206{
207 /* set reset vector, translate 4k */
208 __raw_writel(address, SBAR);
209 __raw_writel(0, APARMBAREA);
210}
211
212static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode)
213{
214 if (pllc0_on)
215 __raw_writel(0, PLLC01STPCR);
216 else
217 __raw_writel(1 << 28, PLLC01STPCR);
218
219 __raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */
220 cpu_suspend(sleep_mode, sh7372_do_idle_sysc);
221 __raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */
222
223 /* disable reset vector translation */
224 __raw_writel(0, SBAR);
225}
226
227static int sh7372_sysc_valid(unsigned long *mskp, unsigned long *msk2p)
228{
229 unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4;
230 unsigned long msk, msk2;
231
232 /* check active clocks to determine potential wakeup sources */
233
234 mstpsr0 = __raw_readl(MSTPSR0);
235 if ((mstpsr0 & 0x00000003) != 0x00000003) {
236 pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0);
237 return 0;
238 }
239
240 mstpsr1 = __raw_readl(MSTPSR1);
241 if ((mstpsr1 & 0xff079b7f) != 0xff079b7f) {
242 pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1);
243 return 0;
244 }
245
246 mstpsr2 = __raw_readl(MSTPSR2);
247 if ((mstpsr2 & 0x000741ff) != 0x000741ff) {
248 pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2);
249 return 0;
250 }
251
252 mstpsr3 = __raw_readl(MSTPSR3);
253 if ((mstpsr3 & 0x1a60f010) != 0x1a60f010) {
254 pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3);
255 return 0;
256 }
257
258 mstpsr4 = __raw_readl(MSTPSR4);
259 if ((mstpsr4 & 0x00008cf0) != 0x00008cf0) {
260 pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4);
261 return 0;
262 }
263
264 msk = 0;
265 msk2 = 0;
266
267 /* make bitmaps of limited number of wakeup sources */
268
269 if ((mstpsr2 & (1 << 23)) == 0) /* SPU2 */
270 msk |= 1 << 31;
271
272 if ((mstpsr2 & (1 << 12)) == 0) /* MFI_MFIM */
273 msk |= 1 << 21;
274
275 if ((mstpsr4 & (1 << 3)) == 0) /* KEYSC */
276 msk |= 1 << 2;
277
278 if ((mstpsr1 & (1 << 24)) == 0) /* CMT0 */
279 msk |= 1 << 1;
280
281 if ((mstpsr3 & (1 << 29)) == 0) /* CMT1 */
282 msk |= 1 << 1;
283
284 if ((mstpsr4 & (1 << 0)) == 0) /* CMT2 */
285 msk |= 1 << 1;
286
287 if ((mstpsr2 & (1 << 13)) == 0) /* MFI_MFIS */
288 msk2 |= 1 << 17;
289
290 *mskp = msk;
291 *msk2p = msk2;
292
293 return 1;
294}
295
296static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p)
297{
298 u16 tmp, irqcr1, irqcr2;
299 int k;
300
301 irqcr1 = 0;
302 irqcr2 = 0;
303
304 /* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */
305 for (k = 0; k <= 7; k++) {
306 tmp = (icr >> ((7 - k) * 4)) & 0xf;
307 irqcr1 |= (tmp & 0x03) << (k * 2);
308 irqcr2 |= (tmp >> 2) << (k * 2);
309 }
310
311 *irqcr1p = irqcr1;
312 *irqcr2p = irqcr2;
313}
314
315static void sh7372_setup_sysc(unsigned long msk, unsigned long msk2)
316{
317 u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high;
318 unsigned long tmp;
319
320 /* read IRQ0A -> IRQ15A mask */
321 tmp = bitrev8(__raw_readb(INTMSK00A));
322 tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8;
323
324 /* setup WUPSMSK from clocks and external IRQ mask */
325 msk = (~msk & 0xc030000f) | (tmp << 4);
326 __raw_writel(msk, WUPSMSK);
327
328 /* propage level/edge trigger for external IRQ 0->15 */
329 sh7372_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low);
330 sh7372_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high);
331 __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR);
332 __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2);
333
334 /* read IRQ16A -> IRQ31A mask */
335 tmp = bitrev8(__raw_readb(INTMSK20A));
336 tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8;
337
338 /* setup WUPSMSK2 from clocks and external IRQ mask */
339 msk2 = (~msk2 & 0x00030000) | tmp;
340 __raw_writel(msk2, WUPSMSK2);
341
342 /* propage level/edge trigger for external IRQ 16->31 */
343 sh7372_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low);
344 sh7372_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high);
345 __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3);
346 __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4);
347}
348
349static void sh7372_enter_a3sm_common(int pllc0_on)
350{
351 /* use INTCA together with SYSC for wakeup */
352 sh7372_setup_sysc(1 << 0, 0);
353 sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
354 sh7372_enter_sysc(pllc0_on, 1 << 12);
355}
356
357static void sh7372_enter_a4s_common(int pllc0_on)
358{
359 sh7372_intca_suspend();
360 sh7372_set_reset_vector(SMFRAM);
361 sh7372_enter_sysc(pllc0_on, 1 << 10);
362 sh7372_intca_resume();
363}
364
365static void sh7372_pm_setup_smfram(void)
366{
367 /* pass physical address of cpu_resume() to assembly resume code */
368 sh7372_cpu_resume = virt_to_phys(cpu_resume);
369
370 memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
371}
372#else
373static inline void sh7372_pm_setup_smfram(void) {}
374#endif /* CONFIG_SUSPEND || CONFIG_CPU_IDLE */
375
376#ifdef CONFIG_CPU_IDLE
377static int sh7372_do_idle_core_standby(unsigned long unused)
378{
379 cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
380 return 0;
381}
382
383static int sh7372_enter_core_standby(struct cpuidle_device *dev,
384 struct cpuidle_driver *drv, int index)
385{
386 sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
387
388 /* enter sleep mode with SYSTBCR to 0x10 */
389 __raw_writel(0x10, SYSTBCR);
390 cpu_suspend(0, sh7372_do_idle_core_standby);
391 __raw_writel(0, SYSTBCR);
392
393 /* disable reset vector translation */
394 __raw_writel(0, SBAR);
395
396 return 1;
397}
398
399static int sh7372_enter_a3sm_pll_on(struct cpuidle_device *dev,
400 struct cpuidle_driver *drv, int index)
401{
402 sh7372_enter_a3sm_common(1);
403 return 2;
404}
405
406static int sh7372_enter_a3sm_pll_off(struct cpuidle_device *dev,
407 struct cpuidle_driver *drv, int index)
408{
409 sh7372_enter_a3sm_common(0);
410 return 3;
411}
412
413static int sh7372_enter_a4s(struct cpuidle_device *dev,
414 struct cpuidle_driver *drv, int index)
415{
416 unsigned long msk, msk2;
417
418 if (!sh7372_sysc_valid(&msk, &msk2))
419 return sh7372_enter_a3sm_pll_off(dev, drv, index);
420
421 sh7372_setup_sysc(msk, msk2);
422 sh7372_enter_a4s_common(0);
423 return 4;
424}
425
426static struct cpuidle_driver sh7372_cpuidle_driver = {
427 .name = "sh7372_cpuidle",
428 .owner = THIS_MODULE,
429 .state_count = 5,
430 .safe_state_index = 0, /* C1 */
431 .states[0] = ARM_CPUIDLE_WFI_STATE,
432 .states[1] = {
433 .name = "C2",
434 .desc = "Core Standby Mode",
435 .exit_latency = 10,
436 .target_residency = 20 + 10,
437 .enter = sh7372_enter_core_standby,
438 },
439 .states[2] = {
440 .name = "C3",
441 .desc = "A3SM PLL ON",
442 .exit_latency = 20,
443 .target_residency = 30 + 20,
444 .enter = sh7372_enter_a3sm_pll_on,
445 },
446 .states[3] = {
447 .name = "C4",
448 .desc = "A3SM PLL OFF",
449 .exit_latency = 120,
450 .target_residency = 30 + 120,
451 .enter = sh7372_enter_a3sm_pll_off,
452 },
453 .states[4] = {
454 .name = "C5",
455 .desc = "A4S PLL OFF",
456 .exit_latency = 240,
457 .target_residency = 30 + 240,
458 .enter = sh7372_enter_a4s,
459 .disabled = true,
460 },
461};
462
463static void __init sh7372_cpuidle_init(void)
464{
465 shmobile_cpuidle_set_driver(&sh7372_cpuidle_driver);
466}
467#else
468static void __init sh7372_cpuidle_init(void) {}
469#endif
470
471#ifdef CONFIG_SUSPEND
472static int sh7372_enter_suspend(suspend_state_t suspend_state)
473{
474 unsigned long msk, msk2;
475
476 /* check active clocks to determine potential wakeup sources */
477 if (sh7372_sysc_valid(&msk, &msk2) && a4s_suspend_ready) {
478 /* convert INTC mask/sense to SYSC mask/sense */
479 sh7372_setup_sysc(msk, msk2);
480
481 /* enter A4S sleep with PLLC0 off */
482 pr_debug("entering A4S\n");
483 sh7372_enter_a4s_common(0);
484 return 0;
485 }
486
487 /* default to enter A3SM sleep with PLLC0 off */
488 pr_debug("entering A3SM\n");
489 sh7372_enter_a3sm_common(0);
490 return 0;
491}
492
493/**
494 * sh7372_pm_notifier_fn - SH7372 PM notifier routine.
495 * @notifier: Unused.
496 * @pm_event: Event being handled.
497 * @unused: Unused.
498 */
499static int sh7372_pm_notifier_fn(struct notifier_block *notifier,
500 unsigned long pm_event, void *unused)
501{
502 switch (pm_event) {
503 case PM_SUSPEND_PREPARE:
504 /*
505 * This is necessary, because the A4R domain has to be "on"
506 * when suspend_device_irqs() and resume_device_irqs() are
507 * executed during system suspend and resume, respectively, so
508 * that those functions don't crash while accessing the INTCS.
509 */
510 pm_genpd_name_poweron("A4R");
511 break;
512 case PM_POST_SUSPEND:
513 pm_genpd_poweroff_unused();
514 break;
515 }
516
517 return NOTIFY_DONE;
518}
519
520static void sh7372_suspend_init(void)
521{
522 shmobile_suspend_ops.enter = sh7372_enter_suspend;
523 pm_notifier(sh7372_pm_notifier_fn, 0);
524}
525#else
526static void sh7372_suspend_init(void) {}
527#endif
528
529void __init sh7372_pm_init(void)
530{
531 /* enable DBG hardware block to kick SYSC */
532 __raw_writel(0x0000a500, DBGREG9);
533 __raw_writel(0x0000a501, DBGREG9);
534 __raw_writel(0x00000000, DBGREG1);
535
536 /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
537 __raw_writel(0, PDNSEL);
538
539 sh7372_pm_setup_smfram();
540
541 sh7372_suspend_init();
542 sh7372_cpuidle_init();
543}
544
545void __init sh7372_pm_init_late(void)
546{
547 shmobile_init_late();
548 pm_genpd_name_attach_cpuidle("A4S", 4);
549}
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
deleted file mode 100644
index 458a2cfad417..000000000000
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ /dev/null
@@ -1,1016 +0,0 @@
1/*
2 * sh7372 processor support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/platform_device.h>
21#include <linux/of_platform.h>
22#include <linux/uio_driver.h>
23#include <linux/delay.h>
24#include <linux/input.h>
25#include <linux/io.h>
26#include <linux/serial_sci.h>
27#include <linux/sh_dma.h>
28#include <linux/sh_timer.h>
29#include <linux/pm_domain.h>
30#include <linux/dma-mapping.h>
31#include <linux/platform_data/sh_ipmmu.h>
32
33#include <asm/mach/map.h>
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37
38#include "common.h"
39#include "dma-register.h"
40#include "intc.h"
41#include "irqs.h"
42#include "pm-rmobile.h"
43#include "sh7372.h"
44
45static struct map_desc sh7372_io_desc[] __initdata = {
46 /* create a 1:1 identity mapping for 0xe6xxxxxx
47 * used by CPGA, INTC and PFC.
48 */
49 {
50 .virtual = 0xe6000000,
51 .pfn = __phys_to_pfn(0xe6000000),
52 .length = 256 << 20,
53 .type = MT_DEVICE_NONSHARED
54 },
55};
56
57void __init sh7372_map_io(void)
58{
59 debug_ll_io_init();
60 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
61}
62
63/* PFC */
64static struct resource sh7372_pfc_resources[] = {
65 [0] = {
66 .start = 0xe6050000,
67 .end = 0xe6057fff,
68 .flags = IORESOURCE_MEM,
69 },
70 [1] = {
71 .start = 0xe605800c,
72 .end = 0xe6058027,
73 .flags = IORESOURCE_MEM,
74 }
75};
76
77static struct platform_device sh7372_pfc_device = {
78 .name = "pfc-sh7372",
79 .id = -1,
80 .resource = sh7372_pfc_resources,
81 .num_resources = ARRAY_SIZE(sh7372_pfc_resources),
82};
83
84void __init sh7372_pinmux_init(void)
85{
86 platform_device_register(&sh7372_pfc_device);
87}
88
89/* SCIF */
90#define SH7372_SCIF(scif_type, index, baseaddr, irq) \
91static struct plat_sci_port scif##index##_platform_data = { \
92 .type = scif_type, \
93 .flags = UPF_BOOT_AUTOCONF, \
94 .scscr = SCSCR_RE | SCSCR_TE, \
95}; \
96 \
97static struct resource scif##index##_resources[] = { \
98 DEFINE_RES_MEM(baseaddr, 0x100), \
99 DEFINE_RES_IRQ(irq), \
100}; \
101 \
102static struct platform_device scif##index##_device = { \
103 .name = "sh-sci", \
104 .id = index, \
105 .resource = scif##index##_resources, \
106 .num_resources = ARRAY_SIZE(scif##index##_resources), \
107 .dev = { \
108 .platform_data = &scif##index##_platform_data, \
109 }, \
110}
111
112SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
113SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
114SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
115SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
116SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
117SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
118SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
119
120/* CMT */
121static struct sh_timer_config cmt2_platform_data = {
122 .channels_mask = 0x20,
123};
124
125static struct resource cmt2_resources[] = {
126 DEFINE_RES_MEM(0xe6130000, 0x50),
127 DEFINE_RES_IRQ(evt2irq(0x0b80)),
128};
129
130static struct platform_device cmt2_device = {
131 .name = "sh-cmt-32-fast",
132 .id = 2,
133 .dev = {
134 .platform_data = &cmt2_platform_data,
135 },
136 .resource = cmt2_resources,
137 .num_resources = ARRAY_SIZE(cmt2_resources),
138};
139
140/* TMU */
141static struct sh_timer_config tmu0_platform_data = {
142 .channels_mask = 7,
143};
144
145static struct resource tmu0_resources[] = {
146 DEFINE_RES_MEM(0xfff60000, 0x2c),
147 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
148 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
149 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
150};
151
152static struct platform_device tmu0_device = {
153 .name = "sh-tmu",
154 .id = 0,
155 .dev = {
156 .platform_data = &tmu0_platform_data,
157 },
158 .resource = tmu0_resources,
159 .num_resources = ARRAY_SIZE(tmu0_resources),
160};
161
162/* I2C */
163static struct resource iic0_resources[] = {
164 [0] = {
165 .name = "IIC0",
166 .start = 0xFFF20000,
167 .end = 0xFFF20425 - 1,
168 .flags = IORESOURCE_MEM,
169 },
170 [1] = {
171 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
172 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
173 .flags = IORESOURCE_IRQ,
174 },
175};
176
177static struct platform_device iic0_device = {
178 .name = "i2c-sh_mobile",
179 .id = 0, /* "i2c0" clock */
180 .num_resources = ARRAY_SIZE(iic0_resources),
181 .resource = iic0_resources,
182};
183
184static struct resource iic1_resources[] = {
185 [0] = {
186 .name = "IIC1",
187 .start = 0xE6C20000,
188 .end = 0xE6C20425 - 1,
189 .flags = IORESOURCE_MEM,
190 },
191 [1] = {
192 .start = evt2irq(0x780), /* IIC1_ALI1 */
193 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
194 .flags = IORESOURCE_IRQ,
195 },
196};
197
198static struct platform_device iic1_device = {
199 .name = "i2c-sh_mobile",
200 .id = 1, /* "i2c1" clock */
201 .num_resources = ARRAY_SIZE(iic1_resources),
202 .resource = iic1_resources,
203};
204
205/* DMA */
206static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
207 {
208 .slave_id = SHDMA_SLAVE_SCIF0_TX,
209 .addr = 0xe6c40020,
210 .chcr = CHCR_TX(XMIT_SZ_8BIT),
211 .mid_rid = 0x21,
212 }, {
213 .slave_id = SHDMA_SLAVE_SCIF0_RX,
214 .addr = 0xe6c40024,
215 .chcr = CHCR_RX(XMIT_SZ_8BIT),
216 .mid_rid = 0x22,
217 }, {
218 .slave_id = SHDMA_SLAVE_SCIF1_TX,
219 .addr = 0xe6c50020,
220 .chcr = CHCR_TX(XMIT_SZ_8BIT),
221 .mid_rid = 0x25,
222 }, {
223 .slave_id = SHDMA_SLAVE_SCIF1_RX,
224 .addr = 0xe6c50024,
225 .chcr = CHCR_RX(XMIT_SZ_8BIT),
226 .mid_rid = 0x26,
227 }, {
228 .slave_id = SHDMA_SLAVE_SCIF2_TX,
229 .addr = 0xe6c60020,
230 .chcr = CHCR_TX(XMIT_SZ_8BIT),
231 .mid_rid = 0x29,
232 }, {
233 .slave_id = SHDMA_SLAVE_SCIF2_RX,
234 .addr = 0xe6c60024,
235 .chcr = CHCR_RX(XMIT_SZ_8BIT),
236 .mid_rid = 0x2a,
237 }, {
238 .slave_id = SHDMA_SLAVE_SCIF3_TX,
239 .addr = 0xe6c70020,
240 .chcr = CHCR_TX(XMIT_SZ_8BIT),
241 .mid_rid = 0x2d,
242 }, {
243 .slave_id = SHDMA_SLAVE_SCIF3_RX,
244 .addr = 0xe6c70024,
245 .chcr = CHCR_RX(XMIT_SZ_8BIT),
246 .mid_rid = 0x2e,
247 }, {
248 .slave_id = SHDMA_SLAVE_SCIF4_TX,
249 .addr = 0xe6c80020,
250 .chcr = CHCR_TX(XMIT_SZ_8BIT),
251 .mid_rid = 0x39,
252 }, {
253 .slave_id = SHDMA_SLAVE_SCIF4_RX,
254 .addr = 0xe6c80024,
255 .chcr = CHCR_RX(XMIT_SZ_8BIT),
256 .mid_rid = 0x3a,
257 }, {
258 .slave_id = SHDMA_SLAVE_SCIF5_TX,
259 .addr = 0xe6cb0020,
260 .chcr = CHCR_TX(XMIT_SZ_8BIT),
261 .mid_rid = 0x35,
262 }, {
263 .slave_id = SHDMA_SLAVE_SCIF5_RX,
264 .addr = 0xe6cb0024,
265 .chcr = CHCR_RX(XMIT_SZ_8BIT),
266 .mid_rid = 0x36,
267 }, {
268 .slave_id = SHDMA_SLAVE_SCIF6_TX,
269 .addr = 0xe6c30040,
270 .chcr = CHCR_TX(XMIT_SZ_8BIT),
271 .mid_rid = 0x3d,
272 }, {
273 .slave_id = SHDMA_SLAVE_SCIF6_RX,
274 .addr = 0xe6c30060,
275 .chcr = CHCR_RX(XMIT_SZ_8BIT),
276 .mid_rid = 0x3e,
277 }, {
278 .slave_id = SHDMA_SLAVE_FLCTL0_TX,
279 .addr = 0xe6a30050,
280 .chcr = CHCR_TX(XMIT_SZ_32BIT),
281 .mid_rid = 0x83,
282 }, {
283 .slave_id = SHDMA_SLAVE_FLCTL0_RX,
284 .addr = 0xe6a30050,
285 .chcr = CHCR_RX(XMIT_SZ_32BIT),
286 .mid_rid = 0x83,
287 }, {
288 .slave_id = SHDMA_SLAVE_FLCTL1_TX,
289 .addr = 0xe6a30060,
290 .chcr = CHCR_TX(XMIT_SZ_32BIT),
291 .mid_rid = 0x87,
292 }, {
293 .slave_id = SHDMA_SLAVE_FLCTL1_RX,
294 .addr = 0xe6a30060,
295 .chcr = CHCR_RX(XMIT_SZ_32BIT),
296 .mid_rid = 0x87,
297 }, {
298 .slave_id = SHDMA_SLAVE_SDHI0_TX,
299 .addr = 0xe6850030,
300 .chcr = CHCR_TX(XMIT_SZ_16BIT),
301 .mid_rid = 0xc1,
302 }, {
303 .slave_id = SHDMA_SLAVE_SDHI0_RX,
304 .addr = 0xe6850030,
305 .chcr = CHCR_RX(XMIT_SZ_16BIT),
306 .mid_rid = 0xc2,
307 }, {
308 .slave_id = SHDMA_SLAVE_SDHI1_TX,
309 .addr = 0xe6860030,
310 .chcr = CHCR_TX(XMIT_SZ_16BIT),
311 .mid_rid = 0xc9,
312 }, {
313 .slave_id = SHDMA_SLAVE_SDHI1_RX,
314 .addr = 0xe6860030,
315 .chcr = CHCR_RX(XMIT_SZ_16BIT),
316 .mid_rid = 0xca,
317 }, {
318 .slave_id = SHDMA_SLAVE_SDHI2_TX,
319 .addr = 0xe6870030,
320 .chcr = CHCR_TX(XMIT_SZ_16BIT),
321 .mid_rid = 0xcd,
322 }, {
323 .slave_id = SHDMA_SLAVE_SDHI2_RX,
324 .addr = 0xe6870030,
325 .chcr = CHCR_RX(XMIT_SZ_16BIT),
326 .mid_rid = 0xce,
327 }, {
328 .slave_id = SHDMA_SLAVE_FSIA_TX,
329 .addr = 0xfe1f0024,
330 .chcr = CHCR_TX(XMIT_SZ_32BIT),
331 .mid_rid = 0xb1,
332 }, {
333 .slave_id = SHDMA_SLAVE_FSIA_RX,
334 .addr = 0xfe1f0020,
335 .chcr = CHCR_RX(XMIT_SZ_32BIT),
336 .mid_rid = 0xb2,
337 }, {
338 .slave_id = SHDMA_SLAVE_MMCIF_TX,
339 .addr = 0xe6bd0034,
340 .chcr = CHCR_TX(XMIT_SZ_32BIT),
341 .mid_rid = 0xd1,
342 }, {
343 .slave_id = SHDMA_SLAVE_MMCIF_RX,
344 .addr = 0xe6bd0034,
345 .chcr = CHCR_RX(XMIT_SZ_32BIT),
346 .mid_rid = 0xd2,
347 },
348};
349
350#define SH7372_CHCLR (0x220 - 0x20)
351
352static const struct sh_dmae_channel sh7372_dmae_channels[] = {
353 {
354 .offset = 0,
355 .dmars = 0,
356 .dmars_bit = 0,
357 .chclr_offset = SH7372_CHCLR + 0,
358 }, {
359 .offset = 0x10,
360 .dmars = 0,
361 .dmars_bit = 8,
362 .chclr_offset = SH7372_CHCLR + 0x10,
363 }, {
364 .offset = 0x20,
365 .dmars = 4,
366 .dmars_bit = 0,
367 .chclr_offset = SH7372_CHCLR + 0x20,
368 }, {
369 .offset = 0x30,
370 .dmars = 4,
371 .dmars_bit = 8,
372 .chclr_offset = SH7372_CHCLR + 0x30,
373 }, {
374 .offset = 0x50,
375 .dmars = 8,
376 .dmars_bit = 0,
377 .chclr_offset = SH7372_CHCLR + 0x50,
378 }, {
379 .offset = 0x60,
380 .dmars = 8,
381 .dmars_bit = 8,
382 .chclr_offset = SH7372_CHCLR + 0x60,
383 }
384};
385
386static struct sh_dmae_pdata dma_platform_data = {
387 .slave = sh7372_dmae_slaves,
388 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
389 .channel = sh7372_dmae_channels,
390 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
391 .ts_low_shift = TS_LOW_SHIFT,
392 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
393 .ts_high_shift = TS_HI_SHIFT,
394 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
395 .ts_shift = dma_ts_shift,
396 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
397 .dmaor_init = DMAOR_DME,
398 .chclr_present = 1,
399};
400
401/* Resource order important! */
402static struct resource sh7372_dmae0_resources[] = {
403 {
404 /* Channel registers and DMAOR */
405 .start = 0xfe008020,
406 .end = 0xfe00828f,
407 .flags = IORESOURCE_MEM,
408 },
409 {
410 /* DMARSx */
411 .start = 0xfe009000,
412 .end = 0xfe00900b,
413 .flags = IORESOURCE_MEM,
414 },
415 {
416 .name = "error_irq",
417 .start = evt2irq(0x20c0),
418 .end = evt2irq(0x20c0),
419 .flags = IORESOURCE_IRQ,
420 },
421 {
422 /* IRQ for channels 0-5 */
423 .start = evt2irq(0x2000),
424 .end = evt2irq(0x20a0),
425 .flags = IORESOURCE_IRQ,
426 },
427};
428
429/* Resource order important! */
430static struct resource sh7372_dmae1_resources[] = {
431 {
432 /* Channel registers and DMAOR */
433 .start = 0xfe018020,
434 .end = 0xfe01828f,
435 .flags = IORESOURCE_MEM,
436 },
437 {
438 /* DMARSx */
439 .start = 0xfe019000,
440 .end = 0xfe01900b,
441 .flags = IORESOURCE_MEM,
442 },
443 {
444 .name = "error_irq",
445 .start = evt2irq(0x21c0),
446 .end = evt2irq(0x21c0),
447 .flags = IORESOURCE_IRQ,
448 },
449 {
450 /* IRQ for channels 0-5 */
451 .start = evt2irq(0x2100),
452 .end = evt2irq(0x21a0),
453 .flags = IORESOURCE_IRQ,
454 },
455};
456
457/* Resource order important! */
458static struct resource sh7372_dmae2_resources[] = {
459 {
460 /* Channel registers and DMAOR */
461 .start = 0xfe028020,
462 .end = 0xfe02828f,
463 .flags = IORESOURCE_MEM,
464 },
465 {
466 /* DMARSx */
467 .start = 0xfe029000,
468 .end = 0xfe02900b,
469 .flags = IORESOURCE_MEM,
470 },
471 {
472 .name = "error_irq",
473 .start = evt2irq(0x22c0),
474 .end = evt2irq(0x22c0),
475 .flags = IORESOURCE_IRQ,
476 },
477 {
478 /* IRQ for channels 0-5 */
479 .start = evt2irq(0x2200),
480 .end = evt2irq(0x22a0),
481 .flags = IORESOURCE_IRQ,
482 },
483};
484
485static struct platform_device dma0_device = {
486 .name = "sh-dma-engine",
487 .id = 0,
488 .resource = sh7372_dmae0_resources,
489 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
490 .dev = {
491 .platform_data = &dma_platform_data,
492 },
493};
494
495static struct platform_device dma1_device = {
496 .name = "sh-dma-engine",
497 .id = 1,
498 .resource = sh7372_dmae1_resources,
499 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
500 .dev = {
501 .platform_data = &dma_platform_data,
502 },
503};
504
505static struct platform_device dma2_device = {
506 .name = "sh-dma-engine",
507 .id = 2,
508 .resource = sh7372_dmae2_resources,
509 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
510 .dev = {
511 .platform_data = &dma_platform_data,
512 },
513};
514
515/*
516 * USB-DMAC
517 */
518static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
519 {
520 .offset = 0,
521 }, {
522 .offset = 0x20,
523 },
524};
525
526/* USB DMAC0 */
527static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
528 {
529 .slave_id = SHDMA_SLAVE_USB0_TX,
530 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
531 }, {
532 .slave_id = SHDMA_SLAVE_USB0_RX,
533 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
534 },
535};
536
537static struct sh_dmae_pdata usb_dma0_platform_data = {
538 .slave = sh7372_usb_dmae0_slaves,
539 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
540 .channel = sh7372_usb_dmae_channels,
541 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
542 .ts_low_shift = USBTS_LOW_SHIFT,
543 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
544 .ts_high_shift = USBTS_HI_SHIFT,
545 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
546 .ts_shift = dma_usbts_shift,
547 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
548 .dmaor_init = DMAOR_DME,
549 .chcr_offset = 0x14,
550 .chcr_ie_bit = 1 << 5,
551 .dmaor_is_32bit = 1,
552 .needs_tend_set = 1,
553 .no_dmars = 1,
554 .slave_only = 1,
555};
556
557static struct resource sh7372_usb_dmae0_resources[] = {
558 {
559 /* Channel registers and DMAOR */
560 .start = 0xe68a0020,
561 .end = 0xe68a0064 - 1,
562 .flags = IORESOURCE_MEM,
563 },
564 {
565 /* VCR/SWR/DMICR */
566 .start = 0xe68a0000,
567 .end = 0xe68a0014 - 1,
568 .flags = IORESOURCE_MEM,
569 },
570 {
571 /* IRQ for channels */
572 .start = evt2irq(0x0a00),
573 .end = evt2irq(0x0a00),
574 .flags = IORESOURCE_IRQ,
575 },
576};
577
578static struct platform_device usb_dma0_device = {
579 .name = "sh-dma-engine",
580 .id = 3,
581 .resource = sh7372_usb_dmae0_resources,
582 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
583 .dev = {
584 .platform_data = &usb_dma0_platform_data,
585 },
586};
587
588/* USB DMAC1 */
589static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
590 {
591 .slave_id = SHDMA_SLAVE_USB1_TX,
592 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
593 }, {
594 .slave_id = SHDMA_SLAVE_USB1_RX,
595 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
596 },
597};
598
599static struct sh_dmae_pdata usb_dma1_platform_data = {
600 .slave = sh7372_usb_dmae1_slaves,
601 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
602 .channel = sh7372_usb_dmae_channels,
603 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
604 .ts_low_shift = USBTS_LOW_SHIFT,
605 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
606 .ts_high_shift = USBTS_HI_SHIFT,
607 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
608 .ts_shift = dma_usbts_shift,
609 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
610 .dmaor_init = DMAOR_DME,
611 .chcr_offset = 0x14,
612 .chcr_ie_bit = 1 << 5,
613 .dmaor_is_32bit = 1,
614 .needs_tend_set = 1,
615 .no_dmars = 1,
616 .slave_only = 1,
617};
618
619static struct resource sh7372_usb_dmae1_resources[] = {
620 {
621 /* Channel registers and DMAOR */
622 .start = 0xe68c0020,
623 .end = 0xe68c0064 - 1,
624 .flags = IORESOURCE_MEM,
625 },
626 {
627 /* VCR/SWR/DMICR */
628 .start = 0xe68c0000,
629 .end = 0xe68c0014 - 1,
630 .flags = IORESOURCE_MEM,
631 },
632 {
633 /* IRQ for channels */
634 .start = evt2irq(0x1d00),
635 .end = evt2irq(0x1d00),
636 .flags = IORESOURCE_IRQ,
637 },
638};
639
640static struct platform_device usb_dma1_device = {
641 .name = "sh-dma-engine",
642 .id = 4,
643 .resource = sh7372_usb_dmae1_resources,
644 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
645 .dev = {
646 .platform_data = &usb_dma1_platform_data,
647 },
648};
649
650/* VPU */
651static struct uio_info vpu_platform_data = {
652 .name = "VPU5HG",
653 .version = "0",
654 .irq = intcs_evt2irq(0x980),
655};
656
657static struct resource vpu_resources[] = {
658 [0] = {
659 .name = "VPU",
660 .start = 0xfe900000,
661 .end = 0xfe900157,
662 .flags = IORESOURCE_MEM,
663 },
664};
665
666static struct platform_device vpu_device = {
667 .name = "uio_pdrv_genirq",
668 .id = 0,
669 .dev = {
670 .platform_data = &vpu_platform_data,
671 },
672 .resource = vpu_resources,
673 .num_resources = ARRAY_SIZE(vpu_resources),
674};
675
676/* VEU0 */
677static struct uio_info veu0_platform_data = {
678 .name = "VEU0",
679 .version = "0",
680 .irq = intcs_evt2irq(0x700),
681};
682
683static struct resource veu0_resources[] = {
684 [0] = {
685 .name = "VEU0",
686 .start = 0xfe920000,
687 .end = 0xfe9200cb,
688 .flags = IORESOURCE_MEM,
689 },
690};
691
692static struct platform_device veu0_device = {
693 .name = "uio_pdrv_genirq",
694 .id = 1,
695 .dev = {
696 .platform_data = &veu0_platform_data,
697 },
698 .resource = veu0_resources,
699 .num_resources = ARRAY_SIZE(veu0_resources),
700};
701
702/* VEU1 */
703static struct uio_info veu1_platform_data = {
704 .name = "VEU1",
705 .version = "0",
706 .irq = intcs_evt2irq(0x720),
707};
708
709static struct resource veu1_resources[] = {
710 [0] = {
711 .name = "VEU1",
712 .start = 0xfe924000,
713 .end = 0xfe9240cb,
714 .flags = IORESOURCE_MEM,
715 },
716};
717
718static struct platform_device veu1_device = {
719 .name = "uio_pdrv_genirq",
720 .id = 2,
721 .dev = {
722 .platform_data = &veu1_platform_data,
723 },
724 .resource = veu1_resources,
725 .num_resources = ARRAY_SIZE(veu1_resources),
726};
727
728/* VEU2 */
729static struct uio_info veu2_platform_data = {
730 .name = "VEU2",
731 .version = "0",
732 .irq = intcs_evt2irq(0x740),
733};
734
735static struct resource veu2_resources[] = {
736 [0] = {
737 .name = "VEU2",
738 .start = 0xfe928000,
739 .end = 0xfe928307,
740 .flags = IORESOURCE_MEM,
741 },
742};
743
744static struct platform_device veu2_device = {
745 .name = "uio_pdrv_genirq",
746 .id = 3,
747 .dev = {
748 .platform_data = &veu2_platform_data,
749 },
750 .resource = veu2_resources,
751 .num_resources = ARRAY_SIZE(veu2_resources),
752};
753
754/* VEU3 */
755static struct uio_info veu3_platform_data = {
756 .name = "VEU3",
757 .version = "0",
758 .irq = intcs_evt2irq(0x760),
759};
760
761static struct resource veu3_resources[] = {
762 [0] = {
763 .name = "VEU3",
764 .start = 0xfe92c000,
765 .end = 0xfe92c307,
766 .flags = IORESOURCE_MEM,
767 },
768};
769
770static struct platform_device veu3_device = {
771 .name = "uio_pdrv_genirq",
772 .id = 4,
773 .dev = {
774 .platform_data = &veu3_platform_data,
775 },
776 .resource = veu3_resources,
777 .num_resources = ARRAY_SIZE(veu3_resources),
778};
779
780/* JPU */
781static struct uio_info jpu_platform_data = {
782 .name = "JPU",
783 .version = "0",
784 .irq = intcs_evt2irq(0x560),
785};
786
787static struct resource jpu_resources[] = {
788 [0] = {
789 .name = "JPU",
790 .start = 0xfe980000,
791 .end = 0xfe9902d3,
792 .flags = IORESOURCE_MEM,
793 },
794};
795
796static struct platform_device jpu_device = {
797 .name = "uio_pdrv_genirq",
798 .id = 5,
799 .dev = {
800 .platform_data = &jpu_platform_data,
801 },
802 .resource = jpu_resources,
803 .num_resources = ARRAY_SIZE(jpu_resources),
804};
805
806/* SPU2DSP0 */
807static struct uio_info spu0_platform_data = {
808 .name = "SPU2DSP0",
809 .version = "0",
810 .irq = evt2irq(0x1800),
811};
812
813static struct resource spu0_resources[] = {
814 [0] = {
815 .name = "SPU2DSP0",
816 .start = 0xfe200000,
817 .end = 0xfe2fffff,
818 .flags = IORESOURCE_MEM,
819 },
820};
821
822static struct platform_device spu0_device = {
823 .name = "uio_pdrv_genirq",
824 .id = 6,
825 .dev = {
826 .platform_data = &spu0_platform_data,
827 },
828 .resource = spu0_resources,
829 .num_resources = ARRAY_SIZE(spu0_resources),
830};
831
832/* SPU2DSP1 */
833static struct uio_info spu1_platform_data = {
834 .name = "SPU2DSP1",
835 .version = "0",
836 .irq = evt2irq(0x1820),
837};
838
839static struct resource spu1_resources[] = {
840 [0] = {
841 .name = "SPU2DSP1",
842 .start = 0xfe300000,
843 .end = 0xfe3fffff,
844 .flags = IORESOURCE_MEM,
845 },
846};
847
848static struct platform_device spu1_device = {
849 .name = "uio_pdrv_genirq",
850 .id = 7,
851 .dev = {
852 .platform_data = &spu1_platform_data,
853 },
854 .resource = spu1_resources,
855 .num_resources = ARRAY_SIZE(spu1_resources),
856};
857
858/* IPMMUI (an IPMMU module for ICB/LMB) */
859static struct resource ipmmu_resources[] = {
860 [0] = {
861 .name = "IPMMUI",
862 .start = 0xfe951000,
863 .end = 0xfe9510ff,
864 .flags = IORESOURCE_MEM,
865 },
866};
867
868static const char * const ipmmu_dev_names[] = {
869 "sh_mobile_lcdc_fb.0",
870 "sh_mobile_lcdc_fb.1",
871 "sh_mobile_ceu.0",
872 "uio_pdrv_genirq.0",
873 "uio_pdrv_genirq.1",
874 "uio_pdrv_genirq.2",
875 "uio_pdrv_genirq.3",
876 "uio_pdrv_genirq.4",
877 "uio_pdrv_genirq.5",
878};
879
880static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
881 .dev_names = ipmmu_dev_names,
882 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
883};
884
885static struct platform_device ipmmu_device = {
886 .name = "ipmmu",
887 .id = -1,
888 .dev = {
889 .platform_data = &ipmmu_platform_data,
890 },
891 .resource = ipmmu_resources,
892 .num_resources = ARRAY_SIZE(ipmmu_resources),
893};
894
895static struct platform_device *sh7372_early_devices[] __initdata = {
896 &scif0_device,
897 &scif1_device,
898 &scif2_device,
899 &scif3_device,
900 &scif4_device,
901 &scif5_device,
902 &scif6_device,
903 &cmt2_device,
904 &tmu0_device,
905 &ipmmu_device,
906};
907
908static struct platform_device *sh7372_late_devices[] __initdata = {
909 &iic0_device,
910 &iic1_device,
911 &dma0_device,
912 &dma1_device,
913 &dma2_device,
914 &usb_dma0_device,
915 &usb_dma1_device,
916 &vpu_device,
917 &veu0_device,
918 &veu1_device,
919 &veu2_device,
920 &veu3_device,
921 &jpu_device,
922 &spu0_device,
923 &spu1_device,
924};
925
926void __init sh7372_add_standard_devices(void)
927{
928 static struct pm_domain_device domain_devices[] __initdata = {
929 { "A3RV", &vpu_device, },
930 { "A4MP", &spu0_device, },
931 { "A4MP", &spu1_device, },
932 { "A3SP", &scif0_device, },
933 { "A3SP", &scif1_device, },
934 { "A3SP", &scif2_device, },
935 { "A3SP", &scif3_device, },
936 { "A3SP", &scif4_device, },
937 { "A3SP", &scif5_device, },
938 { "A3SP", &scif6_device, },
939 { "A3SP", &iic1_device, },
940 { "A3SP", &dma0_device, },
941 { "A3SP", &dma1_device, },
942 { "A3SP", &dma2_device, },
943 { "A3SP", &usb_dma0_device, },
944 { "A3SP", &usb_dma1_device, },
945 { "A4R", &iic0_device, },
946 { "A4R", &veu0_device, },
947 { "A4R", &veu1_device, },
948 { "A4R", &veu2_device, },
949 { "A4R", &veu3_device, },
950 { "A4R", &jpu_device, },
951 { "A4R", &tmu0_device, },
952 };
953
954 sh7372_init_pm_domains();
955
956 platform_add_devices(sh7372_early_devices,
957 ARRAY_SIZE(sh7372_early_devices));
958
959 platform_add_devices(sh7372_late_devices,
960 ARRAY_SIZE(sh7372_late_devices));
961
962 rmobile_add_devices_to_domains(domain_devices,
963 ARRAY_SIZE(domain_devices));
964}
965
966void __init sh7372_earlytimer_init(void)
967{
968 sh7372_clock_init();
969 shmobile_earlytimer_init();
970}
971
972void __init sh7372_add_early_devices(void)
973{
974 early_platform_add_devices(sh7372_early_devices,
975 ARRAY_SIZE(sh7372_early_devices));
976
977 /* setup early console here as well */
978 shmobile_setup_console();
979}
980
981#ifdef CONFIG_USE_OF
982
983void __init sh7372_add_early_devices_dt(void)
984{
985 shmobile_init_delay();
986
987 sh7372_add_early_devices();
988}
989
990void __init sh7372_add_standard_devices_dt(void)
991{
992 /* clocks are setup late during boot in the case of DT */
993 sh7372_clock_init();
994
995 platform_add_devices(sh7372_early_devices,
996 ARRAY_SIZE(sh7372_early_devices));
997
998 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
999}
1000
1001static const char *sh7372_boards_compat_dt[] __initdata = {
1002 "renesas,sh7372",
1003 NULL,
1004};
1005
1006DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1007 .map_io = sh7372_map_io,
1008 .init_early = sh7372_add_early_devices_dt,
1009 .init_irq = sh7372_init_irq,
1010 .handle_irq = shmobile_handle_irq_intc,
1011 .init_machine = sh7372_add_standard_devices_dt,
1012 .init_late = shmobile_init_late,
1013 .dt_compat = sh7372_boards_compat_dt,
1014MACHINE_END
1015
1016#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/sh7372.h b/arch/arm/mach-shmobile/sh7372.h
deleted file mode 100644
index 4ad960d5075b..000000000000
--- a/arch/arm/mach-shmobile/sh7372.h
+++ /dev/null
@@ -1,84 +0,0 @@
1/*
2 * Copyright (C) 2010 Renesas Solutions Corp.
3 *
4 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#ifndef __ASM_SH7372_H__
12#define __ASM_SH7372_H__
13
14/* DMA slave IDs */
15enum {
16 SHDMA_SLAVE_INVALID,
17 SHDMA_SLAVE_SCIF0_TX,
18 SHDMA_SLAVE_SCIF0_RX,
19 SHDMA_SLAVE_SCIF1_TX,
20 SHDMA_SLAVE_SCIF1_RX,
21 SHDMA_SLAVE_SCIF2_TX,
22 SHDMA_SLAVE_SCIF2_RX,
23 SHDMA_SLAVE_SCIF3_TX,
24 SHDMA_SLAVE_SCIF3_RX,
25 SHDMA_SLAVE_SCIF4_TX,
26 SHDMA_SLAVE_SCIF4_RX,
27 SHDMA_SLAVE_SCIF5_TX,
28 SHDMA_SLAVE_SCIF5_RX,
29 SHDMA_SLAVE_SCIF6_TX,
30 SHDMA_SLAVE_SCIF6_RX,
31 SHDMA_SLAVE_FLCTL0_TX,
32 SHDMA_SLAVE_FLCTL0_RX,
33 SHDMA_SLAVE_FLCTL1_TX,
34 SHDMA_SLAVE_FLCTL1_RX,
35 SHDMA_SLAVE_SDHI0_RX,
36 SHDMA_SLAVE_SDHI0_TX,
37 SHDMA_SLAVE_SDHI1_RX,
38 SHDMA_SLAVE_SDHI1_TX,
39 SHDMA_SLAVE_SDHI2_RX,
40 SHDMA_SLAVE_SDHI2_TX,
41 SHDMA_SLAVE_FSIA_RX,
42 SHDMA_SLAVE_FSIA_TX,
43 SHDMA_SLAVE_MMCIF_RX,
44 SHDMA_SLAVE_MMCIF_TX,
45 SHDMA_SLAVE_USB0_TX,
46 SHDMA_SLAVE_USB0_RX,
47 SHDMA_SLAVE_USB1_TX,
48 SHDMA_SLAVE_USB1_RX,
49};
50
51extern struct clk sh7372_extal1_clk;
52extern struct clk sh7372_extal2_clk;
53extern struct clk sh7372_dv_clki_clk;
54extern struct clk sh7372_dv_clki_div2_clk;
55extern struct clk sh7372_pllc2_clk;
56
57extern void sh7372_init_irq(void);
58extern void sh7372_map_io(void);
59extern void sh7372_earlytimer_init(void);
60extern void sh7372_add_early_devices(void);
61extern void sh7372_add_standard_devices(void);
62extern void sh7372_add_early_devices_dt(void);
63extern void sh7372_add_standard_devices_dt(void);
64extern void sh7372_clock_init(void);
65extern void sh7372_pinmux_init(void);
66extern void sh7372_pm_init(void);
67extern void sh7372_resume_core_standby_sysc(void);
68extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
69extern void sh7372_intcs_suspend(void);
70extern void sh7372_intcs_resume(void);
71extern void sh7372_intca_suspend(void);
72extern void sh7372_intca_resume(void);
73
74extern unsigned long sh7372_cpu_resume;
75
76#ifdef CONFIG_PM
77extern void __init sh7372_init_pm_domains(void);
78#else
79static inline void sh7372_init_pm_domains(void) {}
80#endif
81
82extern void __init sh7372_pm_init_late(void);
83
84#endif /* __ASM_SH7372_H__ */
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
deleted file mode 100644
index 146b8de16432..000000000000
--- a/arch/arm/mach-shmobile/sleep-sh7372.S
+++ /dev/null
@@ -1,98 +0,0 @@
1/*
2 * sh7372 lowlevel sleep code for "Core Standby Mode"
3 *
4 * Copyright (C) 2011 Magnus Damm
5 *
6 * In "Core Standby Mode" the ARM core is off, but L2 cache is still on
7 *
8 * Based on mach-omap2/sleep34xx.S
9 *
10 * (C) Copyright 2007 Texas Instruments
11 * Karthik Dasu <karthik-dp@ti.com>
12 *
13 * (C) Copyright 2004 Texas Instruments, <www.ti.com>
14 * Richard Woodruff <r-woodruff2@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
24 * GNU General Public License for more details.
25 */
26
27#include <linux/linkage.h>
28#include <linux/init.h>
29#include <asm/memory.h>
30#include <asm/assembler.h>
31
32#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
33 .align 12
34 .text
35 .global sh7372_resume_core_standby_sysc
36sh7372_resume_core_standby_sysc:
37 ldr pc, 1f
38
39 .align 2
40 .globl sh7372_cpu_resume
41sh7372_cpu_resume:
421: .space 4
43
44#define SPDCR 0xe6180008
45
46 /* A3SM & A4S power down */
47 .global sh7372_do_idle_sysc
48sh7372_do_idle_sysc:
49 mov r8, r0 /* sleep mode passed in r0 */
50
51 /*
52 * Clear the SCTLR.C bit to prevent further data cache
53 * allocation. Clearing SCTLR.C would make all the data accesses
54 * strongly ordered and would not hit the cache.
55 */
56 mrc p15, 0, r0, c1, c0, 0
57 bic r0, r0, #(1 << 2) @ Disable the C bit
58 mcr p15, 0, r0, c1, c0, 0
59 isb
60
61 /*
62 * Clean and invalidate data cache again.
63 */
64 ldr r1, kernel_flush
65 blx r1
66
67 /* disable L2 cache in the aux control register */
68 mrc p15, 0, r10, c1, c0, 1
69 bic r10, r10, #2
70 mcr p15, 0, r10, c1, c0, 1
71 isb
72
73 /*
74 * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
75 * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
76 * This sequence switches back to ARM. Note that .align may insert a
77 * nop: bx pc needs to be word-aligned in order to work.
78 */
79 THUMB( .thumb )
80 THUMB( .align )
81 THUMB( bx pc )
82 THUMB( nop )
83 .arm
84
85 /* Data memory barrier and Data sync barrier */
86 dsb
87 dmb
88
89 /* SYSC power down */
90 ldr r0, =SPDCR
91 str r8, [r0]
921:
93 b 1b
94
95 .align 2
96kernel_flush:
97 .word v7_flush_dcache_all
98#endif
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