diff options
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event_p6.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_p6.c b/arch/x86/kernel/cpu/perf_event_p6.c index 9582fcbcd8ec..7d0270bd793e 100644 --- a/arch/x86/kernel/cpu/perf_event_p6.c +++ b/arch/x86/kernel/cpu/perf_event_p6.c | |||
| @@ -157,25 +157,25 @@ static void p6_pmu_enable_all(int added) | |||
| 157 | static inline void | 157 | static inline void |
| 158 | p6_pmu_disable_event(struct perf_event *event) | 158 | p6_pmu_disable_event(struct perf_event *event) |
| 159 | { | 159 | { |
| 160 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | ||
| 161 | struct hw_perf_event *hwc = &event->hw; | 160 | struct hw_perf_event *hwc = &event->hw; |
| 162 | u64 val = P6_NOP_EVENT; | 161 | u64 val = P6_NOP_EVENT; |
| 163 | 162 | ||
| 164 | if (cpuc->enabled) | ||
| 165 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; | ||
| 166 | |||
| 167 | (void)wrmsrl_safe(hwc->config_base, val); | 163 | (void)wrmsrl_safe(hwc->config_base, val); |
| 168 | } | 164 | } |
| 169 | 165 | ||
| 170 | static void p6_pmu_enable_event(struct perf_event *event) | 166 | static void p6_pmu_enable_event(struct perf_event *event) |
| 171 | { | 167 | { |
| 172 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | ||
| 173 | struct hw_perf_event *hwc = &event->hw; | 168 | struct hw_perf_event *hwc = &event->hw; |
| 174 | u64 val; | 169 | u64 val; |
| 175 | 170 | ||
| 176 | val = hwc->config; | 171 | val = hwc->config; |
| 177 | if (cpuc->enabled) | 172 | |
| 178 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; | 173 | /* |
| 174 | * p6 only has a global event enable, set on PerfEvtSel0 | ||
| 175 | * We "disable" events by programming P6_NOP_EVENT | ||
| 176 | * and we rely on p6_pmu_enable_all() being called | ||
| 177 | * to actually enable the events. | ||
| 178 | */ | ||
| 179 | 179 | ||
| 180 | (void)wrmsrl_safe(hwc->config_base, val); | 180 | (void)wrmsrl_safe(hwc->config_base, val); |
| 181 | } | 181 | } |
