1 files changed, 0 insertions, 25 deletions

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index c3d92d537240..8045871335b5 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -17,7 +17,6 @@
 #include <drm/drm_encoder.h>
 #include <drm/drm_modes.h>
 #include <drm/drm_of.h>
-#include <drm/drm_panel.h>
 
 #include <uapi/drm/drm_mode.h>
 
@@ -350,9 +349,6 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
                                      const struct drm_display_mode *mode)
 {
-        struct drm_panel *panel = tcon->panel;
-        struct drm_connector *connector = panel->connector;
-        struct drm_display_info display_info = connector->display_info;
         unsigned int bp, hsync, vsync;
         u8 clk_delay;
         u32 val = 0;
@@ -410,27 +406,6 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
                 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
 
-        /*
-         * On A20 and similar SoCs, the only way to achieve Positive Edge
-         * (Rising Edge), is setting dclk clock phase to 2/3(240°).
-         * By default TCON works in Negative Edge(Falling Edge),
-         * this is why phase is set to 0 in that case.
-         * Unfortunately there's no way to logically invert dclk through
-         * IO_POL register.
-         * The only acceptable way to work, triple checked with scope,
-         * is using clock phase set to 0° for Negative Edge and set to 240°
-         * for Positive Edge.
-         * On A33 and similar SoCs there would be a 90° phase option,
-         * but it divides also dclk by 2.
-         * Following code is a way to avoid quirks all around TCON
-         * and DOTCLOCK drivers.
-         */
-        if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_POSEDGE)
-                clk_set_phase(tcon->dclk, 240);
-
-        if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
-                clk_set_phase(tcon->dclk, 0);
-
         regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
                            SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE,
                            val);