16 files changed, 127 insertions, 106 deletions

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 2e7ee0313c1c..e94d3ac2bdd0 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -341,10 +341,7 @@ GuC
 GuC-specific firmware loader
 ----------------------------
 
-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_loader.c
-   :doc: GuC-specific firmware loader
-
-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_loader.c
+.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fw.c
    :internal:
 
 GuC-based command submission
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index a9782b1aba47..34daf895f848 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -1360,7 +1360,7 @@ void dpp1_cm_set_output_csc_adjustment(
 
 void dpp1_cm_set_output_csc_default(
                 struct dpp *dpp_base,
-                const struct default_adjustment *default_adjust);
+                enum dc_color_space colorspace);
 
 void dpp1_cm_set_gamut_remap(
         struct dpp *dpp,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index 40627c244bf5..ed1216b53465 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -225,14 +225,13 @@ void dpp1_cm_set_gamut_remap(
 
 void dpp1_cm_set_output_csc_default(
                 struct dpp *dpp_base,
-                const struct default_adjustment *default_adjust)
+                enum dc_color_space colorspace)
 {
 
         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
         uint32_t ocsc_mode = 0;
 
-        if (default_adjust != NULL) {
-                switch (default_adjust->out_color_space) {
+        switch (colorspace) {
                 case COLOR_SPACE_SRGB:
                 case COLOR_SPACE_2020_RGB_FULLRANGE:
                         ocsc_mode = 0;
@@ -253,7 +252,6 @@ void dpp1_cm_set_output_csc_default(
                 case COLOR_SPACE_UNKNOWN:
                 default:
                         break;
-                }
         }
 
         REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 961ad5c3b454..05dc01e54531 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2097,6 +2097,8 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
                         tbl_entry.color_space = color_space;
                         //tbl_entry.regval = matrix;
                         pipe_ctx->plane_res.dpp->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry);
+        } else {
+                pipe_ctx->plane_res.dpp->funcs->opp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
         }
 }
 static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index 83a68460edcd..9420dfb94d39 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -64,7 +64,7 @@ struct dpp_funcs {
 
         void (*opp_set_csc_default)(
                 struct dpp *dpp,
-                const struct default_adjustment *default_adjust);
+                enum dc_color_space colorspace);
 
         void (*opp_set_csc_adjustment)(
                 struct dpp *dpp,
diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c
index 2e065facdce7..a0f4d2a2a481 100644
--- a/drivers/gpu/drm/armada/armada_crtc.c
+++ b/drivers/gpu/drm/armada/armada_crtc.c
@@ -168,16 +168,23 @@ static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
 void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb,
         int x, int y)
 {
+        const struct drm_format_info *format = fb->format;
+        unsigned int num_planes = format->num_planes;
         u32 addr = drm_fb_obj(fb)->dev_addr;
-        int num_planes = fb->format->num_planes;
         int i;
 
         if (num_planes > 3)
                 num_planes = 3;
 
-        for (i = 0; i < num_planes; i++)
+        addrs[0] = addr + fb->offsets[0] + y * fb->pitches[0] +
+                   x * format->cpp[0];
+
+        y /= format->vsub;
+        x /= format->hsub;
+
+        for (i = 1; i < num_planes; i++)
                 addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] +
-                             x * fb->format->cpp[i];
+                             x * format->cpp[i];
         for (; i < 3; i++)
                 addrs[i] = 0;
 }
@@ -744,15 +751,14 @@ void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc,
         if (plane->fb)
                 drm_framebuffer_put(plane->fb);
 
-        /* Power down the Y/U/V FIFOs */
-        sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66;
-
         /* Power down most RAMs and FIFOs if this is the primary plane */
         if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
-                sram_para1 |= CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
-                              CFG_PDWN32x32 | CFG_PDWN64x66;
+                sram_para1 = CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
+                             CFG_PDWN32x32 | CFG_PDWN64x66;
                 dma_ctrl0_mask = CFG_GRA_ENA;
         } else {
+                /* Power down the Y/U/V FIFOs */
+                sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66;
                 dma_ctrl0_mask = CFG_DMA_ENA;
         }
 
@@ -1225,17 +1231,13 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
 
         ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
                                dcrtc);
-        if (ret < 0) {
-                kfree(dcrtc);
-                return ret;
-        }
+        if (ret < 0)
+                goto err_crtc;
 
         if (dcrtc->variant->init) {
                 ret = dcrtc->variant->init(dcrtc, dev);
-                if (ret) {
-                        kfree(dcrtc);
-                        return ret;
-                }
+                if (ret)
+                        goto err_crtc;
         }
 
         /* Ensure AXI pipeline is enabled */
@@ -1246,13 +1248,15 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
         dcrtc->crtc.port = port;
 
         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
-        if (!primary)
-                return -ENOMEM;
+        if (!primary) {
+                ret = -ENOMEM;
+                goto err_crtc;
+        }
 
         ret = armada_drm_plane_init(primary);
         if (ret) {
                 kfree(primary);
-                return ret;
+                goto err_crtc;
         }
 
         ret = drm_universal_plane_init(drm, &primary->base, 0,
@@ -1263,7 +1267,7 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
                                        DRM_PLANE_TYPE_PRIMARY, NULL);
         if (ret) {
                 kfree(primary);
-                return ret;
+                goto err_crtc;
         }
 
         ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL,
@@ -1282,6 +1286,9 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
 
 err_crtc_init:
         primary->base.funcs->destroy(&primary->base);
+err_crtc:
+        kfree(dcrtc);
+
         return ret;
 }
 
diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h
index bab11f483575..bfd3514fbe9b 100644
--- a/drivers/gpu/drm/armada/armada_crtc.h
+++ b/drivers/gpu/drm/armada/armada_crtc.h
@@ -42,6 +42,8 @@ struct armada_plane_work {
 };
 
 struct armada_plane_state {
+        u16 src_x;
+        u16 src_y;
         u32 src_hw;
         u32 dst_hw;
         u32 dst_yx;
diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c
index b411b608821a..aba947696178 100644
--- a/drivers/gpu/drm/armada/armada_overlay.c
+++ b/drivers/gpu/drm/armada/armada_overlay.c
@@ -99,6 +99,7 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
 {
         struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
+        const struct drm_format_info *format;
         struct drm_rect src = {
                 .x1 = src_x,
                 .y1 = src_y,
@@ -117,7 +118,7 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
         };
         uint32_t val, ctrl0;
         unsigned idx = 0;
-        bool visible;
+        bool visible, fb_changed;
         int ret;
 
         trace_armada_ovl_plane_update(plane, crtc, fb,
@@ -138,6 +139,18 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
         if (!visible)
                 ctrl0 &= ~CFG_DMA_ENA;
 
+        /*
+         * Shifting a YUV packed format image by one pixel causes the U/V
+         * planes to swap.  Compensate for it by also toggling the UV swap.
+         */
+        format = fb->format;
+        if (format->num_planes == 1 && src.x1 >> 16 & (format->hsub - 1))
+                ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV);
+
+        fb_changed = plane->fb != fb ||
+                     dplane->base.state.src_x != src.x1 >> 16 ||
+                     dplane->base.state.src_y != src.y1 >> 16;
+
         if (!dcrtc->plane) {
                 dcrtc->plane = plane;
                 armada_ovl_update_attr(&dplane->prop, dcrtc);
@@ -145,7 +158,7 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
 
         /* FIXME: overlay on an interlaced display */
         /* Just updating the position/size? */
-        if (plane->fb == fb && dplane->base.state.ctrl0 == ctrl0) {
+        if (!fb_changed && dplane->base.state.ctrl0 == ctrl0) {
                 val = (drm_rect_height(&src) & 0xffff0000) |
                       drm_rect_width(&src) >> 16;
                 dplane->base.state.src_hw = val;
@@ -169,9 +182,8 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
         if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0)
                 armada_drm_plane_work_cancel(dcrtc, &dplane->base);
 
-        if (plane->fb != fb) {
-                u32 addrs[3], pixel_format;
-                int num_planes, hsub;
+        if (fb_changed) {
+                u32 addrs[3];
 
                 /*
                  * Take a reference on the new framebuffer - we want to
@@ -182,23 +194,11 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
                 if (plane->fb)
                         armada_ovl_retire_fb(dplane, plane->fb);
 
-                src_y = src.y1 >> 16;
-                src_x = src.x1 >> 16;
+                dplane->base.state.src_y = src_y = src.y1 >> 16;
+                dplane->base.state.src_x = src_x = src.x1 >> 16;
 
                 armada_drm_plane_calc_addrs(addrs, fb, src_x, src_y);
 
-                pixel_format = fb->format->format;
-                hsub = drm_format_horz_chroma_subsampling(pixel_format);
-                num_planes = fb->format->num_planes;
-
-                /*
-                 * Annoyingly, shifting a YUYV-format image by one pixel
-                 * causes the U/V planes to toggle.  Toggle the UV swap.
-                 * (Unfortunately, this causes momentary colour flickering.)
-                 */
-                if (src_x & (hsub - 1) && num_planes == 1)
-                        ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV);
-
                 armada_reg_queue_set(dplane->vbl.regs, idx, addrs[0],
                                      LCD_SPU_DMA_START_ADDR_Y0);
                 armada_reg_queue_set(dplane->vbl.regs, idx, addrs[1],
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 54b5d4c582b6..e143004e66d5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2368,6 +2368,9 @@ struct drm_i915_private {
          */
         struct workqueue_struct *wq;
 
+        /* ordered wq for modesets */
+        struct workqueue_struct *modeset_wq;
+
         /* Display functions */
         struct drm_i915_display_funcs display;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3866c49bc390..333f40bc03bb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6977,6 +6977,7 @@ enum {
 #define  RESET_PCH_HANDSHAKE_ENABLE     (1<<4)
 
 #define GEN8_CHICKEN_DCPR_1             _MMIO(0x46430)
+#define   SKL_SELECT_ALTERNATE_DC_EXIT  (1<<30)
 #define   MASK_WAKEMEM                  (1<<13)
 
 #define SKL_DFSM                        _MMIO(0x51000)
@@ -8522,6 +8523,7 @@ enum skl_power_gate {
 #define  BXT_CDCLK_CD2X_DIV_SEL_2       (2<<22)
 #define  BXT_CDCLK_CD2X_DIV_SEL_4       (3<<22)
 #define  BXT_CDCLK_CD2X_PIPE(pipe)      ((pipe)<<20)
+#define  CDCLK_DIVMUX_CD_OVERRIDE       (1<<19)
 #define  BXT_CDCLK_CD2X_PIPE_NONE       BXT_CDCLK_CD2X_PIPE(3)
 #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
 #define  CDCLK_FREQ_DECIMAL_MASK        (0x7ff)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index b2a6d62b71c0..60cf4e58389a 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -860,16 +860,10 @@ static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
 
 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 {
-        int min_cdclk = skl_calc_cdclk(0, vco);
         u32 val;
 
         WARN_ON(vco != 8100000 && vco != 8640000);
 
-        /* select the minimum CDCLK before enabling DPLL 0 */
-        val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
-        I915_WRITE(CDCLK_CTL, val);
-        POSTING_READ(CDCLK_CTL);
-
         /*
          * We always enable DPLL0 with the lowest link rate possible, but still
          * taking into account the VCO required to operate the eDP panel at the
@@ -923,7 +917,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 {
         int cdclk = cdclk_state->cdclk;
         int vco = cdclk_state->vco;
-        u32 freq_select, pcu_ack;
+        u32 freq_select, pcu_ack, cdclk_ctl;
         int ret;
 
         WARN_ON((cdclk == 24000) != (vco == 0));
@@ -940,7 +934,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
                 return;
         }
 
-        /* set CDCLK_CTL */
+        /* Choose frequency for this cdclk */
         switch (cdclk) {
         case 450000:
         case 432000:
@@ -968,10 +962,33 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
             dev_priv->cdclk.hw.vco != vco)
                 skl_dpll0_disable(dev_priv);
 
+        cdclk_ctl = I915_READ(CDCLK_CTL);
+
+        if (dev_priv->cdclk.hw.vco != vco) {
+                /* Wa Display #1183: skl,kbl,cfl */
+                cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
+                cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
+                I915_WRITE(CDCLK_CTL, cdclk_ctl);
+        }
+
+        /* Wa Display #1183: skl,kbl,cfl */
+        cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
+        I915_WRITE(CDCLK_CTL, cdclk_ctl);
+        POSTING_READ(CDCLK_CTL);
+
         if (dev_priv->cdclk.hw.vco != vco)
                 skl_dpll0_enable(dev_priv, vco);
 
-        I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
+        /* Wa Display #1183: skl,kbl,cfl */
+        cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
+        I915_WRITE(CDCLK_CTL, cdclk_ctl);
+
+        cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
+        I915_WRITE(CDCLK_CTL, cdclk_ctl);
+
+        /* Wa Display #1183: skl,kbl,cfl */
+        cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
+        I915_WRITE(CDCLK_CTL, cdclk_ctl);
         POSTING_READ(CDCLK_CTL);
 
         /* inform PCU of the change */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 30cf273d57aa..123585eeb87d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12544,11 +12544,15 @@ static int intel_atomic_commit(struct drm_device *dev,
         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
 
         i915_sw_fence_commit(&intel_state->commit_ready);
-        if (nonblock)
+        if (nonblock && intel_state->modeset) {
+                queue_work(dev_priv->modeset_wq, &state->commit_work);
+        } else if (nonblock) {
                 queue_work(system_unbound_wq, &state->commit_work);
-        else
+        } else {
+                if (intel_state->modeset)
+                        flush_workqueue(dev_priv->modeset_wq);
                 intel_atomic_commit_tail(state);
-
+        }
 
         return 0;
 }
@@ -14462,6 +14466,8 @@ int intel_modeset_init(struct drm_device *dev)
         enum pipe pipe;
         struct intel_crtc *crtc;
 
+        dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
+
         drm_mode_config_init(dev);
 
         dev->mode_config.min_width = 0;
@@ -15270,6 +15276,8 @@ void intel_modeset_cleanup(struct drm_device *dev)
         intel_cleanup_gt_powersave(dev_priv);
 
         intel_teardown_gmbus(dev_priv);
+
+        destroy_workqueue(dev_priv->modeset_wq);
 }
 
 void intel_connector_attach_encoder(struct intel_connector *connector,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 6e3b430fccdc..55ea5eb3b7df 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -590,7 +590,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
         struct drm_i915_private *dev_priv = to_i915(dev);
 
         if (dev_priv->psr.active) {
-                i915_reg_t psr_ctl;
+                i915_reg_t psr_status;
                 u32 psr_status_mask;
 
                 if (dev_priv->psr.aux_frame_sync)
@@ -599,24 +599,24 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
                                         0);
 
                 if (dev_priv->psr.psr2_support) {
-                        psr_ctl = EDP_PSR2_CTL;
+                        psr_status = EDP_PSR2_STATUS_CTL;
                         psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
 
-                        I915_WRITE(psr_ctl,
-                                   I915_READ(psr_ctl) &
+                        I915_WRITE(EDP_PSR2_CTL,
+                                   I915_READ(EDP_PSR2_CTL) &
                                    ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
 
                 } else {
-                        psr_ctl = EDP_PSR_STATUS_CTL;
+                        psr_status = EDP_PSR_STATUS_CTL;
                         psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
 
-                        I915_WRITE(psr_ctl,
-                                   I915_READ(psr_ctl) & ~EDP_PSR_ENABLE);
+                        I915_WRITE(EDP_PSR_CTL,
+                                   I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
                 }
 
                 /* Wait till PSR is idle */
                 if (intel_wait_for_register(dev_priv,
-                                            psr_ctl, psr_status_mask, 0,
+                                            psr_status, psr_status_mask, 0,
                                             2000))
                         DRM_ERROR("Timed out waiting for PSR Idle State\n");
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8af286c63d3b..7e115f3927f6 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -598,6 +598,11 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 
         DRM_DEBUG_KMS("Enabling DC5\n");
 
+        /* Wa Display #1183: skl,kbl,cfl */
+        if (IS_GEN9_BC(dev_priv))
+                I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
+                           SKL_SELECT_ALTERNATE_DC_EXIT);
+
         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 }
 
@@ -625,6 +630,11 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv)
 {
         DRM_DEBUG_KMS("Disabling DC6\n");
 
+        /* Wa Display #1183: skl,kbl,cfl */
+        if (IS_GEN9_BC(dev_priv))
+                I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
+                           SKL_SELECT_ALTERNATE_DC_EXIT);
+
         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 }
 
@@ -1786,6 +1796,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
         GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
         BIT_ULL(POWER_DOMAIN_MODESET) |                 \
         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
+        BIT_ULL(POWER_DOMAIN_GMBUS) |                   \
         BIT_ULL(POWER_DOMAIN_INIT))
 
 #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c b/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
index e626eddf24d5..23db74ae1826 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
@@ -78,6 +78,8 @@ static void hdmi_cec_received_msg(struct hdmi_core_data *core)
 
                         /* then read the message */
                         msg.len = cnt & 0xf;
+                        if (msg.len > CEC_MAX_MSG_SIZE - 2)
+                                msg.len = CEC_MAX_MSG_SIZE - 2;
                         msg.msg[0] = hdmi_read_reg(core->base,
                                                    HDMI_CEC_RX_CMD_HEADER);
                         msg.msg[1] = hdmi_read_reg(core->base,
@@ -104,26 +106,6 @@ static void hdmi_cec_received_msg(struct hdmi_core_data *core)
         }
 }
 
-static void hdmi_cec_transmit_fifo_empty(struct hdmi_core_data *core, u32 stat1)
-{
-        if (stat1 & 2) {
-                u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
-
-                cec_transmit_done(core->adap,
-                                  CEC_TX_STATUS_NACK |
-                                  CEC_TX_STATUS_MAX_RETRIES,
-                                  0, (dbg3 >> 4) & 7, 0, 0);
-        } else if (stat1 & 1) {
-                cec_transmit_done(core->adap,
-                                  CEC_TX_STATUS_ARB_LOST |
-                                  CEC_TX_STATUS_MAX_RETRIES,
-                                  0, 0, 0, 0);
-        } else if (stat1 == 0) {
-                cec_transmit_done(core->adap, CEC_TX_STATUS_OK,
-                                  0, 0, 0, 0);
-        }
-}
-
 void hdmi4_cec_irq(struct hdmi_core_data *core)
 {
         u32 stat0 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0);
@@ -132,27 +114,21 @@ void hdmi4_cec_irq(struct hdmi_core_data *core)
         hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0, stat0);
         hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, stat1);
 
-        if (stat0 & 0x40)
+        if (stat0 & 0x20) {
+                cec_transmit_done(core->adap, CEC_TX_STATUS_OK,
+                                  0, 0, 0, 0);
                 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
-        else if (stat0 & 0x24)
-                hdmi_cec_transmit_fifo_empty(core, stat1);
-        if (stat1 & 2) {
+        } else if (stat1 & 0x02) {
                 u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
 
                 cec_transmit_done(core->adap,
                                   CEC_TX_STATUS_NACK |
                                   CEC_TX_STATUS_MAX_RETRIES,
                                   0, (dbg3 >> 4) & 7, 0, 0);
-        } else if (stat1 & 1) {
-                cec_transmit_done(core->adap,
-                                  CEC_TX_STATUS_ARB_LOST |
-                                  CEC_TX_STATUS_MAX_RETRIES,
-                                  0, 0, 0, 0);
+                REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
         }
         if (stat0 & 0x02)
                 hdmi_cec_received_msg(core);
-        if (stat1 & 0x3)
-                REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
 }
 
 static bool hdmi_cec_clear_tx_fifo(struct cec_adapter *adap)
@@ -231,18 +207,14 @@ static int hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
         /*
          * Enable CEC interrupts:
          * Transmit Buffer Full/Empty Change event
-         * Transmitter FIFO Empty event
          * Receiver FIFO Not Empty event
          */
-        hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0x26);
+        hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0x22);
         /*
          * Enable CEC interrupts:
-         * RX FIFO Overrun Error event
-         * Short Pulse Detected event
          * Frame Retransmit Count Exceeded event
-         * Start Bit Irregularity event
          */
-        hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0x0f);
+        hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0x02);
 
         /* cec calibration enable (self clearing) */
         hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x03);
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index b5ba6441489f..5d252fb27a82 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -1007,6 +1007,8 @@ int ttm_page_alloc_init(struct ttm_mem_global *glob, unsigned max_pages)
         pr_info("Initializing pool allocator\n");
 
         _manager = kzalloc(sizeof(*_manager), GFP_KERNEL);
+        if (!_manager)
+                return -ENOMEM;
 
         ttm_page_pool_init_locked(&_manager->wc_pool, GFP_HIGHUSER, "wc", 0);