diff options
-rw-r--r-- | include/linux/lockref.h | 7 | ||||
-rw-r--r-- | lib/Kconfig | 7 | ||||
-rw-r--r-- | lib/lockref.c | 2 |
3 files changed, 7 insertions, 9 deletions
diff --git a/include/linux/lockref.h b/include/linux/lockref.h index 13dfd36a3294..c8929c3832db 100644 --- a/include/linux/lockref.h +++ b/include/linux/lockref.h | |||
@@ -15,10 +15,15 @@ | |||
15 | */ | 15 | */ |
16 | 16 | ||
17 | #include <linux/spinlock.h> | 17 | #include <linux/spinlock.h> |
18 | #include <generated/bounds.h> | ||
19 | |||
20 | #define USE_CMPXCHG_LOCKREF \ | ||
21 | (IS_ENABLED(CONFIG_ARCH_USE_CMPXCHG_LOCKREF) && \ | ||
22 | IS_ENABLED(CONFIG_SMP) && !BLOATED_SPINLOCKS) | ||
18 | 23 | ||
19 | struct lockref { | 24 | struct lockref { |
20 | union { | 25 | union { |
21 | #ifdef CONFIG_CMPXCHG_LOCKREF | 26 | #if USE_CMPXCHG_LOCKREF |
22 | aligned_u64 lock_count; | 27 | aligned_u64 lock_count; |
23 | #endif | 28 | #endif |
24 | struct { | 29 | struct { |
diff --git a/lib/Kconfig b/lib/Kconfig index 75485e163ca3..06dc74200a51 100644 --- a/lib/Kconfig +++ b/lib/Kconfig | |||
@@ -51,13 +51,6 @@ config PERCPU_RWSEM | |||
51 | config ARCH_USE_CMPXCHG_LOCKREF | 51 | config ARCH_USE_CMPXCHG_LOCKREF |
52 | bool | 52 | bool |
53 | 53 | ||
54 | config CMPXCHG_LOCKREF | ||
55 | def_bool y if ARCH_USE_CMPXCHG_LOCKREF | ||
56 | depends on SMP | ||
57 | depends on !GENERIC_LOCKBREAK | ||
58 | depends on !DEBUG_SPINLOCK | ||
59 | depends on !DEBUG_LOCK_ALLOC | ||
60 | |||
61 | config CRC_CCITT | 54 | config CRC_CCITT |
62 | tristate "CRC-CCITT functions" | 55 | tristate "CRC-CCITT functions" |
63 | help | 56 | help |
diff --git a/lib/lockref.c b/lib/lockref.c index af6e95d0bed6..d2b123f8456b 100644 --- a/lib/lockref.c +++ b/lib/lockref.c | |||
@@ -1,7 +1,7 @@ | |||
1 | #include <linux/export.h> | 1 | #include <linux/export.h> |
2 | #include <linux/lockref.h> | 2 | #include <linux/lockref.h> |
3 | 3 | ||
4 | #ifdef CONFIG_CMPXCHG_LOCKREF | 4 | #if USE_CMPXCHG_LOCKREF |
5 | 5 | ||
6 | /* | 6 | /* |
7 | * Allow weakly-ordered memory architectures to provide barrier-less | 7 | * Allow weakly-ordered memory architectures to provide barrier-less |