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-rw-r--r--arch/mips/mm/c-r4k.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 6f534b209971..e12dfa48b478 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -851,9 +851,12 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
851 /* 851 /*
852 * Either no secondary cache or the available caches don't have the 852 * Either no secondary cache or the available caches don't have the
853 * subset property so we have to flush the primary caches 853 * subset property so we have to flush the primary caches
854 * explicitly 854 * explicitly.
855 * If we would need IPI to perform an INDEX-type operation, then
856 * we have to use the HIT-type alternative as IPI cannot be used
857 * here due to interrupts possibly being disabled.
855 */ 858 */
856 if (size >= dcache_size) { 859 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
857 r4k_blast_dcache(); 860 r4k_blast_dcache();
858 } else { 861 } else {
859 R4600_HIT_CACHEOP_WAR_IMPL; 862 R4600_HIT_CACHEOP_WAR_IMPL;
@@ -890,7 +893,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
890 return; 893 return;
891 } 894 }
892 895
893 if (size >= dcache_size) { 896 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
894 r4k_blast_dcache(); 897 r4k_blast_dcache();
895 } else { 898 } else {
896 R4600_HIT_CACHEOP_WAR_IMPL; 899 R4600_HIT_CACHEOP_WAR_IMPL;