aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/gpu/drm/amd/acp/Kconfig1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h16
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_job.c15
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h19
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c116
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_sdma.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cikd.h3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c28
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c22
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vid.h2
-rw-r--r--drivers/gpu/drm/amd/include/amd_acpi.h2
-rw-r--r--drivers/gpu/drm/amd/powerplay/amd_powerplay.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_acpi.h2
18 files changed, 131 insertions, 121 deletions
diff --git a/drivers/gpu/drm/amd/acp/Kconfig b/drivers/gpu/drm/amd/acp/Kconfig
index 2b07813bceed..0f734ee05274 100644
--- a/drivers/gpu/drm/amd/acp/Kconfig
+++ b/drivers/gpu/drm/amd/acp/Kconfig
@@ -2,7 +2,6 @@ menu "ACP Configuration"
2 2
3config DRM_AMD_ACP 3config DRM_AMD_ACP
4 bool "Enable ACP IP support" 4 bool "Enable ACP IP support"
5 default y
6 select MFD_CORE 5 select MFD_CORE
7 select PM_GENERIC_DOMAINS if PM 6 select PM_GENERIC_DOMAINS if PM
8 help 7 help
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f5bac97a438b..0c42a85ca5a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -769,8 +769,9 @@ struct amdgpu_ib {
769 uint32_t *ptr; 769 uint32_t *ptr;
770 struct amdgpu_fence *fence; 770 struct amdgpu_fence *fence;
771 struct amdgpu_user_fence *user; 771 struct amdgpu_user_fence *user;
772 bool grabbed_vmid;
773 struct amdgpu_vm *vm; 772 struct amdgpu_vm *vm;
773 unsigned vm_id;
774 uint64_t vm_pd_addr;
774 struct amdgpu_ctx *ctx; 775 struct amdgpu_ctx *ctx;
775 uint32_t gds_base, gds_size; 776 uint32_t gds_base, gds_size;
776 uint32_t gws_base, gws_size; 777 uint32_t gws_base, gws_size;
@@ -877,10 +878,10 @@ struct amdgpu_vm_pt {
877}; 878};
878 879
879struct amdgpu_vm_id { 880struct amdgpu_vm_id {
880 unsigned id; 881 struct amdgpu_vm_manager_id *mgr_id;
881 uint64_t pd_gpu_addr; 882 uint64_t pd_gpu_addr;
882 /* last flushed PD/PT update */ 883 /* last flushed PD/PT update */
883 struct fence *flushed_updates; 884 struct fence *flushed_updates;
884}; 885};
885 886
886struct amdgpu_vm { 887struct amdgpu_vm {
@@ -954,10 +955,11 @@ void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
954void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, 955void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
955 struct amdgpu_vm *vm); 956 struct amdgpu_vm *vm);
956int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 957int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
957 struct amdgpu_sync *sync, struct fence *fence); 958 struct amdgpu_sync *sync, struct fence *fence,
959 unsigned *vm_id, uint64_t *vm_pd_addr);
958void amdgpu_vm_flush(struct amdgpu_ring *ring, 960void amdgpu_vm_flush(struct amdgpu_ring *ring,
959 struct amdgpu_vm *vm, 961 unsigned vmid,
960 struct fence *updates); 962 uint64_t pd_addr);
961uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 963uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
962int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 964int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
963 struct amdgpu_vm *vm); 965 struct amdgpu_vm *vm);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 9f8cfaab3004..d6b0bff510aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -240,12 +240,10 @@ static int acp_poweron(struct generic_pm_domain *genpd)
240static struct device *get_mfd_cell_dev(const char *device_name, int r) 240static struct device *get_mfd_cell_dev(const char *device_name, int r)
241{ 241{
242 char auto_dev_name[25]; 242 char auto_dev_name[25];
243 char buf[8];
244 struct device *dev; 243 struct device *dev;
245 244
246 sprintf(buf, ".%d.auto", r); 245 snprintf(auto_dev_name, sizeof(auto_dev_name),
247 strcpy(auto_dev_name, device_name); 246 "%s.%d.auto", device_name, r);
248 strcat(auto_dev_name, buf);
249 dev = bus_find_device_by_name(&platform_bus_type, NULL, auto_dev_name); 247 dev = bus_find_device_by_name(&platform_bus_type, NULL, auto_dev_name);
250 dev_info(dev, "device %s added to pm domain\n", auto_dev_name); 248 dev_info(dev, "device %s added to pm domain\n", auto_dev_name);
251 249
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
index 90d6fc1618aa..4792f9d0b7d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
@@ -118,6 +118,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
118 usermm = amdgpu_ttm_tt_get_usermm(entry->robj->tbo.ttm); 118 usermm = amdgpu_ttm_tt_get_usermm(entry->robj->tbo.ttm);
119 if (usermm) { 119 if (usermm) {
120 if (usermm != current->mm) { 120 if (usermm != current->mm) {
121 amdgpu_bo_unref(&entry->robj);
121 r = -EPERM; 122 r = -EPERM;
122 goto error_free; 123 goto error_free;
123 } 124 }
@@ -151,6 +152,8 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
151 return 0; 152 return 0;
152 153
153error_free: 154error_free:
155 while (i--)
156 amdgpu_bo_unref(&array[i].robj);
154 drm_free_large(array); 157 drm_free_large(array);
155 return r; 158 return r;
156} 159}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index b5bdd5d59b58..db14a7bbb8f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -75,6 +75,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
75 } 75 }
76 76
77 ib->vm = vm; 77 ib->vm = vm;
78 ib->vm_id = 0;
78 79
79 return 0; 80 return 0;
80} 81}
@@ -139,7 +140,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
139 return -EINVAL; 140 return -EINVAL;
140 } 141 }
141 142
142 if (vm && !ibs->grabbed_vmid) { 143 if (vm && !ibs->vm_id) {
143 dev_err(adev->dev, "VM IB without ID\n"); 144 dev_err(adev->dev, "VM IB without ID\n");
144 return -EINVAL; 145 return -EINVAL;
145 } 146 }
@@ -152,10 +153,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
152 153
153 if (vm) { 154 if (vm) {
154 /* do context switch */ 155 /* do context switch */
155 amdgpu_vm_flush(ring, vm, last_vm_update); 156 amdgpu_vm_flush(ring, ib->vm_id, ib->vm_pd_addr);
156 157
157 if (ring->funcs->emit_gds_switch) 158 if (ring->funcs->emit_gds_switch)
158 amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id, 159 amdgpu_ring_emit_gds_switch(ring, ib->vm_id,
159 ib->gds_base, ib->gds_size, 160 ib->gds_base, ib->gds_size,
160 ib->gws_base, ib->gws_size, 161 ib->gws_base, ib->gws_size,
161 ib->oa_base, ib->oa_size); 162 ib->oa_base, ib->oa_size);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index f29bbb96a881..90e52f7e17a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -105,16 +105,23 @@ static struct fence *amdgpu_job_dependency(struct amd_sched_job *sched_job)
105 105
106 struct fence *fence = amdgpu_sync_get_fence(&job->sync); 106 struct fence *fence = amdgpu_sync_get_fence(&job->sync);
107 107
108 if (fence == NULL && vm && !job->ibs->grabbed_vmid) { 108 if (fence == NULL && vm && !job->ibs->vm_id) {
109 struct amdgpu_ring *ring = job->ring; 109 struct amdgpu_ring *ring = job->ring;
110 unsigned i, vm_id;
111 uint64_t vm_pd_addr;
110 int r; 112 int r;
111 113
112 r = amdgpu_vm_grab_id(vm, ring, &job->sync, 114 r = amdgpu_vm_grab_id(vm, ring, &job->sync,
113 &job->base.s_fence->base); 115 &job->base.s_fence->base,
116 &vm_id, &vm_pd_addr);
114 if (r) 117 if (r)
115 DRM_ERROR("Error getting VM ID (%d)\n", r); 118 DRM_ERROR("Error getting VM ID (%d)\n", r);
116 else 119 else {
117 job->ibs->grabbed_vmid = true; 120 for (i = 0; i < job->num_ibs; ++i) {
121 job->ibs[i].vm_id = vm_id;
122 job->ibs[i].vm_pd_addr = vm_pd_addr;
123 }
124 }
118 125
119 fence = amdgpu_sync_get_fence(&job->sync); 126 fence = amdgpu_sync_get_fence(&job->sync);
120 } 127 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 9ca3735c563c..26a5f4acf584 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -100,21 +100,24 @@ TRACE_EVENT(amdgpu_sched_run_job,
100 100
101 101
102TRACE_EVENT(amdgpu_vm_grab_id, 102TRACE_EVENT(amdgpu_vm_grab_id,
103 TP_PROTO(struct amdgpu_vm *vm, unsigned vmid, int ring), 103 TP_PROTO(struct amdgpu_vm *vm, int ring, unsigned vmid,
104 TP_ARGS(vm, vmid, ring), 104 uint64_t pd_addr),
105 TP_ARGS(vm, ring, vmid, pd_addr),
105 TP_STRUCT__entry( 106 TP_STRUCT__entry(
106 __field(struct amdgpu_vm *, vm) 107 __field(struct amdgpu_vm *, vm)
107 __field(u32, vmid)
108 __field(u32, ring) 108 __field(u32, ring)
109 __field(u32, vmid)
110 __field(u64, pd_addr)
109 ), 111 ),
110 112
111 TP_fast_assign( 113 TP_fast_assign(
112 __entry->vm = vm; 114 __entry->vm = vm;
113 __entry->vmid = vmid;
114 __entry->ring = ring; 115 __entry->ring = ring;
116 __entry->vmid = vmid;
117 __entry->pd_addr = pd_addr;
115 ), 118 ),
116 TP_printk("vm=%p, id=%u, ring=%u", __entry->vm, __entry->vmid, 119 TP_printk("vm=%p, ring=%u, id=%u, pd_addr=%010Lx", __entry->vm,
117 __entry->ring) 120 __entry->ring, __entry->vmid, __entry->pd_addr)
118); 121);
119 122
120TRACE_EVENT(amdgpu_vm_bo_map, 123TRACE_EVENT(amdgpu_vm_bo_map,
@@ -231,8 +234,8 @@ TRACE_EVENT(amdgpu_vm_flush,
231 __entry->ring = ring; 234 __entry->ring = ring;
232 __entry->id = id; 235 __entry->id = id;
233 ), 236 ),
234 TP_printk("pd_addr=%010Lx, ring=%u, id=%u", 237 TP_printk("ring=%u, id=%u, pd_addr=%010Lx",
235 __entry->pd_addr, __entry->ring, __entry->id) 238 __entry->ring, __entry->id, __entry->pd_addr)
236); 239);
237 240
238TRACE_EVENT(amdgpu_bo_list_set, 241TRACE_EVENT(amdgpu_bo_list_set,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 264c5968a1d3..d9dc8bea5e98 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -50,6 +50,9 @@
50 * SI supports 16. 50 * SI supports 16.
51 */ 51 */
52 52
53/* Special value that no flush is necessary */
54#define AMDGPU_VM_NO_FLUSH (~0ll)
55
53/** 56/**
54 * amdgpu_vm_num_pde - return the number of page directory entries 57 * amdgpu_vm_num_pde - return the number of page directory entries
55 * 58 *
@@ -157,50 +160,70 @@ void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
157 * Allocate an id for the vm, adding fences to the sync obj as necessary. 160 * Allocate an id for the vm, adding fences to the sync obj as necessary.
158 */ 161 */
159int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 162int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
160 struct amdgpu_sync *sync, struct fence *fence) 163 struct amdgpu_sync *sync, struct fence *fence,
164 unsigned *vm_id, uint64_t *vm_pd_addr)
161{ 165{
162 struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; 166 uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
163 struct amdgpu_device *adev = ring->adev; 167 struct amdgpu_device *adev = ring->adev;
164 struct amdgpu_vm_manager_id *id; 168 struct amdgpu_vm_id *id = &vm->ids[ring->idx];
169 struct fence *updates = sync->last_vm_update;
165 int r; 170 int r;
166 171
167 mutex_lock(&adev->vm_manager.lock); 172 mutex_lock(&adev->vm_manager.lock);
168 173
169 /* check if the id is still valid */ 174 /* check if the id is still valid */
170 if (vm_id->id) { 175 if (id->mgr_id) {
176 struct fence *flushed = id->flushed_updates;
177 bool is_later;
171 long owner; 178 long owner;
172 179
173 id = &adev->vm_manager.ids[vm_id->id]; 180 if (!flushed)
174 owner = atomic_long_read(&id->owner); 181 is_later = true;
175 if (owner == (long)vm) { 182 else if (!updates)
176 list_move_tail(&id->list, &adev->vm_manager.ids_lru); 183 is_later = false;
177 trace_amdgpu_vm_grab_id(vm, vm_id->id, ring->idx); 184 else
185 is_later = fence_is_later(updates, flushed);
186
187 owner = atomic_long_read(&id->mgr_id->owner);
188 if (!is_later && owner == (long)id &&
189 pd_addr == id->pd_gpu_addr) {
190
191 fence_put(id->mgr_id->active);
192 id->mgr_id->active = fence_get(fence);
193
194 list_move_tail(&id->mgr_id->list,
195 &adev->vm_manager.ids_lru);
178 196
179 fence_put(id->active); 197 *vm_id = id->mgr_id - adev->vm_manager.ids;
180 id->active = fence_get(fence); 198 *vm_pd_addr = AMDGPU_VM_NO_FLUSH;
199 trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id,
200 *vm_pd_addr);
181 201
182 mutex_unlock(&adev->vm_manager.lock); 202 mutex_unlock(&adev->vm_manager.lock);
183 return 0; 203 return 0;
184 } 204 }
185 } 205 }
186 206
187 /* we definately need to flush */ 207 id->mgr_id = list_first_entry(&adev->vm_manager.ids_lru,
188 vm_id->pd_gpu_addr = ~0ll; 208 struct amdgpu_vm_manager_id,
209 list);
189 210
190 id = list_first_entry(&adev->vm_manager.ids_lru, 211 r = amdgpu_sync_fence(ring->adev, sync, id->mgr_id->active);
191 struct amdgpu_vm_manager_id, 212 if (!r) {
192 list); 213 fence_put(id->mgr_id->active);
193 list_move_tail(&id->list, &adev->vm_manager.ids_lru); 214 id->mgr_id->active = fence_get(fence);
194 atomic_long_set(&id->owner, (long)vm);
195 215
196 vm_id->id = id - adev->vm_manager.ids; 216 fence_put(id->flushed_updates);
197 trace_amdgpu_vm_grab_id(vm, vm_id->id, ring->idx); 217 id->flushed_updates = fence_get(updates);
198 218
199 r = amdgpu_sync_fence(ring->adev, sync, id->active); 219 id->pd_gpu_addr = pd_addr;
200 220
201 if (!r) { 221 list_move_tail(&id->mgr_id->list, &adev->vm_manager.ids_lru);
202 fence_put(id->active); 222 atomic_long_set(&id->mgr_id->owner, (long)id);
203 id->active = fence_get(fence); 223
224 *vm_id = id->mgr_id - adev->vm_manager.ids;
225 *vm_pd_addr = pd_addr;
226 trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr);
204 } 227 }
205 228
206 mutex_unlock(&adev->vm_manager.lock); 229 mutex_unlock(&adev->vm_manager.lock);
@@ -211,35 +234,18 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
211 * amdgpu_vm_flush - hardware flush the vm 234 * amdgpu_vm_flush - hardware flush the vm
212 * 235 *
213 * @ring: ring to use for flush 236 * @ring: ring to use for flush
214 * @vm: vm we want to flush 237 * @vmid: vmid number to use
215 * @updates: last vm update that we waited for 238 * @pd_addr: address of the page directory
216 * 239 *
217 * Flush the vm. 240 * Emit a VM flush when it is necessary.
218 */ 241 */
219void amdgpu_vm_flush(struct amdgpu_ring *ring, 242void amdgpu_vm_flush(struct amdgpu_ring *ring,
220 struct amdgpu_vm *vm, 243 unsigned vmid,
221 struct fence *updates) 244 uint64_t pd_addr)
222{ 245{
223 uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); 246 if (pd_addr != AMDGPU_VM_NO_FLUSH) {
224 struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; 247 trace_amdgpu_vm_flush(pd_addr, ring->idx, vmid);
225 struct fence *flushed_updates = vm_id->flushed_updates; 248 amdgpu_ring_emit_vm_flush(ring, vmid, pd_addr);
226 bool is_later;
227
228 if (!flushed_updates)
229 is_later = true;
230 else if (!updates)
231 is_later = false;
232 else
233 is_later = fence_is_later(updates, flushed_updates);
234
235 if (pd_addr != vm_id->pd_gpu_addr || is_later) {
236 trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id->id);
237 if (is_later) {
238 vm_id->flushed_updates = fence_get(updates);
239 fence_put(flushed_updates);
240 }
241 vm_id->pd_gpu_addr = pd_addr;
242 amdgpu_ring_emit_vm_flush(ring, vm_id->id, vm_id->pd_gpu_addr);
243 } 249 }
244} 250}
245 251
@@ -1284,7 +1290,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1284 int i, r; 1290 int i, r;
1285 1291
1286 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 1292 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1287 vm->ids[i].id = 0; 1293 vm->ids[i].mgr_id = NULL;
1288 vm->ids[i].flushed_updates = NULL; 1294 vm->ids[i].flushed_updates = NULL;
1289 } 1295 }
1290 vm->va = RB_ROOT; 1296 vm->va = RB_ROOT;
@@ -1381,13 +1387,13 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1381 amdgpu_bo_unref(&vm->page_directory); 1387 amdgpu_bo_unref(&vm->page_directory);
1382 fence_put(vm->page_directory_fence); 1388 fence_put(vm->page_directory_fence);
1383 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 1389 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1384 unsigned id = vm->ids[i].id; 1390 struct amdgpu_vm_id *id = &vm->ids[i];
1385 1391
1386 atomic_long_cmpxchg(&adev->vm_manager.ids[id].owner, 1392 if (id->mgr_id)
1387 (long)vm, 0); 1393 atomic_long_cmpxchg(&id->mgr_id->owner,
1388 fence_put(vm->ids[i].flushed_updates); 1394 (long)id, 0);
1395 fence_put(id->flushed_updates);
1389 } 1396 }
1390
1391} 1397}
1392 1398
1393/** 1399/**
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 675f34916aab..e4e4b2ac77b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -212,7 +212,7 @@ static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
212static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, 212static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
213 struct amdgpu_ib *ib) 213 struct amdgpu_ib *ib)
214{ 214{
215 u32 extra_bits = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; 215 u32 extra_bits = ib->vm_id & 0xf;
216 u32 next_rptr = ring->wptr + 5; 216 u32 next_rptr = ring->wptr + 5;
217 217
218 while ((next_rptr & 7) != 4) 218 while ((next_rptr & 7) != 4)
diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h
index 7f6d457f250a..60d4493206dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/cikd.h
+++ b/drivers/gpu/drm/amd/amdgpu/cikd.h
@@ -46,9 +46,6 @@
46#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 46#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
47#define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 47#define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003
48 48
49#define CIK_RB_BITMAP_WIDTH_PER_SH 2
50#define HAWAII_RB_BITMAP_WIDTH_PER_SH 4
51
52#define AMDGPU_NUM_OF_VMIDS 8 49#define AMDGPU_NUM_OF_VMIDS 8
53 50
54#define PIPEID(x) ((x) << 0) 51#define PIPEID(x) ((x) << 0)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 250bcbce7fdc..8fb7ebf3be3e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1635,30 +1635,25 @@ static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1635static void gfx_v7_0_setup_rb(struct amdgpu_device *adev) 1635static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
1636{ 1636{
1637 int i, j; 1637 int i, j;
1638 u32 data, tmp, num_rbs = 0; 1638 u32 data;
1639 u32 active_rbs = 0; 1639 u32 active_rbs = 0;
1640 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1641 adev->gfx.config.max_sh_per_se;
1640 1642
1641 mutex_lock(&adev->grbm_idx_mutex); 1643 mutex_lock(&adev->grbm_idx_mutex);
1642 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1644 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1643 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1645 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1644 gfx_v7_0_select_se_sh(adev, i, j); 1646 gfx_v7_0_select_se_sh(adev, i, j);
1645 data = gfx_v7_0_get_rb_active_bitmap(adev); 1647 data = gfx_v7_0_get_rb_active_bitmap(adev);
1646 if (adev->asic_type == CHIP_HAWAII) 1648 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1647 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1649 rb_bitmap_width_per_sh);
1648 HAWAII_RB_BITMAP_WIDTH_PER_SH);
1649 else
1650 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1651 CIK_RB_BITMAP_WIDTH_PER_SH);
1652 } 1650 }
1653 } 1651 }
1654 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 1652 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1655 mutex_unlock(&adev->grbm_idx_mutex); 1653 mutex_unlock(&adev->grbm_idx_mutex);
1656 1654
1657 adev->gfx.config.backend_enable_mask = active_rbs; 1655 adev->gfx.config.backend_enable_mask = active_rbs;
1658 tmp = active_rbs; 1656 adev->gfx.config.num_rbs = hweight32(active_rbs);
1659 while (tmp >>= 1)
1660 num_rbs++;
1661 adev->gfx.config.num_rbs = num_rbs;
1662} 1657}
1663 1658
1664/** 1659/**
@@ -2046,8 +2041,7 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2046 else 2041 else
2047 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 2042 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2048 2043
2049 control |= ib->length_dw | 2044 control |= ib->length_dw | (ib->vm_id << 24);
2050 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
2051 2045
2052 amdgpu_ring_write(ring, header); 2046 amdgpu_ring_write(ring, header);
2053 amdgpu_ring_write(ring, 2047 amdgpu_ring_write(ring,
@@ -2075,8 +2069,7 @@ static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2075 2069
2076 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 2070 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2077 2071
2078 control |= ib->length_dw | 2072 control |= ib->length_dw | (ib->vm_id << 24);
2079 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
2080 2073
2081 amdgpu_ring_write(ring, header); 2074 amdgpu_ring_write(ring, header);
2082 amdgpu_ring_write(ring, 2075 amdgpu_ring_write(ring,
@@ -3825,8 +3818,7 @@ static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3825 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3818 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3826 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3819 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3827 3820
3828 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se / 3821 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
3829 adev->gfx.config.max_sh_per_se);
3830 3822
3831 return (~data) & mask; 3823 return (~data) & mask;
3832} 3824}
@@ -5237,6 +5229,8 @@ int gfx_v7_0_get_cu_info(struct amdgpu_device *adev,
5237 if (!adev || !cu_info) 5229 if (!adev || !cu_info)
5238 return -EINVAL; 5230 return -EINVAL;
5239 5231
5232 memset(cu_info, 0, sizeof(*cu_info));
5233
5240 mutex_lock(&adev->grbm_idx_mutex); 5234 mutex_lock(&adev->grbm_idx_mutex);
5241 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5235 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5242 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5236 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 10c865087d0a..e37378fe1edc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -2613,8 +2613,10 @@ static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
2613static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) 2613static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
2614{ 2614{
2615 int i, j; 2615 int i, j;
2616 u32 data, tmp, num_rbs = 0; 2616 u32 data;
2617 u32 active_rbs = 0; 2617 u32 active_rbs = 0;
2618 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
2619 adev->gfx.config.max_sh_per_se;
2618 2620
2619 mutex_lock(&adev->grbm_idx_mutex); 2621 mutex_lock(&adev->grbm_idx_mutex);
2620 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2622 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
@@ -2622,17 +2624,14 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
2622 gfx_v8_0_select_se_sh(adev, i, j); 2624 gfx_v8_0_select_se_sh(adev, i, j);
2623 data = gfx_v8_0_get_rb_active_bitmap(adev); 2625 data = gfx_v8_0_get_rb_active_bitmap(adev);
2624 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 2626 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
2625 RB_BITMAP_WIDTH_PER_SH); 2627 rb_bitmap_width_per_sh);
2626 } 2628 }
2627 } 2629 }
2628 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 2630 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2629 mutex_unlock(&adev->grbm_idx_mutex); 2631 mutex_unlock(&adev->grbm_idx_mutex);
2630 2632
2631 adev->gfx.config.backend_enable_mask = active_rbs; 2633 adev->gfx.config.backend_enable_mask = active_rbs;
2632 tmp = active_rbs; 2634 adev->gfx.config.num_rbs = hweight32(active_rbs);
2633 while (tmp >>= 1)
2634 num_rbs++;
2635 adev->gfx.config.num_rbs = num_rbs;
2636} 2635}
2637 2636
2638/** 2637/**
@@ -4622,8 +4621,7 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4622 else 4621 else
4623 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4622 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4624 4623
4625 control |= ib->length_dw | 4624 control |= ib->length_dw | (ib->vm_id << 24);
4626 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
4627 4625
4628 amdgpu_ring_write(ring, header); 4626 amdgpu_ring_write(ring, header);
4629 amdgpu_ring_write(ring, 4627 amdgpu_ring_write(ring,
@@ -4652,8 +4650,7 @@ static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4652 4650
4653 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4651 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4654 4652
4655 control |= ib->length_dw | 4653 control |= ib->length_dw | (ib->vm_id << 24);
4656 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
4657 4654
4658 amdgpu_ring_write(ring, header); 4655 amdgpu_ring_write(ring, header);
4659 amdgpu_ring_write(ring, 4656 amdgpu_ring_write(ring,
@@ -5131,8 +5128,7 @@ static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
5131 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 5128 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
5132 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 5129 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
5133 5130
5134 mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_backends_per_se / 5131 mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
5135 adev->gfx.config.max_sh_per_se);
5136 5132
5137 return (~data) & mask; 5133 return (~data) & mask;
5138} 5134}
@@ -5146,6 +5142,8 @@ int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
5146 if (!adev || !cu_info) 5142 if (!adev || !cu_info)
5147 return -EINVAL; 5143 return -EINVAL;
5148 5144
5145 memset(cu_info, 0, sizeof(*cu_info));
5146
5149 mutex_lock(&adev->grbm_idx_mutex); 5147 mutex_lock(&adev->grbm_idx_mutex);
5150 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5148 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5151 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5149 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 29ec986dd6fc..dddb8d6a81f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -244,7 +244,7 @@ static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
244static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, 244static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
245 struct amdgpu_ib *ib) 245 struct amdgpu_ib *ib)
246{ 246{
247 u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; 247 u32 vmid = ib->vm_id & 0xf;
248 u32 next_rptr = ring->wptr + 5; 248 u32 next_rptr = ring->wptr + 5;
249 249
250 while ((next_rptr & 7) != 2) 250 while ((next_rptr & 7) != 2)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 6f064d7076e6..19e02f7a06f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -355,7 +355,7 @@ static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
355static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 355static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
356 struct amdgpu_ib *ib) 356 struct amdgpu_ib *ib)
357{ 357{
358 u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; 358 u32 vmid = ib->vm_id & 0xf;
359 u32 next_rptr = ring->wptr + 5; 359 u32 next_rptr = ring->wptr + 5;
360 360
361 while ((next_rptr & 7) != 2) 361 while ((next_rptr & 7) != 2)
diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h
index d98aa9d82fa1..ace49976f7be 100644
--- a/drivers/gpu/drm/amd/amdgpu/vid.h
+++ b/drivers/gpu/drm/amd/amdgpu/vid.h
@@ -71,8 +71,6 @@
71#define VMID(x) ((x) << 4) 71#define VMID(x) ((x) << 4)
72#define QUEUEID(x) ((x) << 8) 72#define QUEUEID(x) ((x) << 8)
73 73
74#define RB_BITMAP_WIDTH_PER_SH 2
75
76#define MC_SEQ_MISC0__MT__MASK 0xf0000000 74#define MC_SEQ_MISC0__MT__MASK 0xf0000000
77#define MC_SEQ_MISC0__MT__GDDR1 0x10000000 75#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
78#define MC_SEQ_MISC0__MT__DDR2 0x20000000 76#define MC_SEQ_MISC0__MT__DDR2 0x20000000
diff --git a/drivers/gpu/drm/amd/include/amd_acpi.h b/drivers/gpu/drm/amd/include/amd_acpi.h
index 496360eb3fba..50e893325141 100644
--- a/drivers/gpu/drm/amd/include/amd_acpi.h
+++ b/drivers/gpu/drm/amd/include/amd_acpi.h
@@ -340,6 +340,8 @@ struct atcs_pref_req_output {
340# define ATPX_FIXED_NOT_SUPPORTED (1 << 9) 340# define ATPX_FIXED_NOT_SUPPORTED (1 << 9)
341# define ATPX_DYNAMIC_DGPU_POWER_OFF_SUPPORTED (1 << 10) 341# define ATPX_DYNAMIC_DGPU_POWER_OFF_SUPPORTED (1 << 10)
342# define ATPX_DGPU_REQ_POWER_FOR_DISPLAYS (1 << 11) 342# define ATPX_DGPU_REQ_POWER_FOR_DISPLAYS (1 << 11)
343# define ATPX_DGPU_CAN_DRIVE_DISPLAYS (1 << 12)
344# define ATPX_MS_HYBRID_GFX_SUPPORTED (1 << 14)
343#define ATPX_FUNCTION_POWER_CONTROL 0x2 345#define ATPX_FUNCTION_POWER_CONTROL 0x2
344/* ARG0: ATPX_FUNCTION_POWER_CONTROL 346/* ARG0: ATPX_FUNCTION_POWER_CONTROL
345 * ARG1: 347 * ARG1:
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 2ee4190f8c89..0db64231effe 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -606,7 +606,7 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
606 606
607 if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || 607 if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
608 hwmgr->hwmgr_func->set_pp_table == NULL) 608 hwmgr->hwmgr_func->set_pp_table == NULL)
609 return -EINVAL; 609 return -EINVAL;
610 610
611 return hwmgr->hwmgr_func->set_pp_table(hwmgr, buf, size); 611 return hwmgr->hwmgr_func->set_pp_table(hwmgr, buf, size);
612} 612}
@@ -623,7 +623,7 @@ static int pp_dpm_force_clock_level(void *handle,
623 623
624 if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || 624 if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
625 hwmgr->hwmgr_func->force_clock_level == NULL) 625 hwmgr->hwmgr_func->force_clock_level == NULL)
626 return -EINVAL; 626 return -EINVAL;
627 627
628 return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, level); 628 return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, level);
629} 629}
diff --git a/drivers/gpu/drm/radeon/radeon_acpi.h b/drivers/gpu/drm/radeon/radeon_acpi.h
index be4af76f213d..cd872f7953c6 100644
--- a/drivers/gpu/drm/radeon/radeon_acpi.h
+++ b/drivers/gpu/drm/radeon/radeon_acpi.h
@@ -291,6 +291,8 @@ int radeon_atif_handler(struct radeon_device *rdev,
291# define ATPX_FIXED_NOT_SUPPORTED (1 << 9) 291# define ATPX_FIXED_NOT_SUPPORTED (1 << 9)
292# define ATPX_DYNAMIC_DGPU_POWER_OFF_SUPPORTED (1 << 10) 292# define ATPX_DYNAMIC_DGPU_POWER_OFF_SUPPORTED (1 << 10)
293# define ATPX_DGPU_REQ_POWER_FOR_DISPLAYS (1 << 11) 293# define ATPX_DGPU_REQ_POWER_FOR_DISPLAYS (1 << 11)
294# define ATPX_DGPU_CAN_DRIVE_DISPLAYS (1 << 12)
295# define ATPX_MS_HYBRID_GFX_SUPPORTED (1 << 14)
294#define ATPX_FUNCTION_POWER_CONTROL 0x2 296#define ATPX_FUNCTION_POWER_CONTROL 0x2
295/* ARG0: ATPX_FUNCTION_POWER_CONTROL 297/* ARG0: ATPX_FUNCTION_POWER_CONTROL
296 * ARG1: 298 * ARG1:
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-26 13:51:54 -0400