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-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/psp_v11_0.c28
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c22
-rw-r--r--drivers/gpu/drm/drm_lease.c3
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c12
-rw-r--r--drivers/gpu/drm/i915/i915_pmu.c22
-rw-r--r--drivers/gpu/drm/i915/i915_pmu.h2
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h18
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c238
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c4
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h10
-rw-r--r--drivers/gpu/drm/i915/intel_fbdev.c33
-rw-r--r--drivers/gpu/drm/i915/intel_opregion.c38
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h9
-rw-r--r--drivers/gpu/drm/imx/imx-ldb.c25
-rw-r--r--drivers/gpu/drm/imx/ipuv3-plane.c4
-rw-r--r--drivers/gpu/drm/scheduler/sched_entity.c7
-rw-r--r--drivers/gpu/drm/vkms/vkms_crc.c3
-rw-r--r--drivers/gpu/drm/vkms/vkms_crtc.c8
-rw-r--r--drivers/gpu/drm/vkms/vkms_drv.c7
-rw-r--r--drivers/gpu/drm/vkms/vkms_drv.h2
-rw-r--r--drivers/gpu/drm/vkms/vkms_gem.c8
-rw-r--r--drivers/gpu/drm/vkms/vkms_output.c8
-rw-r--r--drivers/gpu/drm/vkms/vkms_plane.c8
-rw-r--r--drivers/gpu/ipu-v3/ipu-common.c8
-rw-r--r--drivers/gpu/ipu-v3/ipu-pre.c6
26 files changed, 294 insertions, 248 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 8fab0d637ee5..3a9b48b227ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -90,8 +90,10 @@ static int psp_sw_fini(void *handle)
90 adev->psp.sos_fw = NULL; 90 adev->psp.sos_fw = NULL;
91 release_firmware(adev->psp.asd_fw); 91 release_firmware(adev->psp.asd_fw);
92 adev->psp.asd_fw = NULL; 92 adev->psp.asd_fw = NULL;
93 release_firmware(adev->psp.ta_fw); 93 if (adev->psp.ta_fw) {
94 adev->psp.ta_fw = NULL; 94 release_firmware(adev->psp.ta_fw);
95 adev->psp.ta_fw = NULL;
96 }
95 return 0; 97 return 0;
96} 98}
97 99
@@ -435,6 +437,9 @@ static int psp_xgmi_initialize(struct psp_context *psp)
435 struct ta_xgmi_shared_memory *xgmi_cmd; 437 struct ta_xgmi_shared_memory *xgmi_cmd;
436 int ret; 438 int ret;
437 439
440 if (!psp->adev->psp.ta_fw)
441 return -ENOENT;
442
438 if (!psp->xgmi_context.initialized) { 443 if (!psp->xgmi_context.initialized) {
439 ret = psp_xgmi_init_shared_buf(psp); 444 ret = psp_xgmi_init_shared_buf(psp);
440 if (ret) 445 if (ret)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 0c6e7f9b143f..189fcb004579 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -152,18 +152,22 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
152 152
153 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 153 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
154 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 154 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
155 if (err) 155 if (err) {
156 goto out2; 156 release_firmware(adev->psp.ta_fw);
157 157 adev->psp.ta_fw = NULL;
158 err = amdgpu_ucode_validate(adev->psp.ta_fw); 158 dev_info(adev->dev,
159 if (err) 159 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
160 goto out2; 160 } else {
161 161 err = amdgpu_ucode_validate(adev->psp.ta_fw);
162 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 162 if (err)
163 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version); 163 goto out2;
164 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); 164
165 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + 165 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
166 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 166 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
167 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
168 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
169 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
170 }
167 171
168 return 0; 172 return 0;
169 173
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 9a7ac58eb18e..ddd75a4d8ba5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -671,6 +671,25 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us
671 return bytes_from_user; 671 return bytes_from_user;
672} 672}
673 673
674/*
675 * Returns the min and max vrr vfreq through the connector's debugfs file.
676 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range
677 */
678static int vrr_range_show(struct seq_file *m, void *data)
679{
680 struct drm_connector *connector = m->private;
681 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
682
683 if (connector->status != connector_status_connected)
684 return -ENODEV;
685
686 seq_printf(m, "Min: %u\n", (unsigned int)aconnector->min_vfreq);
687 seq_printf(m, "Max: %u\n", (unsigned int)aconnector->max_vfreq);
688
689 return 0;
690}
691DEFINE_SHOW_ATTRIBUTE(vrr_range);
692
674static const struct file_operations dp_link_settings_debugfs_fops = { 693static const struct file_operations dp_link_settings_debugfs_fops = {
675 .owner = THIS_MODULE, 694 .owner = THIS_MODULE,
676 .read = dp_link_settings_read, 695 .read = dp_link_settings_read,
@@ -697,7 +716,8 @@ static const struct {
697} dp_debugfs_entries[] = { 716} dp_debugfs_entries[] = {
698 {"link_settings", &dp_link_settings_debugfs_fops}, 717 {"link_settings", &dp_link_settings_debugfs_fops},
699 {"phy_settings", &dp_phy_settings_debugfs_fop}, 718 {"phy_settings", &dp_phy_settings_debugfs_fop},
700 {"test_pattern", &dp_phy_test_pattern_fops} 719 {"test_pattern", &dp_phy_test_pattern_fops},
720 {"vrr_range", &vrr_range_fops}
701}; 721};
702 722
703int connector_debugfs_init(struct amdgpu_dm_connector *connector) 723int connector_debugfs_init(struct amdgpu_dm_connector *connector)
diff --git a/drivers/gpu/drm/drm_lease.c b/drivers/gpu/drm/drm_lease.c
index 99cba8ea5d82..5df1256618cc 100644
--- a/drivers/gpu/drm/drm_lease.c
+++ b/drivers/gpu/drm/drm_lease.c
@@ -528,7 +528,8 @@ int drm_mode_create_lease_ioctl(struct drm_device *dev,
528 528
529 object_count = cl->object_count; 529 object_count = cl->object_count;
530 530
531 object_ids = memdup_user(u64_to_user_ptr(cl->object_ids), object_count * sizeof(__u32)); 531 object_ids = memdup_user(u64_to_user_ptr(cl->object_ids),
532 array_size(object_count, sizeof(__u32)));
532 if (IS_ERR(object_ids)) 533 if (IS_ERR(object_ids))
533 return PTR_ERR(object_ids); 534 return PTR_ERR(object_ids);
534 535
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 216f52b744a6..c882ea94172c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1824,6 +1824,16 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1824 return 0; 1824 return 0;
1825} 1825}
1826 1826
1827static inline bool
1828__vma_matches(struct vm_area_struct *vma, struct file *filp,
1829 unsigned long addr, unsigned long size)
1830{
1831 if (vma->vm_file != filp)
1832 return false;
1833
1834 return vma->vm_start == addr && (vma->vm_end - vma->vm_start) == size;
1835}
1836
1827/** 1837/**
1828 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address 1838 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1829 * it is mapped to. 1839 * it is mapped to.
@@ -1882,7 +1892,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1882 return -EINTR; 1892 return -EINTR;
1883 } 1893 }
1884 vma = find_vma(mm, addr); 1894 vma = find_vma(mm, addr);
1885 if (vma) 1895 if (vma && __vma_matches(vma, obj->base.filp, addr, args->size))
1886 vma->vm_page_prot = 1896 vma->vm_page_prot =
1887 pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); 1897 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1888 else 1898 else
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index d6c8f8fdfda5..017fc602a10e 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -594,7 +594,8 @@ static void i915_pmu_enable(struct perf_event *event)
594 * Update the bitmask of enabled events and increment 594 * Update the bitmask of enabled events and increment
595 * the event reference counter. 595 * the event reference counter.
596 */ 596 */
597 GEM_BUG_ON(bit >= I915_PMU_MASK_BITS); 597 BUILD_BUG_ON(ARRAY_SIZE(i915->pmu.enable_count) != I915_PMU_MASK_BITS);
598 GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count));
598 GEM_BUG_ON(i915->pmu.enable_count[bit] == ~0); 599 GEM_BUG_ON(i915->pmu.enable_count[bit] == ~0);
599 i915->pmu.enable |= BIT_ULL(bit); 600 i915->pmu.enable |= BIT_ULL(bit);
600 i915->pmu.enable_count[bit]++; 601 i915->pmu.enable_count[bit]++;
@@ -615,11 +616,16 @@ static void i915_pmu_enable(struct perf_event *event)
615 engine = intel_engine_lookup_user(i915, 616 engine = intel_engine_lookup_user(i915,
616 engine_event_class(event), 617 engine_event_class(event),
617 engine_event_instance(event)); 618 engine_event_instance(event));
618 GEM_BUG_ON(!engine);
619 engine->pmu.enable |= BIT(sample);
620 619
621 GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS); 620 BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) !=
621 I915_ENGINE_SAMPLE_COUNT);
622 BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.sample) !=
623 I915_ENGINE_SAMPLE_COUNT);
624 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
625 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
622 GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0); 626 GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
627
628 engine->pmu.enable |= BIT(sample);
623 engine->pmu.enable_count[sample]++; 629 engine->pmu.enable_count[sample]++;
624 } 630 }
625 631
@@ -649,9 +655,11 @@ static void i915_pmu_disable(struct perf_event *event)
649 engine = intel_engine_lookup_user(i915, 655 engine = intel_engine_lookup_user(i915,
650 engine_event_class(event), 656 engine_event_class(event),
651 engine_event_instance(event)); 657 engine_event_instance(event));
652 GEM_BUG_ON(!engine); 658
653 GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS); 659 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
660 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
654 GEM_BUG_ON(engine->pmu.enable_count[sample] == 0); 661 GEM_BUG_ON(engine->pmu.enable_count[sample] == 0);
662
655 /* 663 /*
656 * Decrement the reference count and clear the enabled 664 * Decrement the reference count and clear the enabled
657 * bitmask when the last listener on an event goes away. 665 * bitmask when the last listener on an event goes away.
@@ -660,7 +668,7 @@ static void i915_pmu_disable(struct perf_event *event)
660 engine->pmu.enable &= ~BIT(sample); 668 engine->pmu.enable &= ~BIT(sample);
661 } 669 }
662 670
663 GEM_BUG_ON(bit >= I915_PMU_MASK_BITS); 671 GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count));
664 GEM_BUG_ON(i915->pmu.enable_count[bit] == 0); 672 GEM_BUG_ON(i915->pmu.enable_count[bit] == 0);
665 /* 673 /*
666 * Decrement the reference count and clear the enabled 674 * Decrement the reference count and clear the enabled
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index 7f164ca3db12..b3728c5f13e7 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -31,6 +31,8 @@ enum {
31 ((1 << I915_PMU_SAMPLE_BITS) + \ 31 ((1 << I915_PMU_SAMPLE_BITS) + \
32 (I915_PMU_LAST + 1 - __I915_PMU_OTHER(0))) 32 (I915_PMU_LAST + 1 - __I915_PMU_OTHER(0)))
33 33
34#define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1)
35
34struct i915_pmu_sample { 36struct i915_pmu_sample {
35 u64 cur; 37 u64 cur;
36}; 38};
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a7d60509ca7..067054cf4a86 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1790,7 +1790,7 @@ enum i915_power_well_id {
1790#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40 1790#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
1791#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40 1791#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
1792#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840 1792#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
1793#define _CNL_PORT_TX_DW_GRP(port, dw) (_PICK((port), \ 1793#define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \
1794 _CNL_PORT_TX_AE_GRP_OFFSET, \ 1794 _CNL_PORT_TX_AE_GRP_OFFSET, \
1795 _CNL_PORT_TX_B_GRP_OFFSET, \ 1795 _CNL_PORT_TX_B_GRP_OFFSET, \
1796 _CNL_PORT_TX_B_GRP_OFFSET, \ 1796 _CNL_PORT_TX_B_GRP_OFFSET, \
@@ -1798,7 +1798,7 @@ enum i915_power_well_id {
1798 _CNL_PORT_TX_AE_GRP_OFFSET, \ 1798 _CNL_PORT_TX_AE_GRP_OFFSET, \
1799 _CNL_PORT_TX_F_GRP_OFFSET) + \ 1799 _CNL_PORT_TX_F_GRP_OFFSET) + \
1800 4 * (dw)) 1800 4 * (dw))
1801#define _CNL_PORT_TX_DW_LN0(port, dw) (_PICK((port), \ 1801#define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \
1802 _CNL_PORT_TX_AE_LN0_OFFSET, \ 1802 _CNL_PORT_TX_AE_LN0_OFFSET, \
1803 _CNL_PORT_TX_B_LN0_OFFSET, \ 1803 _CNL_PORT_TX_B_LN0_OFFSET, \
1804 _CNL_PORT_TX_B_LN0_OFFSET, \ 1804 _CNL_PORT_TX_B_LN0_OFFSET, \
@@ -1834,9 +1834,9 @@ enum i915_power_well_id {
1834 1834
1835#define _CNL_PORT_TX_DW4_LN0_AE 0x162450 1835#define _CNL_PORT_TX_DW4_LN0_AE 0x162450
1836#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0 1836#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
1837#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 4)) 1837#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
1838#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4)) 1838#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
1839#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \ 1839#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
1840 ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \ 1840 ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
1841 _CNL_PORT_TX_DW4_LN0_AE))) 1841 _CNL_PORT_TX_DW4_LN0_AE)))
1842#define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port)) 1842#define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port))
@@ -1864,8 +1864,12 @@ enum i915_power_well_id {
1864#define RTERM_SELECT(x) ((x) << 3) 1864#define RTERM_SELECT(x) ((x) << 3)
1865#define RTERM_SELECT_MASK (0x7 << 3) 1865#define RTERM_SELECT_MASK (0x7 << 3)
1866 1866
1867#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7)) 1867#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
1868#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7)) 1868#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
1869#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
1870#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
1871#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
1872#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
1869#define N_SCALAR(x) ((x) << 24) 1873#define N_SCALAR(x) ((x) << 24)
1870#define N_SCALAR_MASK (0x7F << 24) 1874#define N_SCALAR_MASK (0x7F << 24)
1871 1875
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4079050f9d6c..7edce1b7b348 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -494,103 +494,58 @@ static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
494 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 494 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
495}; 495};
496 496
497struct icl_combo_phy_ddi_buf_trans { 497/* icl_combo_phy_ddi_translations */
498 u32 dw2_swing_select; 498static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
499 u32 dw2_swing_scalar; 499 /* NT mV Trans mV db */
500 u32 dw4_scaling; 500 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
501}; 501 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
502 502 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
503/* Voltage Swing Programming for VccIO 0.85V for DP */ 503 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
504static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = { 504 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
505 /* Voltage mV db */ 505 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
506 { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ 506 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
507 { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ 507 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
508 { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ 508 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
509 { 0x2, 0x98, 0x900F }, /* 400 9.5 */ 509 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
510 { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
511 { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
512 { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
513 { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
514 { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
515 { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
516};
517
518/* FIXME - After table is updated in Bspec */
519/* Voltage Swing Programming for VccIO 0.85V for eDP */
520static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
521 /* Voltage mV db */
522 { 0x0, 0x00, 0x00 }, /* 200 0.0 */
523 { 0x0, 0x00, 0x00 }, /* 200 1.5 */
524 { 0x0, 0x00, 0x00 }, /* 200 4.0 */
525 { 0x0, 0x00, 0x00 }, /* 200 6.0 */
526 { 0x0, 0x00, 0x00 }, /* 250 0.0 */
527 { 0x0, 0x00, 0x00 }, /* 250 1.5 */
528 { 0x0, 0x00, 0x00 }, /* 250 4.0 */
529 { 0x0, 0x00, 0x00 }, /* 300 0.0 */
530 { 0x0, 0x00, 0x00 }, /* 300 1.5 */
531 { 0x0, 0x00, 0x00 }, /* 350 0.0 */
532};
533
534/* Voltage Swing Programming for VccIO 0.95V for DP */
535static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
536 /* Voltage mV db */
537 { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
538 { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
539 { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
540 { 0x2, 0x98, 0x900F }, /* 400 9.5 */
541 { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
542 { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
543 { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
544 { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
545 { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
546 { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
547}; 510};
548 511
549/* FIXME - After table is updated in Bspec */ 512static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
550/* Voltage Swing Programming for VccIO 0.95V for eDP */ 513 /* NT mV Trans mV db */
551static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = { 514 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
552 /* Voltage mV db */ 515 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
553 { 0x0, 0x00, 0x00 }, /* 200 0.0 */ 516 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
554 { 0x0, 0x00, 0x00 }, /* 200 1.5 */ 517 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
555 { 0x0, 0x00, 0x00 }, /* 200 4.0 */ 518 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
556 { 0x0, 0x00, 0x00 }, /* 200 6.0 */ 519 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
557 { 0x0, 0x00, 0x00 }, /* 250 0.0 */ 520 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
558 { 0x0, 0x00, 0x00 }, /* 250 1.5 */ 521 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
559 { 0x0, 0x00, 0x00 }, /* 250 4.0 */ 522 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
560 { 0x0, 0x00, 0x00 }, /* 300 0.0 */ 523 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
561 { 0x0, 0x00, 0x00 }, /* 300 1.5 */
562 { 0x0, 0x00, 0x00 }, /* 350 0.0 */
563}; 524};
564 525
565/* Voltage Swing Programming for VccIO 1.05V for DP */ 526static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
566static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = { 527 /* NT mV Trans mV db */
567 /* Voltage mV db */ 528 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
568 { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ 529 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
569 { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ 530 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
570 { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ 531 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
571 { 0x2, 0x98, 0x900F }, /* 400 9.5 */ 532 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
572 { 0x4, 0x98, 0x0018 }, /* 600 0.0 */ 533 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
573 { 0x4, 0x98, 0x3015 }, /* 600 3.5 */ 534 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
574 { 0x4, 0x98, 0x6012 }, /* 600 6.0 */ 535 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
575 { 0x5, 0x71, 0x0018 }, /* 800 0.0 */ 536 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
576 { 0x5, 0x71, 0x3015 }, /* 800 3.5 */ 537 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
577 { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
578}; 538};
579 539
580/* FIXME - After table is updated in Bspec */ 540static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
581/* Voltage Swing Programming for VccIO 1.05V for eDP */ 541 /* NT mV Trans mV db */
582static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = { 542 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
583 /* Voltage mV db */ 543 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
584 { 0x0, 0x00, 0x00 }, /* 200 0.0 */ 544 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
585 { 0x0, 0x00, 0x00 }, /* 200 1.5 */ 545 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
586 { 0x0, 0x00, 0x00 }, /* 200 4.0 */ 546 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
587 { 0x0, 0x00, 0x00 }, /* 200 6.0 */ 547 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
588 { 0x0, 0x00, 0x00 }, /* 250 0.0 */ 548 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
589 { 0x0, 0x00, 0x00 }, /* 250 1.5 */
590 { 0x0, 0x00, 0x00 }, /* 250 4.0 */
591 { 0x0, 0x00, 0x00 }, /* 300 0.0 */
592 { 0x0, 0x00, 0x00 }, /* 300 1.5 */
593 { 0x0, 0x00, 0x00 }, /* 350 0.0 */
594}; 549};
595 550
596struct icl_mg_phy_ddi_buf_trans { 551struct icl_mg_phy_ddi_buf_trans {
@@ -871,43 +826,23 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
871 } 826 }
872} 827}
873 828
874static const struct icl_combo_phy_ddi_buf_trans * 829static const struct cnl_ddi_buf_trans *
875icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port, 830icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
876 int type, int *n_entries) 831 int type, int rate, int *n_entries)
877{ 832{
878 u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK; 833 if (type == INTEL_OUTPUT_HDMI) {
879 834 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
880 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { 835 return icl_combo_phy_ddi_translations_hdmi;
881 switch (voltage) { 836 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
882 case VOLTAGE_INFO_0_85V: 837 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
883 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V); 838 return icl_combo_phy_ddi_translations_edp_hbr3;
884 return icl_combo_phy_ddi_translations_edp_0_85V; 839 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
885 case VOLTAGE_INFO_0_95V: 840 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
886 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V); 841 return icl_combo_phy_ddi_translations_edp_hbr2;
887 return icl_combo_phy_ddi_translations_edp_0_95V;
888 case VOLTAGE_INFO_1_05V:
889 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
890 return icl_combo_phy_ddi_translations_edp_1_05V;
891 default:
892 MISSING_CASE(voltage);
893 return NULL;
894 }
895 } else {
896 switch (voltage) {
897 case VOLTAGE_INFO_0_85V:
898 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
899 return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
900 case VOLTAGE_INFO_0_95V:
901 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
902 return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
903 case VOLTAGE_INFO_1_05V:
904 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
905 return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
906 default:
907 MISSING_CASE(voltage);
908 return NULL;
909 }
910 } 842 }
843
844 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
845 return icl_combo_phy_ddi_translations_dp_hbr2;
911} 846}
912 847
913static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) 848static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
@@ -918,8 +853,8 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
918 853
919 if (IS_ICELAKE(dev_priv)) { 854 if (IS_ICELAKE(dev_priv)) {
920 if (intel_port_is_combophy(dev_priv, port)) 855 if (intel_port_is_combophy(dev_priv, port))
921 icl_get_combo_buf_trans(dev_priv, port, 856 icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
922 INTEL_OUTPUT_HDMI, &n_entries); 857 0, &n_entries);
923 else 858 else
924 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 859 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
925 default_entry = n_entries - 1; 860 default_entry = n_entries - 1;
@@ -2275,13 +2210,14 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2275u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) 2210u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2276{ 2211{
2277 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2212 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2213 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2278 enum port port = encoder->port; 2214 enum port port = encoder->port;
2279 int n_entries; 2215 int n_entries;
2280 2216
2281 if (IS_ICELAKE(dev_priv)) { 2217 if (IS_ICELAKE(dev_priv)) {
2282 if (intel_port_is_combophy(dev_priv, port)) 2218 if (intel_port_is_combophy(dev_priv, port))
2283 icl_get_combo_buf_trans(dev_priv, port, encoder->type, 2219 icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2284 &n_entries); 2220 intel_dp->link_rate, &n_entries);
2285 else 2221 else
2286 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 2222 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2287 } else if (IS_CANNONLAKE(dev_priv)) { 2223 } else if (IS_CANNONLAKE(dev_priv)) {
@@ -2462,14 +2398,15 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2462} 2398}
2463 2399
2464static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, 2400static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2465 u32 level, enum port port, int type) 2401 u32 level, enum port port, int type,
2402 int rate)
2466{ 2403{
2467 const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL; 2404 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2468 u32 n_entries, val; 2405 u32 n_entries, val;
2469 int ln; 2406 int ln;
2470 2407
2471 ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type, 2408 ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2472 &n_entries); 2409 rate, &n_entries);
2473 if (!ddi_translations) 2410 if (!ddi_translations)
2474 return; 2411 return;
2475 2412
@@ -2478,34 +2415,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2478 level = n_entries - 1; 2415 level = n_entries - 1;
2479 } 2416 }
2480 2417
2481 /* Set PORT_TX_DW5 Rterm Sel to 110b. */ 2418 /* Set PORT_TX_DW5 */
2482 val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); 2419 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2483 val &= ~RTERM_SELECT_MASK; 2420 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2421 TAP2_DISABLE | TAP3_DISABLE);
2422 val |= SCALING_MODE_SEL(0x2);
2484 val |= RTERM_SELECT(0x6); 2423 val |= RTERM_SELECT(0x6);
2485 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); 2424 val |= TAP3_DISABLE;
2486
2487 /* Program PORT_TX_DW5 */
2488 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2489 /* Set DisableTap2 and DisableTap3 if MIPI DSI
2490 * Clear DisableTap2 and DisableTap3 for all other Ports
2491 */
2492 if (type == INTEL_OUTPUT_DSI) {
2493 val |= TAP2_DISABLE;
2494 val |= TAP3_DISABLE;
2495 } else {
2496 val &= ~TAP2_DISABLE;
2497 val &= ~TAP3_DISABLE;
2498 }
2499 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); 2425 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2500 2426
2501 /* Program PORT_TX_DW2 */ 2427 /* Program PORT_TX_DW2 */
2502 val = I915_READ(ICL_PORT_TX_DW2_LN0(port)); 2428 val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2503 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2429 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2504 RCOMP_SCALAR_MASK); 2430 RCOMP_SCALAR_MASK);
2505 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select); 2431 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2506 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select); 2432 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2507 /* Program Rcomp scalar for every table entry */ 2433 /* Program Rcomp scalar for every table entry */
2508 val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar); 2434 val |= RCOMP_SCALAR(0x98);
2509 I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val); 2435 I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2510 2436
2511 /* Program PORT_TX_DW4 */ 2437 /* Program PORT_TX_DW4 */
@@ -2514,9 +2440,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2514 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln)); 2440 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2515 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2441 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2516 CURSOR_COEFF_MASK); 2442 CURSOR_COEFF_MASK);
2517 val |= ddi_translations[level].dw4_scaling; 2443 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2444 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2445 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2518 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val); 2446 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2519 } 2447 }
2448
2449 /* Program PORT_TX_DW7 */
2450 val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
2451 val &= ~N_SCALAR_MASK;
2452 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2453 I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
2520} 2454}
2521 2455
2522static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2456static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
@@ -2581,7 +2515,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2581 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); 2515 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2582 2516
2583 /* 5. Program swing and de-emphasis */ 2517 /* 5. Program swing and de-emphasis */
2584 icl_ddi_combo_vswing_program(dev_priv, level, port, type); 2518 icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
2585 2519
2586 /* 6. Set training enable to trigger update */ 2520 /* 6. Set training enable to trigger update */
2587 val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); 2521 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fdd2cbc56fa3..22a74608c6e4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -304,9 +304,11 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
304static int icl_max_source_rate(struct intel_dp *intel_dp) 304static int icl_max_source_rate(struct intel_dp *intel_dp)
305{ 305{
306 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 306 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
307 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
307 enum port port = dig_port->base.port; 308 enum port port = dig_port->base.port;
308 309
309 if (port == PORT_B) 310 if (intel_port_is_combophy(dev_priv, port) &&
311 !intel_dp_is_edp(intel_dp))
310 return 540000; 312 return 540000;
311 313
312 return 810000; 314 return 810000;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f94a04b4ad87..e9ddeaf05a14 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -209,6 +209,16 @@ struct intel_fbdev {
209 unsigned long vma_flags; 209 unsigned long vma_flags;
210 async_cookie_t cookie; 210 async_cookie_t cookie;
211 int preferred_bpp; 211 int preferred_bpp;
212
213 /* Whether or not fbdev hpd processing is temporarily suspended */
214 bool hpd_suspended : 1;
215 /* Set when a hotplug was received while HPD processing was
216 * suspended
217 */
218 bool hpd_waiting : 1;
219
220 /* Protects hpd_suspended */
221 struct mutex hpd_lock;
212}; 222};
213 223
214struct intel_encoder { 224struct intel_encoder {
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index fb5bb5b32a60..7f365ac0b549 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -679,6 +679,7 @@ int intel_fbdev_init(struct drm_device *dev)
679 if (ifbdev == NULL) 679 if (ifbdev == NULL)
680 return -ENOMEM; 680 return -ENOMEM;
681 681
682 mutex_init(&ifbdev->hpd_lock);
682 drm_fb_helper_prepare(dev, &ifbdev->helper, &intel_fb_helper_funcs); 683 drm_fb_helper_prepare(dev, &ifbdev->helper, &intel_fb_helper_funcs);
683 684
684 if (!intel_fbdev_init_bios(dev, ifbdev)) 685 if (!intel_fbdev_init_bios(dev, ifbdev))
@@ -752,6 +753,26 @@ void intel_fbdev_fini(struct drm_i915_private *dev_priv)
752 intel_fbdev_destroy(ifbdev); 753 intel_fbdev_destroy(ifbdev);
753} 754}
754 755
756/* Suspends/resumes fbdev processing of incoming HPD events. When resuming HPD
757 * processing, fbdev will perform a full connector reprobe if a hotplug event
758 * was received while HPD was suspended.
759 */
760static void intel_fbdev_hpd_set_suspend(struct intel_fbdev *ifbdev, int state)
761{
762 bool send_hpd = false;
763
764 mutex_lock(&ifbdev->hpd_lock);
765 ifbdev->hpd_suspended = state == FBINFO_STATE_SUSPENDED;
766 send_hpd = !ifbdev->hpd_suspended && ifbdev->hpd_waiting;
767 ifbdev->hpd_waiting = false;
768 mutex_unlock(&ifbdev->hpd_lock);
769
770 if (send_hpd) {
771 DRM_DEBUG_KMS("Handling delayed fbcon HPD event\n");
772 drm_fb_helper_hotplug_event(&ifbdev->helper);
773 }
774}
775
755void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) 776void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
756{ 777{
757 struct drm_i915_private *dev_priv = to_i915(dev); 778 struct drm_i915_private *dev_priv = to_i915(dev);
@@ -773,6 +794,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous
773 */ 794 */
774 if (state != FBINFO_STATE_RUNNING) 795 if (state != FBINFO_STATE_RUNNING)
775 flush_work(&dev_priv->fbdev_suspend_work); 796 flush_work(&dev_priv->fbdev_suspend_work);
797
776 console_lock(); 798 console_lock();
777 } else { 799 } else {
778 /* 800 /*
@@ -800,17 +822,26 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous
800 822
801 drm_fb_helper_set_suspend(&ifbdev->helper, state); 823 drm_fb_helper_set_suspend(&ifbdev->helper, state);
802 console_unlock(); 824 console_unlock();
825
826 intel_fbdev_hpd_set_suspend(ifbdev, state);
803} 827}
804 828
805void intel_fbdev_output_poll_changed(struct drm_device *dev) 829void intel_fbdev_output_poll_changed(struct drm_device *dev)
806{ 830{
807 struct intel_fbdev *ifbdev = to_i915(dev)->fbdev; 831 struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
832 bool send_hpd;
808 833
809 if (!ifbdev) 834 if (!ifbdev)
810 return; 835 return;
811 836
812 intel_fbdev_sync(ifbdev); 837 intel_fbdev_sync(ifbdev);
813 if (ifbdev->vma || ifbdev->helper.deferred_setup) 838
839 mutex_lock(&ifbdev->hpd_lock);
840 send_hpd = !ifbdev->hpd_suspended;
841 ifbdev->hpd_waiting = true;
842 mutex_unlock(&ifbdev->hpd_lock);
843
844 if (send_hpd && (ifbdev->vma || ifbdev->helper.deferred_setup))
814 drm_fb_helper_hotplug_event(&ifbdev->helper); 845 drm_fb_helper_hotplug_event(&ifbdev->helper);
815} 846}
816 847
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index b8f106d9ecf8..3ac20153705a 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -55,7 +55,12 @@
55struct opregion_header { 55struct opregion_header {
56 u8 signature[16]; 56 u8 signature[16];
57 u32 size; 57 u32 size;
58 u32 opregion_ver; 58 struct {
59 u8 rsvd;
60 u8 revision;
61 u8 minor;
62 u8 major;
63 } __packed over;
59 u8 bios_ver[32]; 64 u8 bios_ver[32];
60 u8 vbios_ver[16]; 65 u8 vbios_ver[16];
61 u8 driver_ver[16]; 66 u8 driver_ver[16];
@@ -119,7 +124,8 @@ struct opregion_asle {
119 u64 fdss; 124 u64 fdss;
120 u32 fdsp; 125 u32 fdsp;
121 u32 stat; 126 u32 stat;
122 u64 rvda; /* Physical address of raw vbt data */ 127 u64 rvda; /* Physical (2.0) or relative from opregion (2.1+)
128 * address of raw VBT data. */
123 u32 rvds; /* Size of raw vbt data */ 129 u32 rvds; /* Size of raw vbt data */
124 u8 rsvd[58]; 130 u8 rsvd[58];
125} __packed; 131} __packed;
@@ -925,6 +931,11 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
925 opregion->header = base; 931 opregion->header = base;
926 opregion->lid_state = base + ACPI_CLID; 932 opregion->lid_state = base + ACPI_CLID;
927 933
934 DRM_DEBUG_DRIVER("ACPI OpRegion version %u.%u.%u\n",
935 opregion->header->over.major,
936 opregion->header->over.minor,
937 opregion->header->over.revision);
938
928 mboxes = opregion->header->mboxes; 939 mboxes = opregion->header->mboxes;
929 if (mboxes & MBOX_ACPI) { 940 if (mboxes & MBOX_ACPI) {
930 DRM_DEBUG_DRIVER("Public ACPI methods supported\n"); 941 DRM_DEBUG_DRIVER("Public ACPI methods supported\n");
@@ -953,11 +964,26 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
953 if (dmi_check_system(intel_no_opregion_vbt)) 964 if (dmi_check_system(intel_no_opregion_vbt))
954 goto out; 965 goto out;
955 966
956 if (opregion->header->opregion_ver >= 2 && opregion->asle && 967 if (opregion->header->over.major >= 2 && opregion->asle &&
957 opregion->asle->rvda && opregion->asle->rvds) { 968 opregion->asle->rvda && opregion->asle->rvds) {
958 opregion->rvda = memremap(opregion->asle->rvda, 969 resource_size_t rvda = opregion->asle->rvda;
959 opregion->asle->rvds, 970
971 /*
972 * opregion 2.0: rvda is the physical VBT address.
973 *
974 * opregion 2.1+: rvda is unsigned, relative offset from
975 * opregion base, and should never point within opregion.
976 */
977 if (opregion->header->over.major > 2 ||
978 opregion->header->over.minor >= 1) {
979 WARN_ON(rvda < OPREGION_SIZE);
980
981 rvda += asls;
982 }
983
984 opregion->rvda = memremap(rvda, opregion->asle->rvds,
960 MEMREMAP_WB); 985 MEMREMAP_WB);
986
961 vbt = opregion->rvda; 987 vbt = opregion->rvda;
962 vbt_size = opregion->asle->rvds; 988 vbt_size = opregion->asle->rvds;
963 if (intel_bios_is_valid_vbt(vbt, vbt_size)) { 989 if (intel_bios_is_valid_vbt(vbt, vbt_size)) {
@@ -967,6 +993,8 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
967 goto out; 993 goto out;
968 } else { 994 } else {
969 DRM_DEBUG_KMS("Invalid VBT in ACPI OpRegion (RVDA)\n"); 995 DRM_DEBUG_KMS("Invalid VBT in ACPI OpRegion (RVDA)\n");
996 memunmap(opregion->rvda);
997 opregion->rvda = NULL;
970 } 998 }
971 } 999 }
972 1000
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 72edaa7ff411..a1a7cc29fdd1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -415,16 +415,17 @@ struct intel_engine_cs {
415 /** 415 /**
416 * @enable_count: Reference count for the enabled samplers. 416 * @enable_count: Reference count for the enabled samplers.
417 * 417 *
418 * Index number corresponds to the bit number from @enable. 418 * Index number corresponds to @enum drm_i915_pmu_engine_sample.
419 */ 419 */
420 unsigned int enable_count[I915_PMU_SAMPLE_BITS]; 420 unsigned int enable_count[I915_ENGINE_SAMPLE_COUNT];
421 /** 421 /**
422 * @sample: Counter values for sampling events. 422 * @sample: Counter values for sampling events.
423 * 423 *
424 * Our internal timer stores the current counters in this field. 424 * Our internal timer stores the current counters in this field.
425 *
426 * Index number corresponds to @enum drm_i915_pmu_engine_sample.
425 */ 427 */
426#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_SEMA + 1) 428 struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_COUNT];
427 struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX];
428 } pmu; 429 } pmu;
429 430
430 /* 431 /*
diff --git a/drivers/gpu/drm/imx/imx-ldb.c b/drivers/gpu/drm/imx/imx-ldb.c
index 2c5bbe317353..e31e263cf86b 100644
--- a/drivers/gpu/drm/imx/imx-ldb.c
+++ b/drivers/gpu/drm/imx/imx-ldb.c
@@ -643,8 +643,10 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
643 int bus_format; 643 int bus_format;
644 644
645 ret = of_property_read_u32(child, "reg", &i); 645 ret = of_property_read_u32(child, "reg", &i);
646 if (ret || i < 0 || i > 1) 646 if (ret || i < 0 || i > 1) {
647 return -EINVAL; 647 ret = -EINVAL;
648 goto free_child;
649 }
648 650
649 if (!of_device_is_available(child)) 651 if (!of_device_is_available(child))
650 continue; 652 continue;
@@ -657,7 +659,6 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
657 channel = &imx_ldb->channel[i]; 659 channel = &imx_ldb->channel[i];
658 channel->ldb = imx_ldb; 660 channel->ldb = imx_ldb;
659 channel->chno = i; 661 channel->chno = i;
660 channel->child = child;
661 662
662 /* 663 /*
663 * The output port is port@4 with an external 4-port mux or 664 * The output port is port@4 with an external 4-port mux or
@@ -667,13 +668,13 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
667 imx_ldb->lvds_mux ? 4 : 2, 0, 668 imx_ldb->lvds_mux ? 4 : 2, 0,
668 &channel->panel, &channel->bridge); 669 &channel->panel, &channel->bridge);
669 if (ret && ret != -ENODEV) 670 if (ret && ret != -ENODEV)
670 return ret; 671 goto free_child;
671 672
672 /* panel ddc only if there is no bridge */ 673 /* panel ddc only if there is no bridge */
673 if (!channel->bridge) { 674 if (!channel->bridge) {
674 ret = imx_ldb_panel_ddc(dev, channel, child); 675 ret = imx_ldb_panel_ddc(dev, channel, child);
675 if (ret) 676 if (ret)
676 return ret; 677 goto free_child;
677 } 678 }
678 679
679 bus_format = of_get_bus_format(dev, child); 680 bus_format = of_get_bus_format(dev, child);
@@ -689,18 +690,26 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
689 if (bus_format < 0) { 690 if (bus_format < 0) {
690 dev_err(dev, "could not determine data mapping: %d\n", 691 dev_err(dev, "could not determine data mapping: %d\n",
691 bus_format); 692 bus_format);
692 return bus_format; 693 ret = bus_format;
694 goto free_child;
693 } 695 }
694 channel->bus_format = bus_format; 696 channel->bus_format = bus_format;
697 channel->child = child;
695 698
696 ret = imx_ldb_register(drm, channel); 699 ret = imx_ldb_register(drm, channel);
697 if (ret) 700 if (ret) {
698 return ret; 701 channel->child = NULL;
702 goto free_child;
703 }
699 } 704 }
700 705
701 dev_set_drvdata(dev, imx_ldb); 706 dev_set_drvdata(dev, imx_ldb);
702 707
703 return 0; 708 return 0;
709
710free_child:
711 of_node_put(child);
712 return ret;
704} 713}
705 714
706static void imx_ldb_unbind(struct device *dev, struct device *master, 715static void imx_ldb_unbind(struct device *dev, struct device *master,
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c
index c390924de93d..21e964f6ab5c 100644
--- a/drivers/gpu/drm/imx/ipuv3-plane.c
+++ b/drivers/gpu/drm/imx/ipuv3-plane.c
@@ -370,9 +370,9 @@ static int ipu_plane_atomic_check(struct drm_plane *plane,
370 if (ret) 370 if (ret)
371 return ret; 371 return ret;
372 372
373 /* CRTC should be enabled */ 373 /* nothing to check when disabling or disabled */
374 if (!crtc_state->enable) 374 if (!crtc_state->enable)
375 return -EINVAL; 375 return 0;
376 376
377 switch (plane->type) { 377 switch (plane->type) {
378 case DRM_PLANE_TYPE_PRIMARY: 378 case DRM_PLANE_TYPE_PRIMARY:
diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c
index 4463d3826ecb..e2942c9a11a7 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -440,13 +440,10 @@ struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity)
440 440
441 while ((entity->dependency = 441 while ((entity->dependency =
442 sched->ops->dependency(sched_job, entity))) { 442 sched->ops->dependency(sched_job, entity))) {
443 trace_drm_sched_job_wait_dep(sched_job, entity->dependency);
443 444
444 if (drm_sched_entity_add_dependency_cb(entity)) { 445 if (drm_sched_entity_add_dependency_cb(entity))
445
446 trace_drm_sched_job_wait_dep(sched_job,
447 entity->dependency);
448 return NULL; 446 return NULL;
449 }
450 } 447 }
451 448
452 /* skip jobs from entity that marked guilty */ 449 /* skip jobs from entity that marked guilty */
diff --git a/drivers/gpu/drm/vkms/vkms_crc.c b/drivers/gpu/drm/vkms/vkms_crc.c
index 9d9e8146db90..d7b409a3c0f8 100644
--- a/drivers/gpu/drm/vkms/vkms_crc.c
+++ b/drivers/gpu/drm/vkms/vkms_crc.c
@@ -1,4 +1,5 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0+
2
2#include "vkms_drv.h" 3#include "vkms_drv.h"
3#include <linux/crc32.h> 4#include <linux/crc32.h>
4#include <drm/drm_atomic.h> 5#include <drm/drm_atomic.h>
diff --git a/drivers/gpu/drm/vkms/vkms_crtc.c b/drivers/gpu/drm/vkms/vkms_crtc.c
index 177bbcb38306..eb56ee893761 100644
--- a/drivers/gpu/drm/vkms/vkms_crtc.c
+++ b/drivers/gpu/drm/vkms/vkms_crtc.c
@@ -1,10 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 */
8 2
9#include "vkms_drv.h" 3#include "vkms_drv.h"
10#include <drm/drm_atomic_helper.h> 4#include <drm/drm_atomic_helper.h>
diff --git a/drivers/gpu/drm/vkms/vkms_drv.c b/drivers/gpu/drm/vkms/vkms_drv.c
index 83087877565c..7dcbecb5fac2 100644
--- a/drivers/gpu/drm/vkms/vkms_drv.c
+++ b/drivers/gpu/drm/vkms/vkms_drv.c
@@ -1,9 +1,4 @@
1/* 1// SPDX-License-Identifier: GPL-2.0+
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 */
7 2
8/** 3/**
9 * DOC: vkms (Virtual Kernel Modesetting) 4 * DOC: vkms (Virtual Kernel Modesetting)
diff --git a/drivers/gpu/drm/vkms/vkms_drv.h b/drivers/gpu/drm/vkms/vkms_drv.h
index e4469cd3d254..81f1cfbeb936 100644
--- a/drivers/gpu/drm/vkms/vkms_drv.h
+++ b/drivers/gpu/drm/vkms/vkms_drv.h
@@ -1,3 +1,5 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2
1#ifndef _VKMS_DRV_H_ 3#ifndef _VKMS_DRV_H_
2#define _VKMS_DRV_H_ 4#define _VKMS_DRV_H_
3 5
diff --git a/drivers/gpu/drm/vkms/vkms_gem.c b/drivers/gpu/drm/vkms/vkms_gem.c
index 80311daed47a..138b0bb325cf 100644
--- a/drivers/gpu/drm/vkms/vkms_gem.c
+++ b/drivers/gpu/drm/vkms/vkms_gem.c
@@ -1,10 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 */
8 2
9#include <linux/shmem_fs.h> 3#include <linux/shmem_fs.h>
10 4
diff --git a/drivers/gpu/drm/vkms/vkms_output.c b/drivers/gpu/drm/vkms/vkms_output.c
index 271a0eb9042c..4173e4f48334 100644
--- a/drivers/gpu/drm/vkms/vkms_output.c
+++ b/drivers/gpu/drm/vkms/vkms_output.c
@@ -1,10 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 */
8 2
9#include "vkms_drv.h" 3#include "vkms_drv.h"
10#include <drm/drm_crtc_helper.h> 4#include <drm/drm_crtc_helper.h>
diff --git a/drivers/gpu/drm/vkms/vkms_plane.c b/drivers/gpu/drm/vkms/vkms_plane.c
index 418817600ad1..0e67d2d42f0c 100644
--- a/drivers/gpu/drm/vkms/vkms_plane.c
+++ b/drivers/gpu/drm/vkms/vkms_plane.c
@@ -1,10 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 */
8 2
9#include "vkms_drv.h" 3#include "vkms_drv.h"
10#include <drm/drm_plane_helper.h> 4#include <drm/drm_plane_helper.h>
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index 474b00e19697..0a7d4395d427 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -898,8 +898,8 @@ static struct ipu_devtype ipu_type_imx51 = {
898 .cpmem_ofs = 0x1f000000, 898 .cpmem_ofs = 0x1f000000,
899 .srm_ofs = 0x1f040000, 899 .srm_ofs = 0x1f040000,
900 .tpm_ofs = 0x1f060000, 900 .tpm_ofs = 0x1f060000,
901 .csi0_ofs = 0x1f030000, 901 .csi0_ofs = 0x1e030000,
902 .csi1_ofs = 0x1f038000, 902 .csi1_ofs = 0x1e038000,
903 .ic_ofs = 0x1e020000, 903 .ic_ofs = 0x1e020000,
904 .disp0_ofs = 0x1e040000, 904 .disp0_ofs = 0x1e040000,
905 .disp1_ofs = 0x1e048000, 905 .disp1_ofs = 0x1e048000,
@@ -914,8 +914,8 @@ static struct ipu_devtype ipu_type_imx53 = {
914 .cpmem_ofs = 0x07000000, 914 .cpmem_ofs = 0x07000000,
915 .srm_ofs = 0x07040000, 915 .srm_ofs = 0x07040000,
916 .tpm_ofs = 0x07060000, 916 .tpm_ofs = 0x07060000,
917 .csi0_ofs = 0x07030000, 917 .csi0_ofs = 0x06030000,
918 .csi1_ofs = 0x07038000, 918 .csi1_ofs = 0x06038000,
919 .ic_ofs = 0x06020000, 919 .ic_ofs = 0x06020000,
920 .disp0_ofs = 0x06040000, 920 .disp0_ofs = 0x06040000,
921 .disp1_ofs = 0x06048000, 921 .disp1_ofs = 0x06048000,
diff --git a/drivers/gpu/ipu-v3/ipu-pre.c b/drivers/gpu/ipu-v3/ipu-pre.c
index 2f8db9d62551..4a28f3fbb0a2 100644
--- a/drivers/gpu/ipu-v3/ipu-pre.c
+++ b/drivers/gpu/ipu-v3/ipu-pre.c
@@ -106,6 +106,7 @@ struct ipu_pre {
106 void *buffer_virt; 106 void *buffer_virt;
107 bool in_use; 107 bool in_use;
108 unsigned int safe_window_end; 108 unsigned int safe_window_end;
109 unsigned int last_bufaddr;
109}; 110};
110 111
111static DEFINE_MUTEX(ipu_pre_list_mutex); 112static DEFINE_MUTEX(ipu_pre_list_mutex);
@@ -185,6 +186,7 @@ void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
185 186
186 writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF); 187 writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF);
187 writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF); 188 writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
189 pre->last_bufaddr = bufaddr;
188 190
189 val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) | 191 val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) |
190 IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) | 192 IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) |
@@ -242,7 +244,11 @@ void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr)
242 unsigned short current_yblock; 244 unsigned short current_yblock;
243 u32 val; 245 u32 val;
244 246
247 if (bufaddr == pre->last_bufaddr)
248 return;
249
245 writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF); 250 writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
251 pre->last_bufaddr = bufaddr;
246 252
247 do { 253 do {
248 if (time_after(jiffies, timeout)) { 254 if (time_after(jiffies, timeout)) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-26 07:52:18 -0500