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-rw-r--r--drivers/pci/probe.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index e164b5c9f0f0..204960e70333 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1169,6 +1169,7 @@ void set_pcie_port_type(struct pci_dev *pdev)
1169 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1169 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1170 if (!pos) 1170 if (!pos)
1171 return; 1171 return;
1172
1172 pdev->pcie_cap = pos; 1173 pdev->pcie_cap = pos;
1173 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16); 1174 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
1174 pdev->pcie_flags_reg = reg16; 1175 pdev->pcie_flags_reg = reg16;
@@ -1176,13 +1177,14 @@ void set_pcie_port_type(struct pci_dev *pdev)
1176 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 1177 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1177 1178
1178 /* 1179 /*
1179 * A Root Port is always the upstream end of a Link. No PCIe 1180 * A Root Port or a PCI-to-PCIe bridge is always the upstream end
1180 * component has two Links. Two Links are connected by a Switch 1181 * of a Link. No PCIe component has two Links. Two Links are
1181 * that has a Port on each Link and internal logic to connect the 1182 * connected by a Switch that has a Port on each Link and internal
1182 * two Ports. 1183 * logic to connect the two Ports.
1183 */ 1184 */
1184 type = pci_pcie_type(pdev); 1185 type = pci_pcie_type(pdev);
1185 if (type == PCI_EXP_TYPE_ROOT_PORT) 1186 if (type == PCI_EXP_TYPE_ROOT_PORT ||
1187 type == PCI_EXP_TYPE_PCIE_BRIDGE)
1186 pdev->has_secondary_link = 1; 1188 pdev->has_secondary_link = 1;
1187 else if (type == PCI_EXP_TYPE_UPSTREAM || 1189 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1188 type == PCI_EXP_TYPE_DOWNSTREAM) { 1190 type == PCI_EXP_TYPE_DOWNSTREAM) {