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-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi88
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts1
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp.dtsi43
3 files changed, 90 insertions, 42 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi
new file mode 100644
index 000000000000..cdc6a437dcc7
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi
@@ -0,0 +1,88 @@
1/*
2 * clock specification for Xilinx ZynqMP ep108 development board
3 *
4 * (C) Copyright 2015, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14&amba {
15 misc_clk: misc_clk {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <25000000>;
19 };
20
21 i2c_clk: i2c_clk {
22 compatible = "fixed-clock";
23 #clock-cells = <0x0>;
24 clock-frequency = <111111111>;
25 };
26
27 sata_clk: sata_clk {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <75000000>;
31 };
32};
33
34&can0 {
35 clocks = <&misc_clk &misc_clk>;
36};
37
38&gem0 {
39 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
40};
41
42&gpio {
43 clocks = <&misc_clk>;
44};
45
46&i2c0 {
47 clocks = <&i2c_clk>;
48};
49
50&i2c1 {
51 clocks = <&i2c_clk>;
52};
53
54&sata {
55 clocks = <&sata_clk>;
56};
57
58&sdhci0 {
59 clocks = <&misc_clk>, <&misc_clk>;
60};
61
62&sdhci1 {
63 clocks = <&misc_clk>, <&misc_clk>;
64};
65
66&spi0 {
67 clocks = <&misc_clk &misc_clk>;
68};
69
70&spi1 {
71 clocks = <&misc_clk &misc_clk>;
72};
73
74&uart0 {
75 clocks = <&misc_clk &misc_clk>;
76};
77
78&usb0 {
79 clocks = <&misc_clk>, <&misc_clk>;
80};
81
82&usb1 {
83 clocks = <&misc_clk>, <&misc_clk>;
84};
85
86&watchdog0 {
87 clocks= <&misc_clk>;
88};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
index ce5d848251fa..acb0527fdc4a 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -14,6 +14,7 @@
14/dts-v1/; 14/dts-v1/;
15 15
16/include/ "zynqmp.dtsi" 16/include/ "zynqmp.dtsi"
17/include/ "zynqmp-ep108-clk.dtsi"
17 18
18/ { 19/ {
19 model = "ZynqMP EP108"; 20 model = "ZynqMP EP108";
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 7bc65e391530..e595f22e7e4b 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -90,7 +90,7 @@
90 }; 90 };
91 }; 91 };
92 92
93 amba { 93 amba: amba {
94 compatible = "simple-bus"; 94 compatible = "simple-bus";
95 #address-cells = <2>; 95 #address-cells = <2>;
96 #size-cells = <1>; 96 #size-cells = <1>;
@@ -99,7 +99,6 @@
99 can0: can@ff060000 { 99 can0: can@ff060000 {
100 compatible = "xlnx,zynq-can-1.0"; 100 compatible = "xlnx,zynq-can-1.0";
101 status = "disabled"; 101 status = "disabled";
102 clocks = <&misc_clk &misc_clk>;
103 clock-names = "can_clk", "pclk"; 102 clock-names = "can_clk", "pclk";
104 reg = <0x0 0xff060000 0x1000>; 103 reg = <0x0 0xff060000 0x1000>;
105 interrupts = <0 23 4>; 104 interrupts = <0 23 4>;
@@ -111,7 +110,6 @@
111 can1: can@ff070000 { 110 can1: can@ff070000 {
112 compatible = "xlnx,zynq-can-1.0"; 111 compatible = "xlnx,zynq-can-1.0";
113 status = "disabled"; 112 status = "disabled";
114 clocks = <&misc_clk &misc_clk>;
115 clock-names = "can_clk", "pclk"; 113 clock-names = "can_clk", "pclk";
116 reg = <0x0 0xff070000 0x1000>; 114 reg = <0x0 0xff070000 0x1000>;
117 interrupts = <0 24 4>; 115 interrupts = <0 24 4>;
@@ -120,12 +118,6 @@
120 rx-fifo-depth = <0x40>; 118 rx-fifo-depth = <0x40>;
121 }; 119 };
122 120
123 misc_clk: misc_clk {
124 compatible = "fixed-clock";
125 #clock-cells = <0>;
126 clock-frequency = <25000000>;
127 };
128
129 gem0: ethernet@ff0b0000 { 121 gem0: ethernet@ff0b0000 {
130 compatible = "cdns,gem"; 122 compatible = "cdns,gem";
131 status = "disabled"; 123 status = "disabled";
@@ -133,7 +125,6 @@
133 interrupts = <0 57 4>, <0 57 4>; 125 interrupts = <0 57 4>, <0 57 4>;
134 reg = <0x0 0xff0b0000 0x1000>; 126 reg = <0x0 0xff0b0000 0x1000>;
135 clock-names = "pclk", "hclk", "tx_clk"; 127 clock-names = "pclk", "hclk", "tx_clk";
136 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
137 #address-cells = <1>; 128 #address-cells = <1>;
138 #size-cells = <0>; 129 #size-cells = <0>;
139 }; 130 };
@@ -145,7 +136,6 @@
145 interrupts = <0 59 4>, <0 59 4>; 136 interrupts = <0 59 4>, <0 59 4>;
146 reg = <0x0 0xff0c0000 0x1000>; 137 reg = <0x0 0xff0c0000 0x1000>;
147 clock-names = "pclk", "hclk", "tx_clk"; 138 clock-names = "pclk", "hclk", "tx_clk";
148 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
149 #address-cells = <1>; 139 #address-cells = <1>;
150 #size-cells = <0>; 140 #size-cells = <0>;
151 }; 141 };
@@ -157,7 +147,6 @@
157 interrupts = <0 61 4>, <0 61 4>; 147 interrupts = <0 61 4>, <0 61 4>;
158 reg = <0x0 0xff0d0000 0x1000>; 148 reg = <0x0 0xff0d0000 0x1000>;
159 clock-names = "pclk", "hclk", "tx_clk"; 149 clock-names = "pclk", "hclk", "tx_clk";
160 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
161 #address-cells = <1>; 150 #address-cells = <1>;
162 #size-cells = <0>; 151 #size-cells = <0>;
163 }; 152 };
@@ -169,7 +158,6 @@
169 interrupts = <0 63 4>, <0 63 4>; 158 interrupts = <0 63 4>, <0 63 4>;
170 reg = <0x0 0xff0e0000 0x1000>; 159 reg = <0x0 0xff0e0000 0x1000>;
171 clock-names = "pclk", "hclk", "tx_clk"; 160 clock-names = "pclk", "hclk", "tx_clk";
172 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
173 #address-cells = <1>; 161 #address-cells = <1>;
174 #size-cells = <0>; 162 #size-cells = <0>;
175 }; 163 };
@@ -178,7 +166,6 @@
178 compatible = "xlnx,zynqmp-gpio-1.0"; 166 compatible = "xlnx,zynqmp-gpio-1.0";
179 status = "disabled"; 167 status = "disabled";
180 #gpio-cells = <0x2>; 168 #gpio-cells = <0x2>;
181 clocks = <&misc_clk>;
182 interrupt-parent = <&gic>; 169 interrupt-parent = <&gic>;
183 interrupts = <0 16 4>; 170 interrupts = <0 16 4>;
184 interrupt-controller; 171 interrupt-controller;
@@ -186,19 +173,12 @@
186 reg = <0x0 0xff0a0000 0x1000>; 173 reg = <0x0 0xff0a0000 0x1000>;
187 }; 174 };
188 175
189 i2c_clk: i2c_clk {
190 compatible = "fixed-clock";
191 #clock-cells = <0x0>;
192 clock-frequency = <111111111>;
193 };
194
195 i2c0: i2c@ff020000 { 176 i2c0: i2c@ff020000 {
196 compatible = "cdns,i2c-r1p10"; 177 compatible = "cdns,i2c-r1p10";
197 status = "disabled"; 178 status = "disabled";
198 interrupt-parent = <&gic>; 179 interrupt-parent = <&gic>;
199 interrupts = <0 17 4>; 180 interrupts = <0 17 4>;
200 reg = <0x0 0xff020000 0x1000>; 181 reg = <0x0 0xff020000 0x1000>;
201 clocks = <&i2c_clk>;
202 #address-cells = <1>; 182 #address-cells = <1>;
203 #size-cells = <0>; 183 #size-cells = <0>;
204 }; 184 };
@@ -209,24 +189,16 @@
209 interrupt-parent = <&gic>; 189 interrupt-parent = <&gic>;
210 interrupts = <0 18 4>; 190 interrupts = <0 18 4>;
211 reg = <0x0 0xff030000 0x1000>; 191 reg = <0x0 0xff030000 0x1000>;
212 clocks = <&i2c_clk>;
213 #address-cells = <1>; 192 #address-cells = <1>;
214 #size-cells = <0>; 193 #size-cells = <0>;
215 }; 194 };
216 195
217 sata_clk: sata_clk {
218 compatible = "fixed-clock";
219 #clock-cells = <0>;
220 clock-frequency = <75000000>;
221 };
222
223 sata: ahci@fd0c0000 { 196 sata: ahci@fd0c0000 {
224 compatible = "ceva,ahci-1v84"; 197 compatible = "ceva,ahci-1v84";
225 status = "disabled"; 198 status = "disabled";
226 reg = <0x0 0xfd0c0000 0x2000>; 199 reg = <0x0 0xfd0c0000 0x2000>;
227 interrupt-parent = <&gic>; 200 interrupt-parent = <&gic>;
228 interrupts = <0 133 4>; 201 interrupts = <0 133 4>;
229 clocks = <&sata_clk>;
230 }; 202 };
231 203
232 sdhci0: sdhci@ff160000 { 204 sdhci0: sdhci@ff160000 {
@@ -236,7 +208,6 @@
236 interrupts = <0 48 4>; 208 interrupts = <0 48 4>;
237 reg = <0x0 0xff160000 0x1000>; 209 reg = <0x0 0xff160000 0x1000>;
238 clock-names = "clk_xin", "clk_ahb"; 210 clock-names = "clk_xin", "clk_ahb";
239 clocks = <&misc_clk>, <&misc_clk>;
240 }; 211 };
241 212
242 sdhci1: sdhci@ff170000 { 213 sdhci1: sdhci@ff170000 {
@@ -246,7 +217,6 @@
246 interrupts = <0 49 4>; 217 interrupts = <0 49 4>;
247 reg = <0x0 0xff170000 0x1000>; 218 reg = <0x0 0xff170000 0x1000>;
248 clock-names = "clk_xin", "clk_ahb"; 219 clock-names = "clk_xin", "clk_ahb";
249 clocks = <&misc_clk>, <&misc_clk>;
250 }; 220 };
251 221
252 smmu: smmu@fd800000 { 222 smmu: smmu@fd800000 {
@@ -268,7 +238,6 @@
268 interrupts = <0 19 4>; 238 interrupts = <0 19 4>;
269 reg = <0x0 0xff040000 0x1000>; 239 reg = <0x0 0xff040000 0x1000>;
270 clock-names = "ref_clk", "pclk"; 240 clock-names = "ref_clk", "pclk";
271 clocks = <&misc_clk &misc_clk>;
272 #address-cells = <1>; 241 #address-cells = <1>;
273 #size-cells = <0>; 242 #size-cells = <0>;
274 }; 243 };
@@ -280,7 +249,6 @@
280 interrupts = <0 20 4>; 249 interrupts = <0 20 4>;
281 reg = <0x0 0xff050000 0x1000>; 250 reg = <0x0 0xff050000 0x1000>;
282 clock-names = "ref_clk", "pclk"; 251 clock-names = "ref_clk", "pclk";
283 clocks = <&misc_clk &misc_clk>;
284 #address-cells = <1>; 252 #address-cells = <1>;
285 #size-cells = <0>; 253 #size-cells = <0>;
286 }; 254 };
@@ -291,7 +259,6 @@
291 interrupt-parent = <&gic>; 259 interrupt-parent = <&gic>;
292 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 260 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
293 reg = <0x0 0xff110000 0x1000>; 261 reg = <0x0 0xff110000 0x1000>;
294 clocks = <&misc_clk>;
295 timer-width = <32>; 262 timer-width = <32>;
296 }; 263 };
297 264
@@ -301,7 +268,6 @@
301 interrupt-parent = <&gic>; 268 interrupt-parent = <&gic>;
302 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 269 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
303 reg = <0x0 0xff120000 0x1000>; 270 reg = <0x0 0xff120000 0x1000>;
304 clocks = <&misc_clk>;
305 timer-width = <32>; 271 timer-width = <32>;
306 }; 272 };
307 273
@@ -311,7 +277,6 @@
311 interrupt-parent = <&gic>; 277 interrupt-parent = <&gic>;
312 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 278 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
313 reg = <0x0 0xff130000 0x1000>; 279 reg = <0x0 0xff130000 0x1000>;
314 clocks = <&misc_clk>;
315 timer-width = <32>; 280 timer-width = <32>;
316 }; 281 };
317 282
@@ -321,7 +286,6 @@
321 interrupt-parent = <&gic>; 286 interrupt-parent = <&gic>;
322 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 287 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
323 reg = <0x0 0xff140000 0x1000>; 288 reg = <0x0 0xff140000 0x1000>;
324 clocks = <&misc_clk>;
325 timer-width = <32>; 289 timer-width = <32>;
326 }; 290 };
327 291
@@ -332,7 +296,6 @@
332 interrupts = <0 21 4>; 296 interrupts = <0 21 4>;
333 reg = <0x0 0xff000000 0x1000>; 297 reg = <0x0 0xff000000 0x1000>;
334 clock-names = "uart_clk", "pclk"; 298 clock-names = "uart_clk", "pclk";
335 clocks = <&misc_clk &misc_clk>;
336 }; 299 };
337 300
338 uart1: serial@ff010000 { 301 uart1: serial@ff010000 {
@@ -342,7 +305,6 @@
342 interrupts = <0 22 4>; 305 interrupts = <0 22 4>;
343 reg = <0x0 0xff010000 0x1000>; 306 reg = <0x0 0xff010000 0x1000>;
344 clock-names = "uart_clk", "pclk"; 307 clock-names = "uart_clk", "pclk";
345 clocks = <&misc_clk &misc_clk>;
346 }; 308 };
347 309
348 usb0: usb@fe200000 { 310 usb0: usb@fe200000 {
@@ -352,7 +314,6 @@
352 interrupts = <0 65 4>; 314 interrupts = <0 65 4>;
353 reg = <0x0 0xfe200000 0x40000>; 315 reg = <0x0 0xfe200000 0x40000>;
354 clock-names = "clk_xin", "clk_ahb"; 316 clock-names = "clk_xin", "clk_ahb";
355 clocks = <&misc_clk>, <&misc_clk>;
356 }; 317 };
357 318
358 usb1: usb@fe300000 { 319 usb1: usb@fe300000 {
@@ -362,13 +323,11 @@
362 interrupts = <0 70 4>; 323 interrupts = <0 70 4>;
363 reg = <0x0 0xfe300000 0x40000>; 324 reg = <0x0 0xfe300000 0x40000>;
364 clock-names = "clk_xin", "clk_ahb"; 325 clock-names = "clk_xin", "clk_ahb";
365 clocks = <&misc_clk>, <&misc_clk>;
366 }; 326 };
367 327
368 watchdog0: watchdog@fd4d0000 { 328 watchdog0: watchdog@fd4d0000 {
369 compatible = "cdns,wdt-r1p2"; 329 compatible = "cdns,wdt-r1p2";
370 status = "disabled"; 330 status = "disabled";
371 clocks= <&misc_clk>;
372 interrupt-parent = <&gic>; 331 interrupt-parent = <&gic>;
373 interrupts = <0 52 1>; 332 interrupts = <0 52 1>;
374 reg = <0x0 0xfd4d0000 0x1000>; 333 reg = <0x0 0xfd4d0000 0x1000>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-13 11:14:50 -0400