diff options
-rw-r--r-- | drivers/gpu/drm/i915/intel_lrc.c | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 8 |
2 files changed, 0 insertions, 18 deletions
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index d4961fa20c73..beabc17e7c8a 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c | |||
@@ -979,18 +979,8 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, | |||
979 | uint32_t *batch, | 979 | uint32_t *batch, |
980 | uint32_t index) | 980 | uint32_t index) |
981 | { | 981 | { |
982 | struct drm_i915_private *dev_priv = engine->i915; | ||
983 | uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); | 982 | uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); |
984 | 983 | ||
985 | /* | ||
986 | * WaDisableLSQCROPERFforOCL:kbl | ||
987 | * This WA is implemented in skl_init_clock_gating() but since | ||
988 | * this batch updates GEN8_L3SQCREG4 with default value we need to | ||
989 | * set this bit here to retain the WA during flush. | ||
990 | */ | ||
991 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) | ||
992 | l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS; | ||
993 | |||
994 | wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | | 984 | wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | |
995 | MI_SRM_LRM_GLOBAL_GTT)); | 985 | MI_SRM_LRM_GLOBAL_GTT)); |
996 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); | 986 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index aeb637dc1fdf..91cb4c422ad5 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c | |||
@@ -1095,14 +1095,6 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine) | |||
1095 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | 1095 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
1096 | HDC_FENCE_DEST_SLM_DISABLE); | 1096 | HDC_FENCE_DEST_SLM_DISABLE); |
1097 | 1097 | ||
1098 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes | ||
1099 | * involving this register should also be added to WA batch as required. | ||
1100 | */ | ||
1101 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) | ||
1102 | /* WaDisableLSQCROPERFforOCL:kbl */ | ||
1103 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | ||
1104 | GEN8_LQSC_RO_PERF_DIS); | ||
1105 | |||
1106 | /* WaToEnableHwFixForPushConstHWBug:kbl */ | 1098 | /* WaToEnableHwFixForPushConstHWBug:kbl */ |
1107 | if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER)) | 1099 | if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER)) |
1108 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | 1100 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, |