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-rw-r--r--drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c19
1 files changed, 16 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index cdd1d6b7b9f2..4e9ea50141bd 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -790,9 +790,22 @@ bool dce80_validate_bandwidth(
790 struct dc *dc, 790 struct dc *dc,
791 struct dc_state *context) 791 struct dc_state *context)
792{ 792{
793 /* TODO implement when needed but for now hardcode max value*/ 793 int i;
794 context->bw.dce.dispclk_khz = 681000; 794 bool at_least_one_pipe = false;
795 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; 795
796 for (i = 0; i < dc->res_pool->pipe_count; i++) {
797 if (context->res_ctx.pipe_ctx[i].stream)
798 at_least_one_pipe = true;
799 }
800
801 if (at_least_one_pipe) {
802 /* TODO implement when needed but for now hardcode max value*/
803 context->bw.dce.dispclk_khz = 681000;
804 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
805 } else {
806 context->bw.dce.dispclk_khz = 0;
807 context->bw.dce.yclk_khz = 0;
808 }
796 809
797 return true; 810 return true;
798} 811}