diff options
| -rw-r--r-- | drivers/mtd/spi-nor/fsl-quadspi.c | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index b1cc182c46a1..1c7308c2c77d 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c | |||
| @@ -57,7 +57,9 @@ | |||
| 57 | 57 | ||
| 58 | #define QUADSPI_BUF3CR 0x1c | 58 | #define QUADSPI_BUF3CR 0x1c |
| 59 | #define QUADSPI_BUF3CR_ALLMST_SHIFT 31 | 59 | #define QUADSPI_BUF3CR_ALLMST_SHIFT 31 |
| 60 | #define QUADSPI_BUF3CR_ALLMST (1 << QUADSPI_BUF3CR_ALLMST_SHIFT) | 60 | #define QUADSPI_BUF3CR_ALLMST_MASK (1 << QUADSPI_BUF3CR_ALLMST_SHIFT) |
| 61 | #define QUADSPI_BUF3CR_ADATSZ_SHIFT 8 | ||
| 62 | #define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT) | ||
| 61 | 63 | ||
| 62 | #define QUADSPI_BFGENCR 0x20 | 64 | #define QUADSPI_BFGENCR 0x20 |
| 63 | #define QUADSPI_BFGENCR_PAR_EN_SHIFT 16 | 65 | #define QUADSPI_BFGENCR_PAR_EN_SHIFT 16 |
| @@ -198,18 +200,21 @@ struct fsl_qspi_devtype_data { | |||
| 198 | enum fsl_qspi_devtype devtype; | 200 | enum fsl_qspi_devtype devtype; |
| 199 | int rxfifo; | 201 | int rxfifo; |
| 200 | int txfifo; | 202 | int txfifo; |
| 203 | int ahb_buf_size; | ||
| 201 | }; | 204 | }; |
| 202 | 205 | ||
| 203 | static struct fsl_qspi_devtype_data vybrid_data = { | 206 | static struct fsl_qspi_devtype_data vybrid_data = { |
| 204 | .devtype = FSL_QUADSPI_VYBRID, | 207 | .devtype = FSL_QUADSPI_VYBRID, |
| 205 | .rxfifo = 128, | 208 | .rxfifo = 128, |
| 206 | .txfifo = 64 | 209 | .txfifo = 64, |
| 210 | .ahb_buf_size = 1024 | ||
| 207 | }; | 211 | }; |
| 208 | 212 | ||
| 209 | static struct fsl_qspi_devtype_data imx6sx_data = { | 213 | static struct fsl_qspi_devtype_data imx6sx_data = { |
| 210 | .devtype = FSL_QUADSPI_IMX6SX, | 214 | .devtype = FSL_QUADSPI_IMX6SX, |
| 211 | .rxfifo = 128, | 215 | .rxfifo = 128, |
| 212 | .txfifo = 512 | 216 | .txfifo = 512, |
| 217 | .ahb_buf_size = 1024 | ||
| 213 | }; | 218 | }; |
| 214 | 219 | ||
| 215 | #define FSL_QSPI_MAX_CHIP 4 | 220 | #define FSL_QSPI_MAX_CHIP 4 |
| @@ -584,7 +589,12 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q) | |||
| 584 | writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR); | 589 | writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR); |
| 585 | writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR); | 590 | writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR); |
| 586 | writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR); | 591 | writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR); |
| 587 | writel(QUADSPI_BUF3CR_ALLMST, base + QUADSPI_BUF3CR); | 592 | /* |
| 593 | * Set ADATSZ with the maximum AHB buffer size to improve the | ||
| 594 | * read performance. | ||
| 595 | */ | ||
| 596 | writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8) | ||
| 597 | << QUADSPI_BUF3CR_ADATSZ_SHIFT), base + QUADSPI_BUF3CR); | ||
| 588 | 598 | ||
| 589 | /* We only use the buffer3 */ | 599 | /* We only use the buffer3 */ |
| 590 | writel(0, base + QUADSPI_BUF0IND); | 600 | writel(0, base + QUADSPI_BUF0IND); |
