22 files changed, 258 insertions, 86 deletions

diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
index fa05e347262f..06b819db51b1 100644
--- a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
+++ b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
@@ -533,6 +533,7 @@ static void nicvf_rcv_queue_config(struct nicvf *nic, struct queue_set *qs,
                 nicvf_config_vlan_stripping(nic, nic->netdev->features);
 
         /* Enable Receive queue */
+        memset(&rq_cfg, 0, sizeof(struct rq_cfg));
         rq_cfg.ena = 1;
         rq_cfg.tcp_ena = 0;
         nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, *(u64 *)&rq_cfg);
@@ -565,6 +566,7 @@ void nicvf_cmp_queue_config(struct nicvf *nic, struct queue_set *qs,
                               qidx, (u64)(cq->dmem.phys_base));
 
         /* Enable Completion queue */
+        memset(&cq_cfg, 0, sizeof(struct cq_cfg));
         cq_cfg.ena = 1;
         cq_cfg.reset = 0;
         cq_cfg.caching = 0;
@@ -613,6 +615,7 @@ static void nicvf_snd_queue_config(struct nicvf *nic, struct queue_set *qs,
                               qidx, (u64)(sq->dmem.phys_base));
 
         /* Enable send queue  & set queue size */
+        memset(&sq_cfg, 0, sizeof(struct sq_cfg));
         sq_cfg.ena = 1;
         sq_cfg.reset = 0;
         sq_cfg.ldwb = 0;
@@ -649,6 +652,7 @@ static void nicvf_rbdr_config(struct nicvf *nic, struct queue_set *qs,
 
         /* Enable RBDR  & set queue size */
         /* Buffer size should be in multiples of 128 bytes */
+        memset(&rbdr_cfg, 0, sizeof(struct rbdr_cfg));
         rbdr_cfg.ena = 1;
         rbdr_cfg.reset = 0;
         rbdr_cfg.ldwb = 0;
diff --git a/drivers/net/ethernet/ezchip/nps_enet.c b/drivers/net/ethernet/ezchip/nps_enet.c
index 1f23845a0694..085f9125cf42 100644
--- a/drivers/net/ethernet/ezchip/nps_enet.c
+++ b/drivers/net/ethernet/ezchip/nps_enet.c
@@ -145,7 +145,7 @@ static void nps_enet_tx_handler(struct net_device *ndev)
         u32 tx_ctrl_nt = (tx_ctrl_value & TX_CTL_NT_MASK) >> TX_CTL_NT_SHIFT;
 
         /* Check if we got TX */
-        if (!priv->tx_packet_sent || tx_ctrl_ct)
+        if (!priv->tx_skb || tx_ctrl_ct)
                 return;
 
         /* Ack Tx ctrl register */
@@ -160,7 +160,7 @@ static void nps_enet_tx_handler(struct net_device *ndev)
         }
 
         dev_kfree_skb(priv->tx_skb);
-        priv->tx_packet_sent = false;
+        priv->tx_skb = NULL;
 
         if (netif_queue_stopped(ndev))
                 netif_wake_queue(ndev);
@@ -183,6 +183,9 @@ static int nps_enet_poll(struct napi_struct *napi, int budget)
         work_done = nps_enet_rx_handler(ndev);
         if (work_done < budget) {
                 u32 buf_int_enable_value = 0;
+                u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL);
+                u32 tx_ctrl_ct =
+                        (tx_ctrl_value & TX_CTL_CT_MASK) >> TX_CTL_CT_SHIFT;
 
                 napi_complete(napi);
 
@@ -192,6 +195,18 @@ static int nps_enet_poll(struct napi_struct *napi, int budget)
 
                 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE,
                                  buf_int_enable_value);
+
+                /* in case we will get a tx interrupt while interrupts
+                 * are masked, we will lose it since the tx is edge interrupt.
+                 * specifically, while executing the code section above,
+                 * between nps_enet_tx_handler and the interrupts enable, all
+                 * tx requests will be stuck until we will get an rx interrupt.
+                 * the two code lines below will solve this situation by
+                 * re-adding ourselves to the poll list.
+                 */
+
+                if (priv->tx_skb && !tx_ctrl_ct)
+                        napi_reschedule(napi);
         }
 
         return work_done;
@@ -217,7 +232,7 @@ static irqreturn_t nps_enet_irq_handler(s32 irq, void *dev_instance)
         u32 tx_ctrl_ct = (tx_ctrl_value & TX_CTL_CT_MASK) >> TX_CTL_CT_SHIFT;
         u32 rx_ctrl_cr = (rx_ctrl_value & RX_CTL_CR_MASK) >> RX_CTL_CR_SHIFT;
 
-        if ((!tx_ctrl_ct && priv->tx_packet_sent) || rx_ctrl_cr)
+        if ((!tx_ctrl_ct && priv->tx_skb) || rx_ctrl_cr)
                 if (likely(napi_schedule_prep(&priv->napi))) {
                         nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
                         __napi_schedule(&priv->napi);
@@ -387,8 +402,6 @@ static void nps_enet_send_frame(struct net_device *ndev,
         /* Write the length of the Frame */
         tx_ctrl_value |= length << TX_CTL_NT_SHIFT;
 
-        /* Indicate SW is done */
-        priv->tx_packet_sent = true;
         tx_ctrl_value |= NPS_ENET_ENABLE << TX_CTL_CT_SHIFT;
         /* Send Frame */
         nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, tx_ctrl_value);
@@ -465,7 +478,7 @@ static s32 nps_enet_open(struct net_device *ndev)
         s32 err;
 
         /* Reset private variables */
-        priv->tx_packet_sent = false;
+        priv->tx_skb = NULL;
         priv->ge_mac_cfg_2_value = 0;
         priv->ge_mac_cfg_3_value = 0;
 
@@ -534,6 +547,11 @@ static netdev_tx_t nps_enet_start_xmit(struct sk_buff *skb,
 
         priv->tx_skb = skb;
 
+        /* make sure tx_skb is actually written to the memory
+         * before the HW is informed and the IRQ is fired.
+         */
+        wmb();
+
         nps_enet_send_frame(ndev, skb);
 
         return NETDEV_TX_OK;
diff --git a/drivers/net/ethernet/ezchip/nps_enet.h b/drivers/net/ethernet/ezchip/nps_enet.h
index d0cab600bce8..3939ca20cc9f 100644
--- a/drivers/net/ethernet/ezchip/nps_enet.h
+++ b/drivers/net/ethernet/ezchip/nps_enet.h
@@ -165,14 +165,12 @@
  * struct nps_enet_priv - Storage of ENET's private information.
  * @regs_base:      Base address of ENET memory-mapped control registers.
  * @irq:            For RX/TX IRQ number.
- * @tx_packet_sent: SW indication if frame is being sent.
  * @tx_skb:         socket buffer of sent frame.
  * @napi:           Structure for NAPI.
  */